JP3168622B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3168622B2 JP3168622B2 JP19634391A JP19634391A JP3168622B2 JP 3168622 B2 JP3168622 B2 JP 3168622B2 JP 19634391 A JP19634391 A JP 19634391A JP 19634391 A JP19634391 A JP 19634391A JP 3168622 B2 JP3168622 B2 JP 3168622B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon film
- film
- insulating film
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
浅いベース層を有するバイポーラ型トランジスタに関す
る。The present invention relates to a semiconductor device, and more particularly to a bipolar transistor having a shallow base layer.
【０００２】[0002]
【従来の技術】従来の半導体装置は図４に示すように、
Ｐ型シリコン基板上に設けたＮ型埋込コレクタ層２及び
Ｎ型のエピタキシャル成長層３と、エピタキシャル成長
層３上に開口部を有する窒化シリコン膜５と、ベース引
出し電極となるＰ型の多結晶シリコン膜６と、開口部の
エピタキシャル成長層３上に形成されたＰ型のベース領
域１０ａと、ベース領域１０ａとＰ型多結晶シリコン膜
６とを接続するＰ型多結晶シリコン膜１０ｂと、Ｐ型多
結晶シリコン膜６を覆う酸化シリコン膜７，８，と、エ
ミッタ領域１３と、エミッタ電極を構成するＮ型の多結
晶シリコン膜１２及びアルミニウム電極１４とにより構
成されていた。（特願平２−９８１１６号参照）ここ
で、特にベース領域１０ａとＰ型多結晶シリコン膜１０
ｂとは分子線エピタキシャル成長法により同時にＰ型不
純物原子を添加し形成されていた。2. Description of the Related Art As shown in FIG.
N-type buried collector layer 2 and N-type epitaxial growth layer 3 provided on a P-type silicon substrate; silicon nitride film 5 having an opening on epitaxial growth layer 3; A P-type base region 10a formed on the epitaxial growth layer 3 in the opening; a P-type polycrystalline silicon film 10b connecting the base region 10a and the P-type polycrystalline silicon film 6; It was composed of silicon oxide films 7, 8 covering the crystalline silicon film 6, an emitter region 13, an N-type polycrystalline silicon film 12 and an aluminum electrode 14 constituting an emitter electrode. (See Japanese Patent Application No. 2-98116) Here, in particular, the base region 10a and the P-type polycrystalline silicon film 10
b was formed by simultaneously adding P-type impurity atoms by molecular beam epitaxial growth.
【０００３】[0003]
【発明が解決しようとする課題】この従来の半導体装置
では、厚さが０．１μｍ以下のベース領域を安定に形成
するため、分子線エピタキシャル成長法を採用してベー
ス領域１０ａを選択成長させると同時にベース引出し用
の多結晶シリコン膜６と接続するＰ型多結晶シリコン膜
１０ｂを形成していた。この構成ではベース領域１０ａ
とＰ型多結晶シリコン膜１０ｂの不純物濃度が同じであ
り、接続用のＰ型多結晶シリコン膜１０ｂの膜厚つまり
ベース領域１０ａとベース引出し用多結晶シリコン膜６
との距離が大きくなるとベース抵抗が増大する。In this conventional semiconductor device, in order to stably form a base region having a thickness of 0.1 μm or less, the base region 10a is selectively grown by employing a molecular beam epitaxial growth method. The P-type polycrystalline silicon film 10b connected to the base-leading polycrystalline silicon film 6 was formed. In this configuration, the base region 10a
And the P-type polycrystalline silicon film 10b have the same impurity concentration, and the thickness of the connecting P-type polycrystalline silicon film 10b, that is, the base region 10a and the base-leading polycrystalline silicon film 6
The base resistance increases as the distance from the base increases.
【０００４】また、ベース領域を浅く形成すると、エピ
タキシャル成長層３から成長するベース領域１０ａと、
ベース引き出し用のＰ型多結晶シリコン膜６から下方に
成長するＰ型多結晶シリコン膜１０ｂとが接しなくなる
という問題がある。When the base region is formed shallow, a base region 10a grown from the epitaxial growth layer 3 is formed.
There is a problem that the P-type polycrystalline silicon film 10b that grows downward from the P-type polycrystalline silicon film 6 for drawing out the base does not come in contact with the base.
【０００５】また、窒化シリコン膜５を浅くし、ベース
領域１０ａとＰ型多結晶シリコン膜１０ｂを接続し、ベ
ース抵抗の低減を行うと窒化シリコン膜５の絶縁性が低
下し、ベース引出し用Ｐ型多結晶シリコン膜６とエピタ
キシャル成長層３が短絡するという問題があった。Further, when the silicon nitride film 5 is made shallow, the base region 10a is connected to the P-type polycrystalline silicon film 10b, and the base resistance is reduced, the insulating property of the silicon nitride film 5 is reduced, and the base lead P There is a problem that the type polycrystalline silicon film 6 and the epitaxial growth layer 3 are short-circuited.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
一導電型半導体基板上に設けた逆導電型のコレクタ領域
と、前記コレクタ領域上に順次積層して設けた絶縁膜及
び一導電型の第１の多結晶シリコン膜と、前記第１の多
結晶シリコン膜及び絶縁膜を貫通して設け且つ前記絶縁
膜の側面をエッチングして第１の多結晶シリコン膜の下
面の一部を露出させた開口部と、前記開口部のコレクタ
領域上に設けた一導電型のエピタキシャル成長させたベ
ース層と、前記第１の多結晶シリコン膜の下面に接続し
て設けた高濃度一導電型の第２の多結晶シリコン膜と、
前記コレクタ領域上に設けて前記第２の多結晶シリコン
膜と接続する一導電型の第３の多結晶シリコン膜と、前
記開口部の第１，第２及び第３の多結晶シリコン膜の側
壁に設けた絶縁性スペーサと、前記スペーサの内側の前
記ベース層の表面に設けた逆導電型のエミッタ領域とを
備えている。According to the present invention, there is provided a semiconductor device comprising:
A collector region of the opposite conductivity type provided on the semiconductor substrate of one conductivity type, an insulating film and a first polycrystalline silicon film of one conductivity type provided sequentially on the collector region, and the first polycrystal An opening formed through the silicon film and the insulating film and etching a side surface of the insulating film to expose a part of a lower surface of the first polycrystalline silicon film; and a collector region of the opening. One conductivity type epitaxially grown
And over scan layer and a second polycrystalline silicon film of high concentration first conductivity type which is provided to connect to the lower surface of the first polycrystalline silicon film,
A third polysilicon film of one conductivity type provided on the collector region and connected to the second polysilicon film, and sidewalls of the first, second, and third polysilicon films in the opening; And an emitter region of the opposite conductivity type provided on the surface of the base layer inside the spacer.
【０００７】本発明の半導体装置の製造方法は、一導電
型半導体基板上に逆導電型のコレクタ領域を形成する工
程と、前記コレクタ領域の上に第１及び第２の絶縁膜と
一導電型の第１の多結晶シリコン膜と第３の絶縁膜を順
次堆積して設ける工程と、前記第３の絶縁膜及び第１の
多結晶シリコン膜を選択的に順次異方性エッチングして
開口部を設け前記開口部を含む表面に第４の絶縁膜を堆
積してエッチバックし前記開口部の側壁にのみ前記第４
の絶縁膜を残して第１のスペーサを形成する工程と、前
記第４及び第１の絶縁膜をマスクとして前記第２の絶縁
膜をエッチングし前記第１の多結晶シリコン膜の下面を
露出させる工程と、前記第１の多結晶シリコン膜の下面
に高濃度一導電型の第２の多結晶シリコン膜を選択成長
させる工程と、前記開口部の第１の絶縁膜をエッチング
除去した後前記コレクタ領域の表面に一導電型のベース
層を成長させると同時に前記第２の多結晶シリコン膜の
表面に一導電型の第３の多結晶シリコン膜を堆積して前
記ベース層と接続させる工程と、前記開口部を含む表面
に第５の絶縁膜を堆積してエッチバックし前記開口部の
側壁にのみ第５の絶縁膜を残して第２のスペーサを形成
する工程と、前記開口部を含む表面に逆導電型の多結晶
シリコン膜を堆積し、熱処理により前記ベース層の表面
に逆導電型不純物を拡散してエミッタ領域を形成する工
程とを含んで構成される。According to the method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a collector region of the opposite conductivity type on a semiconductor substrate of one conductivity type, and forming first and second insulating films on the collector region. Sequentially depositing and providing a first polycrystalline silicon film and a third insulating film; and selectively anisotropically etching the third insulating film and the first polycrystalline silicon film to form an opening. A fourth insulating film is deposited on the surface including the opening and etched back, and the fourth insulating film is deposited only on the side wall of the opening.
Forming a first spacer while leaving the insulating film, and etching the second insulating film using the fourth and first insulating films as masks to expose the lower surface of the first polycrystalline silicon film. A step of selectively growing a high-concentration one-conductivity-type second polycrystalline silicon film on a lower surface of the first polycrystalline silicon film; and a step of etching and removing the first insulating film in the opening. One conductivity type base on the surface of the area
Simultaneously growing a layer , depositing a third polycrystalline silicon film of one conductivity type on the surface of the second polycrystalline silicon film and connecting the third polycrystalline silicon film to the base layer ; Depositing and etching back an insulating film to form a second spacer while leaving a fifth insulating film only on the side wall of the opening; and a reverse-conductivity-type polycrystalline silicon film on the surface including the opening. Forming an emitter region by diffusing a reverse conductivity type impurity into the surface of the base layer by heat treatment.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００９】図１（ａ）〜（ｃ）及び図２（ａ）〜
（ｃ）は本発明の第１の実施例の製造方法を説明するた
めの工程順に示した半導体チップの断面図である。1 (a) to 1 (c) and 2 (a) to 2 (a)
4C is a sectional view of the semiconductor chip shown in order of process for explaining the manufacturing method of the first example of the present invention; FIG.
【００１０】まず、図１（ａ）に示すように、Ｐ型シリ
コン基板１の上に例えばヒ素原子を含むＮ型の埋込コレ
クタ層２を選択的に形成し、埋込コレクタ層２を含む表
面にＮ型のエピタキシャル成長層３を０．８μｍの厚さ
に形成する。次に、エピタキシャル成長層３の表面を熱
酸化して厚さ５０ｎｍの酸化シリコン膜４を形成し、酸
化シリコン膜４の上にＣＶＤ法により窒化シリコン膜５
を０．１５μｍの厚さに堆積する。次いで、ホウ素原子
を約１０19〜１０20ｃｍ-3の濃度に添加したＰ型多結晶
シリコン膜６を０．２μｍの厚さに堆積し、Ｐ型多結晶
シリコン膜６の上に酸化シリコン膜７をＣＶＤ法により
０．２μｍの厚さに堆積する。First, as shown in FIG. 1A, an N-type buried collector layer 2 containing, for example, arsenic atoms is selectively formed on a P-type silicon substrate 1, and includes the buried collector layer 2. An N-type epitaxial growth layer 3 is formed on the surface to a thickness of 0.8 μm. Next, the surface of the epitaxial growth layer 3 is thermally oxidized to form a silicon oxide film 4 having a thickness of 50 nm, and the silicon nitride film 5 is formed on the silicon oxide film 4 by CVD.
Is deposited to a thickness of 0.15 μm. Then, a P-type polycrystalline silicon film 6 with the addition of boron atoms to a concentration of about 10 19 ~10 20 cm -3 is deposited to a thickness of 0.2 [mu] m, a silicon oxide film on the P-type polycrystalline silicon film 6 7 is deposited to a thickness of 0.2 μm by the CVD method.
【００１１】次に、図１（ｂ）に示すように、写真蝕刻
法により酸化シリコン膜７とＰ型多結晶シリコン膜６を
選択的に異方性エッチングして開口部を設ける。Next, as shown in FIG. 1B, openings are formed by selectively anisotropically etching the silicon oxide film 7 and the P-type polycrystalline silicon film 6 by photolithography.
【００１２】次に、図１（ｃ）に示すように、開口部を
含む表面に酸化シリコン膜を０．２μｍの厚さに堆積
し、異方性エッチングによりエッチバックし開口部の側
壁にのみ酸化シリコン膜８を残して第１のスペーサを形
成する。次に、リン酸により開口部の窒化シリコン膜５
の側面を横方向へ０．４μｍの幅にエッチングしてＰ型
多結晶シリコン膜６の下面を露出させる。次に、分子線
エピタキシャル成長法によりホウ原子を３×１０19ｃｍ
-3の濃度に添加したＰ型多結晶シリコン膜９をＰ型多結
晶シリコン膜６の下面に選択成長させ０．１μｍの厚さ
に形成する。このＰ型シリコン膜９の成長時にはエピタ
キシャル成長層３の上は酸化シリコン膜４で覆われてい
るためシリコン膜が成長することは無い。Next, as shown in FIG. 1C, a silicon oxide film is deposited to a thickness of 0.2 μm on the surface including the opening and etched back by anisotropic etching to form only the side wall of the opening. A first spacer is formed while leaving the silicon oxide film 8. Next, the silicon nitride film 5 in the opening is
Is laterally etched to a width of 0.4 μm to expose the lower surface of P-type polycrystalline silicon film 6. Next, boron atoms were grown to 3 × 10 19 cm by molecular beam epitaxy.
A P-type polycrystalline silicon film 9 doped to a concentration of -3 is selectively grown on the lower surface of the P-type polycrystalline silicon film 6 to have a thickness of 0.1 μm. During the growth of the P-type silicon film 9, the silicon film does not grow because the upper part of the epitaxial growth layer 3 is covered with the silicon oxide film 4.
【００１３】次に、図２（ａ）に示すように、窒化シリ
コン膜５をマスクとして開口部の酸化シリコン膜４を弗
化水素酸によりエッチングして除去し、露出したエピタ
キシャル成長層３の表面及び多結晶シリコン膜９の表面
に分子線エピタキシャル成長法で５×１０18ｃｍ-3のホ
ウ素原子を添加した厚さ７０ｎｍのベース領域１０ａお
よび厚さ３０ｎｍのＰ型多結晶シリコン膜１０ｂを同時
に成長する。ここで、分子線エピタキシャル成長法の代
りに高真空ＣＶＤ成長法を用いても良い。Next, as shown in FIG. 2A, the silicon oxide film 4 in the opening is removed by etching with hydrofluoric acid using the silicon nitride film 5 as a mask, and the exposed surface of the epitaxial growth layer 3 and On the surface of the polycrystalline silicon film 9, a base region 10 a having a thickness of 70 nm to which boron atoms of 5 × 10 18 cm −3 are added and a P-type polycrystalline silicon film 10 b having a thickness of 30 nm are simultaneously grown by molecular beam epitaxy. Here, a high vacuum CVD growth method may be used instead of the molecular beam epitaxial growth method.
【００１４】次に、図２（ｂ）に示すように、開口部を
含む表面に減圧ＣＶＤ法により酸化シリコン膜を０．２
μｍの厚さに堆積して異方性エッチングによりエッチバ
ックし開口部の側壁にのみ酸化シリコン膜１１を残して
第２のスペーサを形成する。Next, as shown in FIG. 2B, a silicon oxide film is formed on the surface including the opening by a low pressure CVD method.
The second spacer is formed by depositing a thickness of μm and etching back by anisotropic etching, leaving the silicon oxide film 11 only on the side wall of the opening.
【００１５】次に、図２（ｃ）に示すように、開口部を
含む表面にＣＶＤ法により多結晶シリコン膜を０．２μ
ｍの厚さに堆積してヒ素原子をイオン注入し、Ｎ型の多
結晶シリコン膜１２を形成し、熱処理によりＮ型多結晶
シリコン膜１２よりベース領域１０ａの表面に不純物を
拡散してエミッタ領域１３を形成する。次に、Ｎ型多結
晶シリコン膜１２上にアルミニウム層を堆積し、アルミ
ニウム層及びＮ型多結晶シリコン膜１２を選択的に順次
エッチングしてアルミニウム電極１４を形成する。Next, as shown in FIG. 2 (c), a polycrystalline silicon film is
arsenic atoms are ion-implanted to form an N-type polycrystalline silicon film 12, and impurities are diffused from the N-type polycrystalline silicon film 12 to the surface of the base region 10a by heat treatment to form an emitter region. 13 is formed. Next, an aluminum layer is deposited on the N-type polycrystalline silicon film 12, and the aluminum layer and the N-type polycrystalline silicon film 12 are selectively etched sequentially to form an aluminum electrode 14.
【００１６】ここで、ベース引き出し用のＰ型多結晶シ
リコン膜６とベース領域１０ａの間は高濃度のＰ型多結
晶シリコン膜９と低濃度のＰ型多結晶シリコン膜１０ｂ
とにより接続されているが、高抵抗の低濃度Ｐ型多結晶
シリコン膜１０ｂの幅は最小限に抑えられるために、ベ
ース抵抗が大きく増大することは無い。Here, a high-concentration P-type polycrystalline silicon film 9 and a low-concentration P-type polycrystalline silicon film 10b are provided between the base-leading P-type polycrystalline silicon film 6 and the base region 10a.
However, since the width of the high-resistance low-concentration P-type polycrystalline silicon film 10b is minimized, the base resistance does not greatly increase.
【００１７】本実施例ではベース引出し用のＰ型多結晶
シリコン膜６の下層絶縁膜として窒化シリコン膜５を用
いスペーサおよび上層絶縁膜として酸化シリコン膜８，
１１，７を用いたが、下層絶縁膜として酸化シリコン膜
を用いスペーサおよび上層絶縁膜として窒化シリコン膜
を用いても良く、また、これらの多層膜を使用しても良
い。The silicon oxide film 8 as a spacer and the upper insulating film a silicon nitride film 5 as the lower layer insulating film of the P-type polycrystalline silicon film 6 for base leading in this embodiment,
Although 11 and 7 are used, a silicon oxide film may be used as the lower insulating film, and a silicon nitride film may be used as the spacer and the upper insulating film, or a multilayer film of these may be used.
【００１８】図３は本発明の第２の実施例を示す半導体
チップ断面図である。FIG. 3 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【００１９】図３に示すように、ベース領域１５ａ及び
Ｐ型多結晶シリコン膜１５ｂがゲルマニウム原子をシリ
コン中に添加したシリコンゲルマニウム混晶にホウ素原
子を添加して形成した以外は第１の実施例と同様の構成
を有している。バイボーラトランジスタの高性能化には
ベース幅を薄くすることが必要であるが、コレクタベー
ス耐圧の劣化を防止するために、不純物原子の濃度を高
く設定するため、ｈFE特性が低下する。このｈFE低下に
対応するため、シリコンゲルマニウム混晶でベース領域
を構成することは有効である。このようにベース薄膜化
のためにベース領域１５ａの幅を４０ｎｍとした場合で
も、本実施例では高濃度のＰ型多結晶シリコン膜９を
０．１４μｍの厚さに成長し、厚さ２０ｎｍのゲルマニ
ウムを添加したＰ型多結晶シリコン膜１５ｂを介してベ
ース領域１５ａと接続しているため、ベース引出し用の
Ｐ型多結晶シリコン膜６とエピタキシャル成長層３との
絶縁膜厚はベース幅に依らず一定であり、絶縁性，容量
のいずれにおいても問題が生じることは無い。As shown in FIG. 3, the first embodiment except that the base region 15a and the P-type polycrystalline silicon film 15b are formed by adding boron atoms to a silicon-germanium mixed crystal in which germanium atoms are added to silicon. It has the same configuration as To improve the performance of the bipolar transistor, it is necessary to reduce the base width. However, in order to prevent the collector-base breakdown voltage from deteriorating, the hFE characteristic is lowered because the impurity atom concentration is set high. To accommodate this h FE decrease, it is effective to constitute the base region of silicon-germanium mixed crystal. In this embodiment, even when the width of the base region 15a is set to 40 nm in order to reduce the thickness of the base, a high-concentration P-type polycrystalline silicon film 9 is grown to a thickness of 0.14 μm in this embodiment. Since it is connected to the base region 15a via the P-type polycrystalline silicon film 15b to which germanium is added, the insulating film thickness between the P-type polycrystalline silicon film 6 for extracting the base and the epitaxial growth layer 3 does not depend on the base width. It is constant, and there is no problem in either insulation or capacitance.
【００２０】[0020]
【発明の効果】以上説明したように本発明は、ベース引
出し用の一導電型多結晶シリコン膜と選択エピタキシャ
ル成長により形成されるベース領域との間にベース領域
形成と同時に形成される一導電型多結晶シリコン膜及び
高濃度の不純物を導入して選択的に形成される低抵抗の
一導電型多結晶シリコン膜を介在させて接続することに
より、ベース領域引出抵抗を低減させることができると
いう効果を有する。As described above, the present invention relates to a method of forming a conductive type polycrystalline silicon film formed simultaneously with the formation of a base region between a conductive type polycrystalline silicon film for extracting a base and a base region formed by selective epitaxial growth. By connecting through a crystalline silicon film and a low-resistance one-conductivity-type polycrystalline silicon film selectively formed by introducing a high-concentration impurity, the effect of reducing the base region extraction resistance can be obtained. Have.
【００２１】その結果、従来の高抵抗の多結晶シリコン
膜によってのみ接続される場合と比べて、例えば５０ｎ
ｍのベース幅の場合、接続部の抵抗が１／５に低下し、
ベース抵抗値を１５％低減することができた。As a result, as compared with the case where the connection is made only by the conventional high-resistance polycrystalline silicon film, for example, 50 n
In the case of a base width of m, the resistance of the connection decreases to 1/5,
The base resistance could be reduced by 15%.
【図１】本発明の第１の実施例を説明するための工程順
に示した半導体チップの断面図。FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.
【図２】本発明の第１の実施例を説明するための工程順
に示した半導体チップの断面図。FIG. 2 is a sectional view of a semiconductor chip shown in a process order for explaining a first embodiment of the present invention.
【図３】本発明の第２の実施例を示す半導体チップの断
面図。FIG. 3 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【図４】従来の半導体装置の一例を示す半導体チップの
断面図。FIG. 4 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
１ Ｐ型シリコン基板 ２ Ｎ型埋込コレクタ層 ３ エピタキシャル成長層 ４，７，８，１１ 酸化シリコン膜 ５ 窒化シリコン膜 ６，９，１０ｂ，１５ｂ Ｐ型多結晶シリコン膜 １０ａ，１５ａ ベース領域 １２ Ｎ型多結晶シリコン膜 １３ エミッタ領域 １４ アルミニウム電極 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 N-type buried collector layer 3 Epitaxial growth layer 4, 7, 8, 11 Silicon oxide film 5 Silicon nitride film 6, 9, 10b, 15b P-type polycrystalline silicon film 10a, 15a Base region 12 N-type Polycrystalline silicon film 13 Emitter region 14 Aluminum electrode
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/331 H01L 29/73 Continuation of front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/331 H01L 29/73
Claims (3)
のコレクタ領域と、前記コレクタ領域上に順次積層して
設けた絶縁膜及び一導電型の第１の多結晶シリコン膜
と、前記第１の多結晶シリコン膜及び絶縁膜を貫通して
設け且つ前記絶縁膜の側面をエッチングして第１の多結
晶シリコン膜の下面の一部を露出させた開口部と、前記
開口部のコレクタ領域上に設けた一導電型のエピタキシ
ャル成長させたベース層と、前記第１の多結晶シリコン
膜の下面に接続して設けた高濃度一導電型の第２の多結
晶シリコン膜と、前記コレクタ領域上に設けて前記第２
の多結晶シリコン膜と接続する一導電型の第３の多結晶
シリコン膜と、前記開口部の第１，第２及び第３の多結
晶シリコン膜の側璧に設けた絶縁性スペーサと、前記ス
ペーサの内側の前記ベース層の表面に設けた逆導電型の
エミッタ領域とを備えたことを特徴とする半導体装置。A collector region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type; an insulating film and a first polycrystalline silicon film of one conductivity type provided sequentially on the collector region; An opening provided through the first polycrystalline silicon film and the insulating film and etching a side surface of the insulating film to expose a part of the lower surface of the first polycrystalline silicon film; and a collector of the opening. One-conductivity type epitaxy on the region
And a high-concentration one-conductivity-type second polycrystalline silicon film connected to the lower surface of the first polycrystalline silicon film, and the second polycrystalline silicon film provided on the collector region.
A third polycrystalline silicon film of one conductivity type connected to the polycrystalline silicon film, an insulating spacer provided on a side wall of the first, second, and third polycrystalline silicon films in the opening; A semiconductor device having a reverse conductivity type emitter region provided on a surface of the base layer inside a spacer.
混晶である請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said base layer is a silicon-germanium mixed crystal.
クタ領域を形成する工程と、前記コレクタ領域の上に第
１及び第２の絶縁膜と一導電型の第１の多結晶シリコン
膜と第３の絶縁膜を順次堆積して設ける工程と、前記第
３の絶縁膜及び第１の多結晶シリコン膜を選択的に順次
異方性エッチングして開口部を設け前記開口部を含む表
面に第４の絶縁膜を堆積してエッチバックし前記開口部
の側壁にのみ前記第４の絶縁膜を残して第１のスペーサ
を形成する工程と、前記第４及び第１の絶縁膜をマスク
として前記第２の絶縁膜をエッチングし前記第１の多結
晶シリコン膜の下面を露出させる工程と、前記第１の多
結晶シリコン膜の下面に高濃度一導電型の第２の多結晶
シリコン膜を選択成長させる工程と、前記開口部の第１
の絶縁膜をエッチング除去した後前記コレクタ領域の表
面に一導電型のベース層を成長させると同時に前記第２
の多結晶シリコン膜の表面に一導電型の第３の多結晶シ
リコン膜を堆積して前記ベース層と接続させる工程と、
前記開口部を含む表面に第５の絶縁膜を堆積してエッチ
バックし前記開口部の側面にのみ第５の絶縁膜を残して
第２のスペーサを形成する工程と、前記開口部を含む表
面に逆導電型の多結晶シリコン膜を堆積し熱処理により
前記ベース層の表面に逆導電型不純物を拡散してエミッ
タ領域を形成する工程とを含むことを特徴とする半導体
装置の製造方法。3. A step of forming a reverse conductivity type collector region on a one conductivity type semiconductor substrate, a first and a second insulating film and a one conductivity type first polycrystalline silicon film on the collector region. And a step of sequentially depositing and providing a third insulating film, and selectively opening the third insulating film and the first polycrystalline silicon film sequentially and anisotropically to form an opening. Depositing and etching back a fourth insulating film to form a first spacer while leaving the fourth insulating film only on the side wall of the opening; and masking the fourth and first insulating films with each other. Etching the second insulating film to expose a lower surface of the first polycrystalline silicon film; and forming a high-concentration one-conductivity-type second polycrystalline silicon film on the lower surface of the first polycrystalline silicon film. A step of selectively growing
After the insulating film is removed by etching, a base layer of one conductivity type is grown on the surface of the collector region.
Depositing a third polycrystalline silicon film of one conductivity type on the surface of the polycrystalline silicon film and connecting to the base layer ;
Depositing a fifth insulating film on the surface including the opening and etching back to form a second spacer while leaving the fifth insulating film only on the side surface of the opening; and a surface including the opening. Depositing a reverse-conductivity-type polycrystalline silicon film on the substrate, and diffusing a reverse-conductivity-type impurity into the surface of the base layer by heat treatment to form an emitter region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19634391A JP3168622B2 (en) | 1991-08-06 | 1991-08-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19634391A JP3168622B2 (en) | 1991-08-06 | 1991-08-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0541384A JPH0541384A (en) | 1993-02-19 |
| JP3168622B2 true JP3168622B2 (en) | 2001-05-21 |
Family
ID=16356258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19634391A Expired - Fee Related JP3168622B2 (en) | 1991-08-06 | 1991-08-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3168622B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6680522B1 (en) | 1999-01-11 | 2004-01-20 | Nec Electronics Corporation | Semiconductor device with reduced electrical variation |
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1991
- 1991-08-06 JP JP19634391A patent/JP3168622B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0541384A (en) | 1993-02-19 |
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