JP3152873B2 - Low temperature firing circuit board - Google Patents

Low temperature firing circuit board

Info

Publication number
JP3152873B2
JP3152873B2 JP01490696A JP1490696A JP3152873B2 JP 3152873 B2 JP3152873 B2 JP 3152873B2 JP 01490696 A JP01490696 A JP 01490696A JP 1490696 A JP1490696 A JP 1490696A JP 3152873 B2 JP3152873 B2 JP 3152873B2
Authority
JP
Japan
Prior art keywords
wiring conductor
surface wiring
conductor
circuit board
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01490696A
Other languages
Japanese (ja)
Other versions
JPH0974256A (en
Inventor
聡浩 坂ノ上
忠 村上
理香 築地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP01490696A priority Critical patent/JP3152873B2/en
Publication of JPH0974256A publication Critical patent/JPH0974256A/en
Application granted granted Critical
Publication of JP3152873B2 publication Critical patent/JP3152873B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、基板材料にガラス
−セラミック材料を用いて、低温、例えば８００〜１０
５０℃で焼成可能な低温焼成回路基板に関するものであ
り、特に、信頼性の高い表面配線導体を有する低温焼成
回路基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a glass-ceramic material as a substrate material and operates at a low temperature, e.g.
The present invention relates to a low-temperature fired circuit board that can be fired at 50 ° C., and particularly to a low-temperature fired circuit board having a highly reliable surface wiring conductor.

【０００２】[0002]

【従来の技術】従来より、基板の焼成温度を８００〜１
０５０℃と比較的低い温度で焼成可能な材料の検討がさ
れてきた。これは、例えば多層回路基板において、内部
配線導体やビアホール導体をＡｇ系、Ｃｕ系、Ａｕ系な
どの低抵抗材料を用いることにより、回路の高速化を図
るためである。このようなＡｇ系、Ｃｕ系、Ａｕ系など
の低抵抗材料は、融点が比較的低いことから、融点以下
の温度で焼成可能な基板材料が研究されてきた。2. Description of the Related Art Conventionally, the firing temperature of a substrate has been set at 800 to 1 mm.
Materials that can be fired at a relatively low temperature of 050 ° C. have been studied. This is because, for example, in a multilayer circuit board, the internal wiring conductor and the via-hole conductor are made of a low-resistance material such as an Ag-based material, a Cu-based material, or an Au-based material, thereby increasing the speed of the circuit. Since such a low-resistance material such as an Ag-based material, a Cu-based material, or an Au-based material has a relatively low melting point, substrate materials that can be fired at a temperature equal to or lower than the melting point have been studied.

【０００３】このような基板材料として、一般にガラス
−セラミック材料、例えば、コージェライト、ムライ
ト、アノートサイト、セルジアン、スピネル、ガーナイ
ト、ウイレマイト、ドロマイト、ペタライト、オオスミ
ライト及びその置換誘導体などの結晶相のうち少なくと
も１種類を析出し得る低融点ガラス成分とクリストバラ
イト、石英、コランダム（αアルミナ）のうち少なくと
も１種類のセラミック材料（無機物フィラー）とをから
なっていた。特に、このようなガラス−セラミック基板
の混合比率はセラミック材料が１０〜６０ｗｔ％、低融
点ガラス成分が９０ｗｔ％〜４０ｗｔ％と、低融点ガラ
ス成分が多いものであった。[0003] Such substrate materials are generally glass-ceramic materials such as cordierite, mullite, anorthite, serdian, spinel, garnite, willemite, dolomite, petalite, osumilite and substituted derivatives thereof. It consisted of a low melting point glass component capable of precipitating at least one of them, and at least one kind of ceramic material (inorganic filler) among cristobalite, quartz and corundum (α-alumina). In particular, the mixing ratio of such a glass-ceramic substrate was such that the ceramic material was 10 to 60 wt%, the low melting glass component was 90 to 40 wt%, and the low melting glass component was large.

【０００４】実際、このような基板材料を用いて、回路
基板を構成するには、回路基板の表面に表面配線導体を
形成する必要がある。また、製造工程上、基板の焼成と
表面配線導体の焼成工程を共通化して、製造方法の簡略
化を図ることが考えられていた。In fact, in order to construct a circuit board using such a board material, it is necessary to form a surface wiring conductor on the surface of the circuit board. Further, in the manufacturing process, it has been considered to simplify the manufacturing method by sharing the firing process of the substrate and the firing process of the surface wiring conductor.

【０００５】基板と一体的に焼成される表面配線導体と
しては、Ａｇ系導体やＣｕ系導体などが例示できる。し
かしながら、表面配線導体にＩＣチップなどをボンディ
ングワイヤで接続するためには、専らＡｇ系導体に限ら
れていた。[0005] Examples of the surface wiring conductor integrally fired with the substrate include an Ag-based conductor and a Cu-based conductor. However, in order to connect an IC chip or the like to the surface wiring conductor with a bonding wire, it has been exclusively limited to an Ag-based conductor.

【０００６】従来、基板と一体的に焼成されるＡｇ系表
面配線導体は、例えば金属成分中約９９ｗｔ％Ａｇ系金
属粉末、金属成分中約１ｗｔ％Ｐｔ系金属粉末、ホウケ
イ酸系低融点ガラス、有機バインダー、有機溶剤を均質
混合したＡｇ系導電性ペーストを用いて、未焼成状態の
基板（単板または内部に配線導体膜が形成された多層基
板）上に、スクリーン印刷で所定形状の導体膜を形成
し、基板と一体的に酸化性雰囲気、大気雰囲気でピーク
温度８００〜１０５０℃で焼成することによって形成さ
れていた。Conventionally, Ag-based surface wiring conductors integrally fired with a substrate include, for example, about 99 wt% Ag-based metal powder in a metal component, about 1 wt% Pt-based metal powder in a metal component, borosilicate low melting glass, Using an Ag-based conductive paste in which an organic binder and an organic solvent are homogeneously mixed, a conductive film having a predetermined shape is screen-printed on an unfired substrate (single plate or a multilayer substrate having a wiring conductive film formed therein). And sintering at a peak temperature of 800 to 1050 ° C. in an oxidizing atmosphere and an air atmosphere integrally with the substrate.

【０００７】特に、表面配線導体を形成するための表面
配線用Ａｇ系導電性ペーストに含まれるホウケイ酸系低
融点ガラスの添加量は、例えば金属成分に対して１．０
ｗｔ％程度であり、焼成された基板上に後に焼きつけす
る場合の表面配線用Ａｇ系導電性ペーストに含まれるホ
ウケイ酸系低融点ガラスの添加量（金属成分に対して
３．０〜５．０ｗｔ％程度）に比較して非常に少なくな
っている。これは、表面配線導体が基板と一体的に焼成
される場合、焼成処理中において基板材料のガラス成分
が表面配線導体に大きく影響し、基板の表面にまで多量
のガラス成分が析出してくるためである。In particular, the addition amount of the borosilicate low melting point glass contained in the Ag-based conductive paste for surface wiring for forming the surface wiring conductor is, for example, 1.0 to metal component.
wt%, and the amount of borosilicate low-melting glass contained in the Ag-based conductive paste for surface wiring when subsequently baked on a fired substrate (3.0 to 5.0 wt% based on the metal component) %). This is because when the surface wiring conductor is fired integrally with the substrate, the glass component of the substrate material greatly affects the surface wiring conductor during the firing process, and a large amount of glass component is deposited on the surface of the substrate. It is.

【０００８】そして、上述のように表面配線導体及び基
板とが一体的に形成された回路基板としては、表面配線
導体上に、厚膜抵抗体膜や絶縁保護膜を被着形成し、さ
らに、各種電子部品などが半田を介して接続されて達成
されていた。[0008] As described above, as a circuit board in which the surface wiring conductor and the substrate are integrally formed, a thick-film resistor film or an insulating protective film is formed on the surface wiring conductor. This has been achieved by connecting various electronic components and the like via solder.

【０００９】[0009]

【発明が解決しようとする課題】しかし、上述のように
形成された表面配線導体の初期強度は１．５ｋｇｆ／２
ｍｍ□以上、例えば３．３ｋｇｆ／２ｍｍ□と非常に強
固なものであるが、高温（１５０℃）エージング試験や
温度サイクル（−４０℃〜１２５℃、各３０分）試験後
の強度は１．０ｋｇｆ／２ｍｍ□以下となり、例えば、
電子部品などを実装した後、過酷な条件で使用した場
合、基板と表面配線導体との間での接合強度が低下して
しまうことがある。However, the surface wiring conductor formed as described above has an initial strength of 1.5 kgf / 2.
mm □ or more, for example, 3.3 kgf / 2 mm □, which is very strong, but the strength after a high temperature (150 ° C.) aging test and a temperature cycle (−40 ° C. to 125 ° C., 30 minutes each) test is 1. 0kgf / 2mm □ or less, for example,
When used under severe conditions after mounting electronic components or the like, the bonding strength between the substrate and the surface wiring conductor may be reduced.

【００１０】これは、Ａｇ系表面配線導体を構成するＡ
ｇ粒子と、基板材料のガラス成分とのアンカー効果（Ａ
ｇ粒子と基板材料のガラス成分との界面でスパイク構造
が形成され、両者が強固に接合しあう）が脆弱な場合、
熱的に過酷な条件が加わると、スパイク構造が破壊され
てしまうと考えられる。[0010] This is because A
g particles and the glass component of the substrate material anchor effect (A
When a spike structure is formed at the interface between the g-particles and the glass component of the substrate material, and the two are firmly joined to each other),
It is considered that the spike structure is destroyed when thermally severe conditions are applied.

【００１１】本発明は上述の問題点に問題点に鑑みて案
出されたものであり、その目的は、表面の半田濡れ性に
優れ、高温（１５０℃）エージング試験や温度サイクル
（−４０℃〜１２５℃、各３０分）試験後であっても充
分な接着強度の表面配線導体を有する実用性に優れた低
温焼成回路基板を提供するものである。The present invention has been devised in view of the above-mentioned problems, and has as its object to provide excellent surface solder wettability, a high-temperature (150 ° C.) aging test and a temperature cycle (−40 ° C.). (Up to 125 ° C., 30 minutes each) It is intended to provide a low-temperature fired circuit board excellent in practicability, having surface wiring conductors having sufficient adhesive strength even after the test.

【００１２】[0012]

【００１３】[0013]

【課題を解決するための手段】本発明は、ガラス−セラ
ミック材料からなる基体の少なくとも表面にＡｇを主成
分とし電子部品の電極が半田を介して接続される第１の
配線導体と、Ａｇを主成分としＩＣチップの電極がボン
ディングワイヤを介して接続される第２の配線導体を被
着形成して成る低温焼成回路基板において、前記記第１
の配線導体に、Ａｇを主成分とする金属成分の全重量に
対して、０．２〜１重量％のＶ2Ｏ5を含有させたことを
特徴とする低温焼成回路基板である。According to the present invention, there is provided a first wiring conductor comprising Ag as a main component and electrodes of electronic parts connected via solder to at least the surface of a substrate made of a glass-ceramic material; A low-temperature fired circuit board, comprising as a main component a second wiring conductor to which an electrode of an IC chip is connected via a bonding wire is formed,
A low-temperature fired circuit board characterized in that 0.2 to 1% by weight of V 2 O 5 is contained in the wiring conductor of the present invention with respect to the total weight of the metal component mainly composed of Ag.

【００１４】[0014]

【００１５】[0015]

【作用】本発明によれば、表面配線導体を、ガラス−セ
ラミックからなる未焼成の基板上に、Ａｇ系導電性ペー
ストを用いて印刷・乾燥を行い、一体的に焼成して形成
するが、この時、Ａｇ系導電性ペースト中にＶ2Ｏ5 を
添加しておくことにより、特に、Ａｇ系導電性ペースト
を構成するＡｇ粒子への基板材料のガラス成分によるア
ンカー効果が助長され、これにより、高温（１５０℃）
エージング試験や温度サイクル（−４０℃〜１２５℃、
各３０分）試験をおこなっても、接着強度が劣化するこ
とを防止できる。Ａｇ粉末の焼成時に発生する収縮反応
を遅らせることができ、これにより、基板の反りも有効
に防止することができる。According to the present invention, a surface wiring conductor is formed on an unfired substrate made of glass-ceramic by printing and drying using an Ag-based conductive paste and firing integrally. At this time, by adding V 2 O 5 to the Ag-based conductive paste, in particular, the anchor effect of the glass component of the substrate material to Ag particles constituting the Ag-based conductive paste is promoted. , High temperature (150 ℃)
Aging test and temperature cycle (-40 ° C to 125 ° C,
Even if the test is performed for each 30 minutes), it is possible to prevent the adhesive strength from deteriorating. The shrinkage reaction that occurs during the firing of the Ag powder can be delayed, thereby effectively preventing the substrate from warping.

【００１６】特に、Ｖ2Ｏ5 の添加量が、０．２〜１ｗ
ｔ％に設定すると、高温（１５０℃）エージング試験や
温度サイクル（−４０℃〜１２５℃、各３０分）試験後
であっても、接着強度が１．０Ｋｇｆ／２ｍｍ□と非常
に優れ、且つ表面の半田濡れ性も優れた低温焼成回路基
板となる。In particular, when the added amount of V 2 O 5 is 0.2 to 1 w
When it is set to t%, even after a high temperature (150 ° C.) aging test or a temperature cycle (−40 ° C. to 125 ° C., 30 minutes each) test, the adhesive strength is as excellent as 1.0 kgf / 2 mm □, and A low-temperature fired circuit board having excellent surface solder wettability is obtained.

【００１７】尚、種々検討した結果、Ｖ2 Ｏ5 を含有す
るＡｇ系導体は、表面の半田濡れ性に優れ、半田との接
合は強固になるものの、その表面の面粗度が低下して、
ボンディングワイヤの接合の信頼性が低下してしまうこ
とが判った。As a result of various studies, it has been found that the Ag-based conductor containing V 2 O 5 has excellent solder wettability on the surface and the bonding with the solder is strong, but the surface roughness of the surface is reduced. ,
It has been found that the reliability of bonding of the bonding wire is reduced.

【００１８】従って、本発明のように、低温焼成回路基
板の表面配線導体を、半田接合用の第１の表面配線導体
と主にボンディングワイヤ接合用の第２の表面配線導体
とを区別して、特に、第１の表面配線導体にＶ2Ｏ5 を
含有するＡｇ系導体で構成することにより、各種電子部
品の電極を半田を介して第１の表面配線導体に接続で
き、ＩＣチップの電極をボンディングワイヤを介して第
２の配線導体に接続でき、基板上に接続構造に係わらず
各種電子部品（ＩＣチップも含む）が安定して接続でき
る。Therefore, as in the present invention, the surface wiring conductor of the low-temperature fired circuit board is distinguished from the first surface wiring conductor for solder bonding and the second surface wiring conductor mainly for bonding wire bonding. In particular, by configuring the first surface wiring conductor with an Ag-based conductor containing V 2 O 5 , the electrodes of various electronic components can be connected to the first surface wiring conductor via solder, and the electrodes of the IC chip can be connected. It can be connected to the second wiring conductor via a bonding wire, and various electronic components (including IC chips) can be stably connected to the substrate regardless of the connection structure.

【００１９】[0019]

【発明の実施の形態】以下、本発明の低温焼成回路基板
を図面に基づいて説明する。図１は、本発明の基本とな
る低温焼成回路基板の断面図である。尚、実施例では、
基板として、ガラス−セラミック層を５層積層して成る
多層回路基板で説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A low-temperature fired circuit board according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a low-temperature fired circuit board which is the basis of the present invention. In the embodiment,
A description will be given of a multilayer circuit board formed by laminating five glass-ceramic layers as a substrate.

【００２０】図１において、１０は低温焼回路基板であ
り、１は内部に所定回路を構成する内部配線導体を有す
る積層体、２は積層体１の表面に形成した表面配線導
体、３は内部配線導体、４はビアホール導体、５は厚膜
抵抗膜であり、６は各種電子部品である。In FIG. 1, 10 is a low-temperature circuit board, 1 is a laminated body having an internal wiring conductor constituting a predetermined circuit inside, 2 is a surface wiring conductor formed on the surface of the laminated body 1, and 3 is an internal wiring conductor. Wiring conductors, 4 are via-hole conductors, 5 is a thick resistive film, and 6 is various electronic components.

【００２１】積層体１は、ガラス−セラミック層１ａ〜
１ｅと、ガラス−セラミック層１ａ〜１ｅの各層間に
は、所定回路網を達成するや容量成分を発生するための
内部配線導体３が配置されている。また、ガラス−セラ
ミック層１ａ〜１ｅには、その層の厚み方向を貫くビア
ホール導体４が形成されている。The laminate 1 has glass-ceramic layers 1a to 1c.
An internal wiring conductor 3 for achieving a predetermined circuit network and generating a capacitance component is arranged between each of the layers 1e and the glass-ceramic layers 1a to 1e. Further, via-hole conductors 4 are formed in the glass-ceramic layers 1a to 1e so as to extend through the thickness direction of the layers.

【００２２】ガラス−セラミック層１ａ〜１ｅは、例え
ば８５０〜１０５０℃前後の比較的低い温度で焼成可能
にするガラス−セラミック材料からなる。具体的なセラ
ミック材料としては、クリストバライト、石英、コラン
ダム（αアルミナ）、ムライト、コージライトなどが例
示できる。また、ガラス材料として複数の金属酸化物を
含むガラスフリットを焼成処理することによって、コー
ジェライト、ムライト、アノーサイト、セルジアン、ス
ピネル、ガーナイト、ウイレマイト、ドロマイト、ペタ
ライトやその置換誘導体の結晶を少なくとも１種類を析
出するものである。このガラス−セラミック層１ａ〜１
ｅの厚みは例えば１００〜３００μｍ程度である。The glass-ceramic layers 1a to 1e are made of a glass-ceramic material which can be fired at a relatively low temperature, for example, around 850 to 1050 ° C. Specific examples of the ceramic material include cristobalite, quartz, corundum (α-alumina), mullite, and cordierite. In addition, by firing a glass frit containing a plurality of metal oxides as a glass material, at least one kind of crystal of cordierite, mullite, anorthite, Celsian, spinel, garnite, willemite, dolomite, petalite or a substituted derivative thereof is obtained. Is deposited. This glass-ceramic layer 1a-1
The thickness of e is, for example, about 100 to 300 μm.

【００２３】内部配線導体３、ビアホール導体４は、Ａ
ｇ系（Ａｇ単体、Ａｇ−ＰｄなどのＡｇ合金）など導体
からなり、内部配線導体３の厚みは８〜１５μｍ程度で
あり、ビアホール導体４の直径は任意な値とすることが
できるが、例えば直径は８０〜２５０μｍである。The internal wiring conductor 3 and the via-hole conductor 4
The internal wiring conductor 3 has a thickness of about 8 to 15 μm, and the diameter of the via-hole conductor 4 can be an arbitrary value. The diameter is between 80 and 250 μm.

【００２４】また、積層体１の両主面には、表面配線導
体２が形成されている。表面配線導体２は、金属酸化物
Ｖ2 Ｏ5 を含有するＡｇ系（Ａｇ単体、Ａｇ−Ｐｄなど
のＡｇ合金）導体から成る。On both main surfaces of the laminate 1, surface wiring conductors 2 are formed. The surface wiring conductor 2 is made of an Ag-based (Ag alone, Ag alloy such as Ag-Pd) conductor containing a metal oxide V 2 O 5 .

【００２５】また、表面配線導体２のＡｇ系導体は、積
層体１の焼成時に同時に焼成されて形成されるものであ
り、電子部品６をＡｇ系の表面配線導体２上に半田接合
したときに、Ａｇ系表面配線導体２に半田食われが発生
しないように、Ａｇ系導体にＰｔなどを若干添加されて
いる。The Ag-based conductor of the surface wiring conductor 2 is formed by firing simultaneously with the firing of the laminated body 1, and when the electronic component 6 is soldered onto the Ag-based surface wiring conductor 2. In order to prevent solder erosion from occurring in the Ag-based surface wiring conductor 2, Pt or the like is slightly added to the Ag-based conductor.

【００２６】表面配線導体２は、入出力端子部分や電子
部品搭載パッドを含むものであり、必要に応じて、厚膜
抵抗体膜５や絶縁保護膜が形成され、さらにチップ状コ
ンデンサ、チップ状抵抗器、トランジスタなどの各種電
子部品６などが搭載、半田接合されている。The surface wiring conductor 2 includes an input / output terminal portion and an electronic component mounting pad, and if necessary, a thick film resistor film 5 and an insulating protective film are formed. Various electronic components 6 such as a resistor and a transistor are mounted and soldered.

【００２７】上述の低温焼成回路の製造方法について説
明する。A method of manufacturing the above-described low-temperature firing circuit will be described.

【００２８】積層セラミック回路基板１の製造方法は、
まず、ガラス−セラミック層１ａ〜１ｅとなるガラス−
セラミック材料から成るグリーンシートを形成する。具
体的には、セラミック粉末、低融点ガラス成分のフリッ
ト、有機バインダ、有機溶剤を均質混練したスラリー
を、ドクタブレード法によって所定厚みにテープ成型し
て、所定大きさに切断してシートを作成する。The manufacturing method of the multilayer ceramic circuit board 1 is as follows.
First, glass-ceramic layers 1a to 1e
A green sheet made of a ceramic material is formed. Specifically, a ceramic powder, a frit of a low-melting glass component, an organic binder, and a slurry obtained by homogeneously kneading an organic solvent are tape-formed to a predetermined thickness by a doctor blade method, and cut into a predetermined size to form a sheet. .

【００２９】セラミック粉末は、クリストバライト、石
英、コランダム（αアルミナ）、ムライト、コージライ
トなどの絶縁セラミック材料、ＢａＴｉＯ3 、Ｐｂ4 Ｆ
ｅ2Ｎｂ2 Ｏ12、ＴｉＯ2 などの誘電体セラミック材
料、Ｎｉ−Ｚｎフェライト、Ｍｎ−Ｚｎフェライト（広
義の意味でセラミックという）なとの磁性体セラミック
材料などが挙げられ、その平均粒径１．０〜６．０μ
ｍ、好ましくは１．５〜４．０μｍに粉砕したものを用
いる。尚、セラミック材料は２種以上混合して用いられ
てもよい。特に、コランダムを用いた場合、コスト的に
有利となる。The ceramic powder includes insulating ceramic materials such as cristobalite, quartz, corundum (α-alumina), mullite, cordierite, BaTiO 3 , Pb 4 F
e 2 Nb 2 O 12, the dielectric ceramic material, such as TiO 2, Ni-Zn ferrite, (referred to ceramic in a broad sense) Mn-Zn ferrite Do to as magnetic ceramic material can be mentioned, its average particle size 1 0.0-6.0μ
m, preferably 1.5 to 4.0 μm. Note that two or more ceramic materials may be used in combination. In particular, the use of corundum is advantageous in terms of cost.

【００３０】低融点ガラス成分のフリットは、焼成処理
することによってコージェライト、ムライト、アノーサ
イト、セルジアン、スピネル、ガーナイト、ウイレマイ
ト、ドロマイト、ペタライトやその置換誘導体の結晶や
スピネル構造の結晶相を析出するものであればよく、例
えば、Ｂ2 Ｏ3 、ＳｉＯ2 、Ａｌ2 Ｏ3 、ＺｎＯ、アル
カリ土類酸化物を含むガラスフリットが挙げられる。こ
の様なガラスフリットは、ガラス化範囲が広くまた屈伏
点が６００〜８００℃付近にあるため、８５０〜１０５
０℃程度の低温焼成に適し、Ａｇ系内部配線導体３、Ａ
ｇ系表面配線導体２となる導体膜との焼結挙動が近似し
ている。尚、このガラスフリットの平均粒径は、１．０
〜６．０μｍ、好ましくは１．５〜３．５μｍである。The frit of the low-melting glass component precipitates a crystal phase of cordierite, mullite, anorthite, serdian, spinel, garnite, willemite, dolomite, petalite or a substituted derivative thereof or a crystal phase having a spinel structure by firing. Any material may be used, for example, glass frit containing B 2 O 3 , SiO 2 , Al 2 O 3 , ZnO, and alkaline earth oxide. Such a glass frit has a wide vitrification range and a yield point of about 600 to 800 ° C.
Suitable for firing at a low temperature of about 0 ° C, Ag-based internal wiring conductor 3, A
The sintering behavior with the conductor film serving as the g-based surface wiring conductor 2 is similar. The average particle size of the glass frit is 1.0
６6.0 μm, preferably 1.5-3.5 μm.

【００３１】上述のセラミック材料とガラス材料との構
成比率は、８５０〜１０５０℃の比較的低温で焼成する
場合には、セラミック材料が１０〜６０ｗｔ％、好まし
くは３０〜５０ｗｔ％であり、ガラス材料が９０〜４０
ｗｔ％、好ましくは７０〜５０ｗｔ％である。When the above ceramic material and the glass material are fired at a relatively low temperature of 850 to 1050 ° C., the ceramic material is 10 to 60 wt%, preferably 30 to 50 wt%. Is 90-40
wt%, preferably 70 to 50 wt%.

【００３２】有機バインダは、固形分（セラミック粉
末、低融点ガラス成分のフリット）との濡れ性も重視す
る必要があり、比較的低温で且つ短時間の焼成工程で焼
失できるように熱分解性に優れたものが好ましく、アク
リル酸もしくはメタクリル酸系重合体のようなカルボキ
シル基、アルコール性水酸基を備えたエチレン性不飽和
化合物が好ましい。It is necessary to give importance to the wettability of the organic binder with a solid content (ceramic powder, frit of a low melting point glass component), and the organic binder is thermally decomposable so that it can be burned off in a relatively low temperature and short firing step. Excellent ones are preferable, and ethylenically unsaturated compounds having a carboxyl group and an alcoholic hydroxyl group such as acrylic acid or methacrylic acid-based polymers are preferable.

【００３３】溶剤として、有機系溶剤、水系溶剤を用い
ることができる。例えば、有機溶剤の場合には、２．
２．４−トリメチル−１．３−ペンタジオールモノイソ
ベンチートなどが用いられ、水系溶剤の場合には、水溶
性である必要があり、モノマー及びバインダには、親水
性の官能基、例えばカルボキシル基が付加されている。As the solvent, an organic solvent or an aqueous solvent can be used. For example, in the case of an organic solvent, 2.
For example, 2.4-trimethyl-1.3-pentadiol monoisoventilate is used. In the case of an aqueous solvent, it must be water-soluble, and a hydrophilic functional group such as carboxyl is contained in the monomer and the binder. A group has been added.

【００３４】その付加量は酸価で表せば２〜３００あ
り、好ましくは５〜１００である。付加量が少ない場合
は水への溶解性、固定成分の粉末の分散性が悪くなり、
多い場合は熱分解性が悪くなるため、付加量は、水への
溶解性、分散性、熱分解性を考慮して、上述の範囲で適
宜付加される。The amount of addition is 2 to 300, preferably 5 to 100, in terms of acid value. If the added amount is small, the solubility in water, the dispersibility of the powder of the fixed component becomes poor,
When the amount is large, the thermal decomposability deteriorates. Therefore, the addition amount is appropriately added in the above range in consideration of solubility in water, dispersibility, and thermal decomposability.

【００３５】次に、ガラス−セラミック層１ａ〜１ｅと
なるグリーンシートの夫々に、各層のビアホール導体４
の形成位置に、所定径の貫通穴をパンチングによって形
成する。Next, each of the green sheets serving as the glass-ceramic layers 1a to 1e is provided with a via hole conductor 4 of each layer.
A through hole having a predetermined diameter is formed by punching at the forming position.

【００３６】次に、グリーンシートの貫通穴に、ビアホ
ール導体４の導体をＡｇ系導電性ペーストを印刷・充填
するとともに、ガラス−セラミック層１ｂ〜１ｅとなる
グリーンシート上に、各内部配線導体３となる導体膜を
印刷し、乾燥処理を行う。Next, the conductor of the via-hole conductor 4 is printed and filled with an Ag-based conductive paste in the through-hole of the green sheet, and each of the internal wiring conductors 3 is placed on the green sheet to be the glass-ceramic layers 1b to 1e. Is printed and a drying process is performed.

【００３７】ここで、内部配線用のＡｇ系導電性ペース
トは、Ａｇ系（Ａｇ単体、Ａｇ−ＰｄなどのＡｇ合金）
導電性粉末、必要に応じて所定量のホウケイ酸系低融点
ガラスフリット、エチルセルロースなどの有機バインダ
ー、溶剤を均質混合したものが用いられる。Here, the Ag-based conductive paste for internal wiring is Ag-based (Ag alone, Ag alloy such as Ag-Pd).
A material obtained by homogeneously mixing a conductive powder, a predetermined amount of a borosilicate-based low-melting glass frit, an organic binder such as ethyl cellulose, and a solvent, if necessary, is used.

【００３８】また、ガラス−セラミック層１ａとなるグ
リーンシート上に、表面配線導体２となる導体膜を表面
配線用のＡｇ系導電性ペーストを用いて印刷し、乾燥処
理を行う。Further, a conductor film to be the surface wiring conductor 2 is printed on the green sheet to be the glass-ceramic layer 1a by using an Ag-based conductive paste for the surface wiring, and dried.

【００３９】ここで、表面配線用のＡｇ系導電性ペース
トは、Ａｇ系（Ａｇ単体、Ａｇ−ＰｄなどのＡｇ合金）
粉末、Ｐｔ粉末、所定量のＶ2 Ｏ5 粉末、有機バインダ
ー、溶剤を均質混合したものが用いられる。尚、Ｖ2 Ｏ
5 以外の微量の金属酸化物が含有していても構わない。Here, the Ag-based conductive paste for the surface wiring is Ag-based (Ag alone, Ag alloy such as Ag-Pd).
Powder, Pt powder, a predetermined amount of V 2 O 5 powder, an organic binder, and a solvent in which a solvent is homogeneously mixed are used. In addition, V 2 O
A small amount of metal oxide other than 5 may be contained.

【００４０】このようにビアホール導体４となる導体、
内部配線導体３となる導体膜、表面配線導体２となる導
体膜が形成されたグリーンシートを、積層体１のガラス
−セラミック層１ａ〜１ｅの積層順に応じて積層一体化
する。The conductor which becomes the via-hole conductor 4 in this manner,
The green sheet on which the conductor film serving as the internal wiring conductor 3 and the conductor film serving as the surface wiring conductor 2 are formed is laminated and integrated in accordance with the lamination order of the glass-ceramic layers 1 a to 1 e of the laminate 1.

【００４１】次に、未焼成の積層体を、酸化性雰囲気ま
たは大気雰囲気で焼成処理する。焼成処理は、脱バイン
ダ過程と焼結過程からなる。Next, the unfired laminate is fired in an oxidizing atmosphere or an air atmosphere. The firing process includes a binder removal process and a sintering process.

【００４２】脱バインダ過程は、ガラス−セラミック層
１ａ〜１ｅとなるグリーンシート、内部配線導体３とな
る導体膜、ビアホール導体４となる導体、表面配線導体
２となる導体膜に含まれる有機成分を焼失するためのも
のであり、例えば６００℃以下の温度領域で行われる。In the binder removal process, the organic components contained in the green sheets serving as the glass-ceramic layers 1a to 1e, the conductor film serving as the internal wiring conductor 3, the conductor serving as the via hole conductor 4, and the conductor film serving as the surface wiring conductor 2 are removed. This is for burning out, for example, in a temperature range of 600 ° C. or less.

【００４３】また、焼結過程は、ガラス−セラミックの
グリーンシートのガラス成分を結晶化させると同時にセ
ラミック粉末の粒界に均一に分散させ、積層体に一定強
度を与え、内部配線導体３となる導体膜、ビアホール導
体４となる導体、表面配線導体２となる導体膜の導電材
料、例えば、Ａｇ系粉末を粒成長させて、低抵抗化さ
せ、ガラス−セラミック層１ａ〜１ｅと一体化させるも
のである。これは、ピーク温度８５０〜１０５０℃に達
するまでに行われる。In the sintering process, the glass component of the glass-ceramic green sheet is crystallized and simultaneously dispersed uniformly at the grain boundaries of the ceramic powder to give a certain strength to the laminated body to form the internal wiring conductor 3. Conductive material of the conductive film, the conductor to be the via-hole conductor 4, and the conductive film to be the surface wiring conductor 2, for example, the one in which the Ag-based powder is grain-grown to reduce the resistance and integrate with the glass-ceramic layers 1a to 1e. It is. This is done until a peak temperature of 850-1050 <0> C is reached.

【００４４】これにより、表面配線導体２が形成された
積層体が達成され、その後、必要に応じて、表面配線導
体２に接続する厚膜抵抗素子５や絶縁保護膜を形成し
て、各種電子部品６の電極を半田などで接合・実装を行
う。As a result, a laminated body on which the surface wiring conductor 2 is formed is achieved. After that, if necessary, a thick-film resistance element 5 and an insulating protective film connected to the surface wiring conductor 2 are formed, and various electronic components are formed. The electrodes of the component 6 are joined and mounted with solder or the like.

【００４５】これにより、表面配線導体２が積層体１と
一体的に焼成処理された低温焼成回路基板が達成するこ
とになる。As a result, a low-temperature fired circuit board in which the surface wiring conductor 2 is integrally fired with the laminate 1 is achieved.

【００４６】本発明において、積層体１と一体的に焼成
処理される表面配線導体２は、表面配線用Ａｇ系導電性
ペーストを詳細に説明すると、たとえば、平均粒径３μ
ｍのＡｇ粉末と平均粒径０．５μｍのＰｔ粉末と、Ｖ2
Ｏ5 粉末の金属酸化物と、エチルセルロースなどの有機
バインダー、ペンタンジオールイソブレートなどの有機
溶剤が均質混合されて形成される。In the present invention, the surface wiring conductor 2 which is integrally baked with the laminate 1 is made of, for example, an Ag-based conductive paste for surface wiring.
m Ag powder, Pt powder having an average particle size of 0.5 μm, and V 2
A metal oxide of O 5 powder, an organic binder such as ethyl cellulose, and an organic solvent such as pentanediol isobutrate are mixed in a homogeneous manner.

【００４７】ここで、Ａｇ粉末は導電性を与える主要な
導電材料であり、金属成分中、例えば約９９ｗｔ％の割
合で添加されている。Here, Ag powder is a main conductive material for providing conductivity, and is added to the metal component, for example, at a ratio of about 99 wt%.

【００４８】ここで、Ｐｔ粉末は、表面配線導体２上に
電子部品６の電極などを半田を介して接合した時にＡｇ
成分が半田に食われることを防止するために添加するも
のであり、金属成分中、例えば約１ｗｔ％の割合で添加
されている。Here, when the electrodes of the electronic component 6 and the like are joined to the surface wiring conductor 2 via solder, the Pt powder is Ag.
The components are added in order to prevent the components from being eaten by the solder, and are added, for example, at a ratio of about 1 wt% in the metal components.

【００４９】Ｖ2 Ｏ5 の金属酸化物の粉末は、Ａｇ系粉
末と、例えば積層体１のガラス−セラミック材料のガラ
ス成分とのアンカー効果のスパイク構造をより強固にす
るものであり、全金属成分（Ａｇ、Ｐｔ）に対して０．
１〜２ｗｔ％の範囲で添加されている。The V 2 O 5 metal oxide powder makes the spike structure of the anchor effect between the Ag-based powder and, for example, the glass component of the glass-ceramic material of the laminate 1 stronger, and makes the all-metal 0 .0 for components (Ag, Pt).
It is added in the range of 1-2 wt%.

【００５０】上述のように、表面配線導体２となるＡｇ
系導電性ペーストに、Ｖ2 Ｏ5 粉末を添加しているた
め、上述のようにアンカー効果によるスパイク構造を従
来以上に助長させることができる。これは、Ａｇ系粒子
の凹凸表面に、ガラス−セラミック材料のガラス成分を
安定に付着させることができ、これにより、長期にわた
り、アンカー効果を持続・維持させることができ、積層
体１と表面配線導体２との接着強度が長期にわたり安定
させることができる。さらに、Ｖ2 Ｏ5 は、主に積層体
１との表面配線導体２のとの界面部分に作用するため、
表面配線導体２の表面に析出されることが少ないため、
表面配線導体２の表面において、半田の濡れ性を阻害す
ることがない。As described above, Ag which becomes the surface wiring conductor 2
Since the V 2 O 5 powder is added to the system conductive paste, the spike structure due to the anchor effect can be further promoted as described above. This is because the glass component of the glass-ceramic material can be stably adhered to the uneven surface of the Ag-based particles, whereby the anchor effect can be maintained and maintained for a long period of time. The adhesive strength with the conductor 2 can be stabilized for a long time. Further, since V 2 O 5 mainly acts on the interface between the laminate 1 and the surface wiring conductor 2,
Since it is less likely to be deposited on the surface of the surface wiring conductor 2,
The wettability of the solder is not hindered on the surface of the surface wiring conductor 2.

【００５１】〔実験例〕本発明者は、積層体１と一体的
に焼成される表面配線導体２について、特に、Ｖ2 Ｏ5
の及ぼす影響を調べた。[Experimental Example] The present inventor has found that the surface wiring conductor 2 which is fired integrally with the laminate 1 is particularly V 2 O 5
The effect of was investigated.

【００５２】表面配線用Ａｇ系導電性ペーストとして、
表１に示す固形成分のペーストを作成した。尚、有機バ
インダー、有機溶剤などは省略した。As an Ag-based conductive paste for surface wiring,
A paste of the solid components shown in Table 1 was prepared. Note that an organic binder, an organic solvent, and the like are omitted.

【００５３】試料の積層体を形成するにあたり、基板材
料であるガラス−セラミック材料は、アノーサイト系の
結晶を析出し得るガラス成分とアルナ粉末とからなる２
００μｍのグリーンシートを５枚作成し、積層体の下側
となるグリーンシート上に内部配線用のＡｇ系導電性ペ
ーストで所定パターンの導体膜を、最上層となるグリー
ンシート上に、表１に示す表面配線用Ａｇ系導電性ペー
ストで所定形状の導体膜を夫々形成した後、積層圧着を
行い、大気雰囲気中で９５０℃で焼成処理した。In forming the laminate of the sample, the glass-ceramic material as the substrate material is composed of a glass component capable of precipitating anorthite-based crystals and alumina powder.
Five green sheets each having a thickness of 00 μm were prepared. A conductor film having a predetermined pattern was formed using an Ag-based conductive paste for internal wiring on the lower green sheet of the laminate. After a conductive film having a predetermined shape was formed using the Ag-based conductive paste for surface wiring shown in the figure, lamination and pressure bonding were performed, and firing treatment was performed at 950 ° C. in an air atmosphere.

【００５４】〔半田濡れ性の評価〕このようにして得ら
れた試料をロジン系フラックス溶液に浸漬した後、２３
０℃の２％Ａｇ入りＳｎ−Ｐｂ共晶半田浴中に浸漬し、
表面配線導体２の表面の半田濡れ性を調べた。半田濡れ
性は、全表面面積に対して９０％以上の面積で半田が付
着しているものを「優」として、それ以下を「劣」とし
た。[Evaluation of Solder Wettability] After the sample thus obtained was immersed in a rosin-based flux solution,
Immersed in a 2% Ag-containing Sn-Pb eutectic solder bath at 0 ° C,
The solder wettability of the surface of the surface wiring conductor 2 was examined. The solder wettability was evaluated as “excellent” when the solder was adhered in an area of 90% or more of the entire surface area, and “poor” when less than 90%.

【００５５】〔接着強度の評価〕接着強度は２ｍｍ□の
表面配線導体２に０．６ｍｍφの鉛メッキ導線を半田接
合して、ピール法で、初期状態の接着強度、１５０
℃で５００時間放置後（エージング）の接着強度、−
４０℃〜１２５℃、各３０分を１００サイクルを施した
温度サイクル試験（サイクル）後の接着強度をそれぞれ
調べた。[Evaluation of Adhesive Strength] Adhesive strength was obtained by soldering a lead-plated lead wire of 0.6 mmφ to the surface wiring conductor 2 of 2 mm square, and using a peel method, the adhesive strength in the initial state was 150.
Bonding strength after leaving at 500 ° C for 500 hours (aging),-
The adhesive strength after a temperature cycle test (cycle) in which 100 cycles were performed at 40 ° C to 125 ° C for 30 minutes each was examined.

【００５６】本発明では、初期状態で２．０ｋｇｆ／２
ｍｍ□以上、エージング、サイクル試験後で１．０ｋｇ
ｆ／２ｍｍ□以上が信頼性の高い表面配導体とした。In the present invention, 2.0 kgf / 2 in the initial state
1.0 mm after aging and cycle test
f / 2 mm square or more is a highly reliable surface conductor.

【００５７】〔基板の反りの評価〕また、焼成後の寸法
で８．５ｍｍ角の表面配線導体２を形成し、積層体一の
反りの状況を測定するとともに、外観での積層体の変色
の状況を測定した。[Evaluation of Warpage of Substrate] A surface wiring conductor 2 having a size of 8.5 mm square after firing was formed, the state of warpage of the laminate was measured, and the appearance of the laminate was checked for discoloration. The situation was measured.

【００５８】本発明では、基板の反りが０．０３ｍｍを
越えるものはと、実用性に劣る回路基板とした。In the present invention, a circuit board having a warp of more than 0.03 mm is regarded as a circuit board having poor practicality.

【００５９】その結果を、表１に合わせて示す。The results are shown in Table 1.

【００６０】[0060]

【表１】 [Table 1]

【００６１】上述の表１から明らかのように、表面配線
用Ａｇ系導電性ペーストに金属酸化物として、所定量の
Ｖ2 Ｏ5 粉末を添加すること（試料１、２）によって、
初期の接着強度で２．０Ｋｇｆ／２ｍｍ□を達成し、し
かも、１５０℃で５００時間放置後（エージング）の接
着強度で１．０Ｋｇｆ／２ｍｍ□以上の１．４Ｋｇｆ／
２ｍｍ□を達成し、−４０℃〜１２５℃、各３０分を１
００サイクルを施した温度サイクル試験（サイクル）後
の接着強度でも１．０Ｋｇｆ／２ｍｍ□以上の１．３Ｋ
ｇｆ／２ｍｍ□を達成している。As is clear from Table 1 above, by adding a predetermined amount of V 2 O 5 powder as a metal oxide to the Ag-based conductive paste for surface wiring (samples 1 and 2),
An initial bond strength of 2.0 kgf / 2 mm was achieved, and a bond strength after standing at 150 ° C. for 500 hours (aging) of not less than 1.0 kgf / 2 mm was 1.4 kgf / mm.
2mm □, -40 ° C to 125 ° C, 30 minutes each for 1
The adhesive strength after a temperature cycle test (cycle) subjected to 00 cycles is 1.3 kg of 1.0 kgf / 2 mm □ or more.
gf / 2 mm □ is achieved.

【００６２】即ち、過酷な条件に晒されても、長期的に
表面配線導体２と積層体１と接着強度が高く、且つ安定
した低温焼成回路基板が達成されることが分かる。In other words, it can be seen that a stable low-temperature fired circuit board having a high bonding strength between the surface wiring conductor 2 and the laminate 1 over a long period of time can be achieved even when exposed to severe conditions.

【００６３】これに対して、金属酸化物として、ＳｉＯ
2 を添加した場合（試料４）、通常のホウケイ酸系低融
点ガラスフリットを添加した場合（試料５）では、初期
状態の接着強度は、夫々２．６Ｋｇｆ／２ｍｍ□、３．
３Ｋｇｆ／２ｍｍ□と非常に高い値を示すものの、エー
ジング試験や温度サイクル試験後では、０．７〜０．５
Ｋｇｆ／２ｍｍ□と急激に低下してしまい、長期的に強
固な接着強度を維持できず、表面配線導体と積層体との
接着信頼性が低い低温焼成回路基板となってしまう。On the other hand, as the metal oxide, SiO 2
2 (Sample 4), and when a normal borosilicate low melting glass frit is added (Sample 5), the adhesive strength in the initial state is 2.6 kgf / 2 mm □ and 3.
Although it shows a very high value of 3 kgf / 2 mm □, it is 0.7 to 0.5 after an aging test or a temperature cycle test.
Kgf / 2 mm □, which is a sharp drop, and it is not possible to maintain strong adhesive strength for a long period of time, resulting in a low-temperature fired circuit board having low adhesion reliability between the surface wiring conductor and the laminate.

【００６４】次に、表面配線用Ａｇ系導電性ペーストに
金属酸化物Ｖ2 Ｏ5 粉末の添加量を検討すると、試料３
に示すように、添加量が金属成分に対して１．５ｗｔ％
となると、表面配線導体２の表面にＶ2 Ｏ5 が析出され
てしまい、半田濡れ性を大きく阻害してしまい、実質的
に回路基板として用いることができなくなる。Next, the amount of the metal oxide V 2 O 5 powder added to the Ag-based conductive paste for surface wiring was examined.
As shown in the figure, the addition amount is 1.5 wt% with respect to the metal component.
In this case, V 2 O 5 is deposited on the surface of the surface wiring conductor 2, greatly impairing solder wettability, and cannot be used substantially as a circuit board.

【００６５】また、試料６に示すように、Ｖ2 Ｏ5 の添
加量が０となると、試料４、５と同様に、初期状態の接
着強度は、夫々２．６Ｋｇｆ／２ｍｍ□、３．３Ｋｇｆ
／２ｍｍ□と非常に高い値を示すものの、エージング試
験や温度サイクル試験後では、０．７〜０．５Ｋｇｆ／
２ｍｍ□と急激に低下してしまい、長期的に強固な接着
強度を維持できず、表面配線導体と積層体との接着信頼
性が低い低温焼成回路基板となり、しかも、基板の反り
が０．０５ｍｍと非常に大きいものとなり、実質的に回
路基板として用いることができなくなる。As shown in Sample 6, when the amount of added V 2 O 5 became 0, the adhesive strength in the initial state was 2.6 kgf / 2 mm □ and 3.3 kgf, as in Samples 4 and 5, respectively.
/ 2mm □, a very high value, but after an aging test or a temperature cycle test, 0.7 to 0.5 kgf /
2mm □, which rapidly decreases to a low-temperature fired circuit board which cannot maintain strong adhesive strength for a long time and has low adhesion reliability between the surface wiring conductor and the laminated body. , And cannot be used substantially as a circuit board.

【００６６】このことから、本発明に示すように、表面
配線導体２として、金属成分に対して、Ｖ2Ｏ5 を添加
し、具体的には０．２ｗｔ％以上添加することが重要で
あり、上限として、１．５ｗｔ％未満、具体的には、
１．２ｗｔ％以下の範囲で添加量することが、半田の濡
れ性に優れ、基板の反りが少なく、初期状態、エージン
グ、サイクル試験などの過酷な条件をおこなっても接着
強度の高い表面配線導体となり、長期にわたり接着信頼
性の高い低温焼成回路基板となる。From this, as shown in the present invention, it is important to add V 2 O 5 to the metal component as the surface wiring conductor 2, specifically, to add 0.2 wt% or more. , As an upper limit, less than 1.5 wt%, specifically,
When added in an amount of 1.2 wt% or less, the surface wiring conductor has excellent solder wettability, low warpage of the substrate, and high adhesive strength even under severe conditions such as initial conditions, aging, and cycle tests. And a low-temperature fired circuit board with high bonding reliability over a long period of time.

【００６７】次に、低温焼成回路基板の表面に搭載され
る各電子部品６は、半田接合を想定している。しかし、
実際には、表面に搭載される電子部品６の１つに、ＩＣ
チップがあり、特にＩＣチップ６と表面配線導体膜２と
の接続構造にボンディングワイヤを用いる構造がある。Next, each electronic component 6 mounted on the surface of the low-temperature fired circuit board is assumed to be soldered. But,
Actually, one of the electronic components 6 mounted on the surface includes an IC.
There is a chip, and in particular, there is a structure using a bonding wire for a connection structure between the IC chip 6 and the surface wiring conductor film 2.

【００６８】本発明者が、Ｖ2 Ｏ5 を添加した表面配線
用Ａｇ系導電性ペーストによって形成した表面配線用導
体膜の表面状態について検討したところ、表面の面粗度
が低下していることが判った。即ち、Ｖ2 Ｏ5 を添加し
た表面配線導体２に、ボンディングワイヤを施すこと
は、その接続信頼性の低下を招いてしまうことが考えら
れる。The inventors of the present invention have studied the surface condition of the surface wiring conductor film formed of the surface wiring Ag-based conductive paste to which V 2 O 5 has been added, and found that the surface roughness is reduced. I understood. That is, it is conceivable that applying a bonding wire to the surface wiring conductor 2 to which V 2 O 5 has been added may cause a reduction in connection reliability.

【００６９】従って、積層体１に形成する表面配線導体
２は、その用途によって、適切に使い分けることが重要
となる。即ち、表面配線導体２を電子部品６との接続構
造とによって区別する。Therefore, it is important to properly use the surface wiring conductor 2 formed on the laminate 1 depending on its use. That is, the surface wiring conductor 2 is distinguished from the connection structure with the electronic component 6.

【００７０】例えば、図２に示すように、積層体１の表
面に搭載される電子部品が、電極に半田Ｓを介して接続
される電子部品６１、例えば、チップ状電子部品、トラ
ンジスタ、半田バンプ型ＩＣチップは、この電子部品６
１と半田接合する第１の表面配線導体２１としては上述
のようにＶ2 Ｏ5 を添加したＡｇ系表面配線導体を用い
るべきである。For example, as shown in FIG. 2, an electronic component 61 mounted on the surface of the multilayer body 1 is connected to an electrode via a solder S, for example, a chip-shaped electronic component, a transistor, a solder bump, or the like. Type IC chip
As the first surface wiring conductor 21 to be solder-bonded to the first, an Ag-based surface wiring conductor to which V 2 O 5 is added as described above should be used.

【００７１】電極がボンディングワイヤＷを介して接続
される電子部品６２、例えば、ＩＣチップは、ボンディ
ングワイヤＷの一端と接続する第２の表面配線導体２２
としては、Ｖ2 Ｏ5 を添加しない、通常のＡｇ系表面配
線導体を用いるべきである。The electronic component 62 to which the electrode is connected via the bonding wire W, for example, an IC chip, has a second surface wiring conductor 22 connected to one end of the bonding wire W.
For this purpose, a normal Ag-based surface wiring conductor to which V 2 O 5 is not added should be used.

【００７２】さらに、上述の実験例の試料番号６からも
Ｖ2 Ｏ5 を添加しない場合には、基板との間の接着強度
が弱いことから、ボンディングワイヤＷの一端が当接す
る領域のみに、第２の表面配線導体２２を形成すればよ
い。Further, when V 2 O 5 is not added also from the sample No. 6 of the above-mentioned experimental example, since the bonding strength between the substrate and the substrate is weak, only the region where one end of the bonding wire W is in contact is provided. What is necessary is just to form the 2nd surface wiring conductor 22.

【００７３】また、製造方法においては、上述の表面配
線導体２となる導体膜を形成する際に、２回の印刷、Ｖ
2 Ｏ5 を含有していない表面配線用Ａｇ系導電性ペース
トの印刷で第２の表面配線導体２２となる導体膜を、Ｖ
2 Ｏ5 を含有した表面配線用Ａｇ系導電性ペーストの印
刷で第１の表面配線導体２１となる導体膜を分けて形成
すればよい。図では、第１の表面配線導体２１と第２の
表面配線導体２２とを表面で接続する場合には、第２の
表面配線導体２２の接着強度を補うために、第１表面配
線導体２１が第２の表面配線導体２２の一部に重畳する
ように形成しているが、その逆に、第２表面配線導体２
２が第１の表面配線導体２１の一部に重畳するように形
成ても構わない。これは、第２の表面配線導体２２の形
状によって選択する。Further, in the manufacturing method, when forming the above-mentioned conductor film to be the surface wiring conductor 2, two times of printing, V
A conductive film serving as the second surface conductor 22 in the printing of 2 O 5 and containing no surface wiring Ag-based conductive paste, V
The conductive film serving as the first surface wiring conductor 21 may be formed separately by printing an Ag-based conductive paste for surface wiring containing 2 O 5 . In the figure, when the first surface wiring conductor 21 and the second surface wiring conductor 22 are connected on the surface, the first surface wiring conductor 21 must be The second surface wiring conductor 22 is formed so as to overlap with a part of the second surface wiring conductor 22.
2 may be formed so as to overlap a part of the first surface wiring conductor 21. This is selected according to the shape of the second surface wiring conductor 22.

【００７４】また、基本的には、第１の表面配線導体２
１を形成し、ワイヤボンディング細線Ｗの一端が当接領
域のみに、Ｖ2 Ｏ5 が含有しない第２の表面配線導体２
２を重畳してもよい。Also, basically, the first surface wiring conductor 2
1 and the second surface wiring conductor 2 not containing V 2 O 5 only in the contact area where one end of the wire bonding thin wire W
2 may be superimposed.

【００７５】このようにすれば、電子部品（ＩＣチッ
プ）６１、６２の電極の接続構造が、半田接続であって
も、ボンディングワイヤによる接続であっても、いずれ
もが表面配線導体２１、２２との接続信頼性を向上また
は維持することができる。In this way, whether the connection structure of the electrodes of the electronic components (IC chips) 61 and 62 is a solder connection or a connection by a bonding wire, both are connected to the surface wiring conductors 21 and 22. Connection reliability with the device can be improved or maintained.

【００７６】尚、上述の各実施例において、基板とし
て、複数のガラス−セラミック層１ａ〜１ｅが積層し、
その間に内部配線導体３を有する積層回路基板で説明し
たが、未焼成状態のガラス−セラミック材料からなる単
板であっても構わない。In each of the above embodiments, a plurality of glass-ceramic layers 1a to 1e are laminated as a substrate.
Although the description has been given of the laminated circuit board having the internal wiring conductors 3 in between, a single plate made of an unfired glass-ceramic material may be used.

【００７７】また、積層体の形成工程がグリーンシート
の積層による方法で説明したが、ガラス−セラミック材
のペーストを順次印刷した印刷多層により積層体を形成
してもよく、また、ガラス−セラミック材からなるスリ
ッフプ材に光硬化モノマーを添加して、ビアホール導体
となる貫通穴を露光・現像によって形成する方法を含む
積層体の形成方法であってもよく、要は未焼成状態の基
板（積層体）の表面に表面配線用のＡｇ系導電性ペース
トを用いて、表面配線導体となる導体膜を形成し、その
後、基板（積層体）と同時に焼成した低温焼成回路基板
であれば、基板（積層体）の構造・形成方法は任意に変
更できる。Although the process of forming the laminate has been described by a method of laminating green sheets, the laminate may be formed by a printed multilayer in which pastes of a glass-ceramic material are sequentially printed. The method may be a method of forming a laminated body including a method of adding a photocurable monomer to a slip material made of and exposing and developing a through-hole serving as a via-hole conductor. )), A conductive film to be a surface wiring conductor is formed using an Ag-based conductive paste for surface wiring, and then a low-temperature fired circuit board fired simultaneously with the substrate (laminate). The structure and formation method of the body can be arbitrarily changed.

【００７８】また、上述の表面配線用Ａｇ系導電性ペー
ストとは、上述のようにｐｔ粉末を若干添加したもので
あってもよく、その主成分がＡｇ系（Ａｇ単体、またた
Ａｇ合金）粉末であるものを言い、さらに、Ａｇ系とし
ては、上述のＡｇ粉末であってもよく、また、Ａｇ−Ｐ
ｄ合金のようよに、Ａｇ系合金粉末であっても構わな
い。The above-mentioned Ag-based conductive paste for surface wiring may be a paste to which a small amount of pt powder is added as described above, and its main component is Ag-based (Ag alone or Ag alloy) A powder that is a powder, and the Ag-based powder may be the above-described Ag powder.
Like the d alloy, it may be an Ag-based alloy powder.

【００７９】さらに、Ａｇ系材料を主成分とする金属材
料に対して、金属酸化物として、Ｖ2 Ｏ5 を添加した
が、表面配線導体２の半田濡れ性を阻害しない範囲で、
その他の金属酸化物が微量に含まれていても構わない。Further, V 2 O 5 was added as a metal oxide to a metal material containing an Ag-based material as a main component, but as long as the solder wettability of the surface wiring conductor 2 was not impaired.
Minor amounts of other metal oxides may be included.

【００８０】[0080]

【発明の効果】以上のように本発明によれば、表面配線
導体を、ガラス−セラミックからなる未焼成の基板上
に、Ｖ2 Ｏ5 を含むＡｇ系導電性ペーストを用いて印刷
・乾燥を行い、一体的に焼成して形成した低温焼成回路
基板である。As described above, according to the present invention, a surface wiring conductor is printed and dried on an unfired substrate made of glass-ceramic using an Ag-based conductive paste containing V 2 O 5. This is a low-temperature fired circuit board formed by performing and firing integrally.

【００８１】このように、Ａｇ系の表面配線導体にＶ2
Ｏ5 が含まれることにより、表面配線導体のＡｇ粒子へ
の基板材料のガラス成分からのアンカー効果が助長さ
れ、長期にわたり安定且つ強固な接着強度が維持でき、
接着信頼性に優れた低温焼成回路基板となる。また、基
板の反りも有効に防止することができ、実用性に優れた
低温焼成回路基板となる。As described above, V 2 is applied to the Ag surface wiring conductor.
By containing O 5, the anchor effect from the glass component of the substrate material to the Ag particles of the surface wiring conductor is promoted, and stable and strong adhesive strength can be maintained for a long time,
It becomes a low-temperature fired circuit board with excellent adhesion reliability. Further, the warpage of the substrate can be effectively prevented, and a low-temperature fired circuit substrate excellent in practicality can be obtained.

【００８２】また、Ｖ2 Ｏ5 の添加量を０．２〜１ｗｔ
％に設定すると、接着信頼性、基板の反りに加え、表面
の半田濡れ性も優れた低温焼成回路基板となる。Further, the added amount of V 2 O 5 is 0.2 to 1 wt.
%, A low-temperature fired circuit board having excellent solder wettability on the surface in addition to bonding reliability and board warpage is obtained.

【００８３】さらに、表面配線導体に接続する電子部品
の接続構造によって、Ｖ2 Ｏ5 を含む表面配線導体と、
Ｖ2 Ｏ5 を含まない小さい表面配線導体とを使い分ける
ことによって、全体として、接続信頼性の高い低温焼成
回路基板となる。Further, by the connection structure of the electronic parts connected to the surface wiring conductor, the surface wiring conductor containing V 2 O 5
By properly using small surface wiring conductors not containing V 2 O 5 , a low-temperature fired circuit board with high connection reliability can be obtained as a whole.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の基本となる低温焼成回路基板の断面
図である。FIG. 1 is a cross-sectional view of a low-temperature fired circuit board which is the basis of the present invention.

【図２】 本発明に係る他の低温焼成回路基板の断面図
である。FIG. 2 is a cross-sectional view of another low-temperature fired circuit board according to the present invention.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−169140（ＪＰ，Ａ) 特開 平７−73731（ＪＰ，Ａ) 特開 昭61−245405（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 1/09 H01L 21/60 301 H05K 3/46 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-169140 (JP, A) JP-A-7-73731 (JP, A) JP-A-61-245405 (JP, A) (58) Investigation Field (Int.Cl. 7 , DB name) H05K 1/09 H01L 21/60 301 H05K 3/46

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ガラス−セラミック材料からなる基体の
少なくとも表面にＡｇを主成分とし電子部品の電極が半
田を介して接続される第１の配線導体と、Ａｇを主成分
としＩＣチップの電極がボンディングワイヤを介して接
続される第２の配線導体を被着形成して成る低温焼成回
路基板において、 前記第１の配線導体に、Ａｇを主成分とする金属成分の
全重量に対して、０．２〜１重量％のＶ2Ｏ5を含有させ
たことを特徴とする低温焼成回路基板。1. A first wiring conductor having Ag as a main component and an electrode of an electronic component connected via solder to at least the surface of a substrate made of a glass-ceramic material, and an electrode of an IC chip containing Ag as a main component. In a low-temperature fired circuit board formed by applying and forming a second wiring conductor connected via a bonding wire, the first wiring conductor has a weight of 0 with respect to the total weight of a metal component mainly composed of Ag. temperature fired circuit board, characterized in that it contained V 2 O 5 of .2～1 wt%.
JP01490696A 1995-06-30 1996-01-31 Low temperature firing circuit board Expired - Fee Related JP3152873B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01490696A JP3152873B2 (en) 1995-06-30 1996-01-31 Low temperature firing circuit board

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7-165174 1995-06-30
JP16517495 1995-06-30
JP01490696A JP3152873B2 (en) 1995-06-30 1996-01-31 Low temperature firing circuit board

Publications (2)

Publication Number Publication Date
JPH0974256A JPH0974256A (en) 1997-03-18
JP3152873B2 true JP3152873B2 (en) 2001-04-03

Family

ID=26350947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01490696A Expired - Fee Related JP3152873B2 (en) 1995-06-30 1996-01-31 Low temperature firing circuit board

Country Status (1)

Country Link
JP (1) JP3152873B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11120818A (en) * 1997-10-16 1999-04-30 Tdk Corp Conductive paste and irreversible circuit element using this paste
US6338893B1 (en) 1998-10-28 2002-01-15 Ngk Spark Plug Co., Ltd. Conductive paste and ceramic printed circuit substrate using the same

Also Published As

Publication number Publication date
JPH0974256A (en) 1997-03-18

Similar Documents

Publication Publication Date Title
JP2002198660A (en) Circuit board and method of manufacturing the same
JP3265996B2 (en) Low temperature fired glass-ceramic multilayer wiring board and its manufacturing method
JP3152873B2 (en) Low temperature firing circuit board
JPH10107437A (en) Manufacturing method of circuit board
JP3336204B2 (en) Circuit board
JP2002076609A (en) Circuit board
JP3642648B2 (en) Circuit board
JP3792271B2 (en) Low temperature firing circuit board
JP3493294B2 (en) Circuit board
JP3493264B2 (en) Circuit board
JP2885477B2 (en) Multilayer wiring board and method of manufacturing the same
JP2002198626A (en) Manufacturing method of low temperature baking ceramic circuit board
JP2000049431A (en) Ceramic circuit board
JP2001189550A (en) Circuit board
JP2001284754A (en) Glass ceramic circuit board
JPH07326835A (en) Low-temperature sintered ceramic circuit board
JP2002076639A (en) Circuit board
JP2000165043A (en) Circuit board
JP2002076640A (en) Circuit board
JP2002198624A (en) Circuit board
JP2002050842A (en) Circuit board
JP2002141646A (en) Circuit board
JP2002232093A (en) Circuit board
JPH11135899A (en) Ceramic circuit board
JP2002076554A (en) Circuit board for high frequency

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090126

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100126

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110126

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110126

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120126

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120126

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130126

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140126

Year of fee payment: 13

LAPS Cancellation because of no payment of annual fees