JP3146288B2 - package - Google Patents
packageInfo
- Publication number
- JP3146288B2 JP3146288B2 JP19321492A JP19321492A JP3146288B2 JP 3146288 B2 JP3146288 B2 JP 3146288B2 JP 19321492 A JP19321492 A JP 19321492A JP 19321492 A JP19321492 A JP 19321492A JP 3146288 B2 JP3146288 B2 JP 3146288B2
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- package
- pins
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子部品を搭載し、外
部接続ピンを介してプリント配線板上に表面実装される
パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package on which electronic components are mounted and which is surface-mounted on a printed wiring board via external connection pins.
【０００２】[0002]
【従来の技術】従来から電子部品を搭載し、外部接続ピ
ンを介してプリント配線板上に表面実装されるパッケー
ジとしては、数百本の外部接続端子となる導体ピンを有
するパッケージが使用されている。2. Description of the Related Art Conventionally, as a package on which electronic components are mounted and surface-mounted on a printed wiring board via external connection pins, a package having several hundred conductor pins serving as external connection terminals has been used. I have.
【０００３】[0003]
【発明が解決しようとする課題】上記従来の導体ピンを
有するパッケージでは、その搭載された電子部品と電気
的に接続したリードは、個別に形成された外部接続用の
導体ピンを介してプリント配線板上の回路に接続され
る。すなわち、ほぼ電子部品の端子数だけ外部接続用の
導体ピンが必要となり、導体ピンの品質管理の困難化、
パッケージへの取付け工数の増加、さらにはそのパッケ
ージをプリント配線板上に実装する技術の困難化を招い
ている。In the package having the above-described conventional conductor pins, the leads electrically connected to the mounted electronic components are printed wiring via individually formed external connection conductor pins. Connected to the circuit on the board. In other words, conductor pins for external connection are required almost as many as the number of terminals of the electronic component, making quality control of the conductor pins difficult,
This has led to an increase in the number of steps for attaching to a package, and also has made the technology for mounting the package on a printed wiring board difficult.
【０００４】本発明は、搭載する電子部品の大型化・高
集積化、さらにはマルチチップ化によるパッケージの大
型化・高集積化により顕著に現れる微小かつ膨大な数の
導体ピンの品質管理の困難化、パッケージへの取付け工
数の増加、さらにはそのパッケージをプリント配線板上
に実装する技術の困難化を改善することを目的とする。[0004] The present invention is difficult to control the quality of a very large and very small number of conductive pins, which is remarkable due to the increase in size and integration of electronic components to be mounted and the increase in size and integration of packages by multi-chip. It is an object of the present invention to reduce the number of steps required for mounting the package on a printed wiring board, and to improve the difficulty in technology for mounting the package on a printed wiring board.
【０００５】[0005]
【課題を解決するための手段】本発明は、電子部品を搭
載し、外部接続ピンを介してプリント配線板上に表面実
装されるパッケージにおいて、前記電子部品と電気的に
接続したリードの外端部と接続する前記外部接続ピン
を、複数の芯導体を形成したフレキシブルなピンとし、
その芯導体の各々の側面が、当該外部接続ピンの軸線に
垂直な平面上において前記軸線に向かって絶縁体側面に
形成した各凹部の内部で露出させた、すなわち前記芯導
体のそれぞれを互いに絶縁し分離するフレキシブルな絶
縁体の空洞内に露出させたことを構成とするパッケージ
である。According to the present invention, there is provided a package mounted with an electronic component and mounted on a surface of a printed wiring board via external connection pins, the outer end of a lead electrically connected to the electronic component. The external connection pins to be connected to the section, a flexible pin formed a plurality of core conductors,
Each side surface of the core conductor is exposed inside the concave portion formed on the insulator side surface toward the axis on a plane perpendicular to the axis of the external connection pin, that is, each of the core conductors is insulated from each other. And a package that is exposed in a cavity of a flexible insulator to be separated.
【０００６】[0006]
【作用】本発明は、電子部品と電気的に接続したリード
の外端部と接続する外部接続ピンを互いに絶縁された複
数の芯導体を形成したピンとしたことにより、電子部品
の複数の端子に個別に接続された複数のリードが一つの
外部接続ピンに収集されるから、パッケージに形成せね
ばならない外部接続用の導体ピン数を極めて少なくでき
る。しかも、電子部品と電気的に接続したリードの外端
部と接続する前記外部接続ピンを互いに絶縁された複数
の芯導体を形成したフレキシブルなピンとしたことによ
り、膨大な総端子数を持つ電子部品を搭載しながらも、
プリント配線板上に容易に実装ができ、電子機器に与え
られる機械的衝撃やパッケージとこれを実装するプリン
ト配線板との間の熱膨張率の差による応力歪みに影響さ
れないため、搭載する電子部品の大型化・高集積化、さ
らにはマルチチップ化によるパッケージの大型化・高集
積化に対応できる。According to the present invention, an external connection pin connected to an outer end of a lead electrically connected to an electronic component is a pin formed of a plurality of core conductors insulated from each other, so that a plurality of terminals of the electronic component can be provided. Since a plurality of individually connected leads are collected at one external connection pin, the number of external connection conductor pins that must be formed on the package can be extremely reduced. In addition, since the external connection pins connected to the outer ends of the leads electrically connected to the electronic components are flexible pins formed of a plurality of core conductors insulated from each other, an electronic component having an enormous total number of terminals While equipped with
It can be easily mounted on a printed wiring board and is not affected by mechanical shocks applied to electronic equipment or stress distortion due to the difference in the coefficient of thermal expansion between the package and the printed wiring board on which it is mounted. It is possible to cope with an increase in the size and integration of a package, and further, an increase in the size and integration of a package due to multi-chip integration.
【０００７】[0007]
【実施例】以下実施例をあげて、本発明を具体的に説明
する。EXAMPLES The present invention will be specifically described below with reference to examples.
【０００８】（実施例１）この実施例はＬＳＩ搭載用パ
ッケージであり、これを図１および図２に基づき説明す
る。図１は、完成したパッケージの縦断面図であり、図
２は、この実施例に使用した外部接続ピンの上面図、側
面図、底面図である。まず、この実施例は、以下の工程
により形成された。 １：厚さ５０ミクロンメータのフレキシブルな弗素系樹
脂材からなる中絶縁層を介して上下に厚さ３５ミクロン
メータの銅箔からなるリードを形成するとともに、上下
リードを保護する厚さ５０ミクロンメータの弗素系樹脂
からなる上下の絶縁層を形成した基板をリール トゥ
リール（ｒｅｅｌ ｔｏ ｒｅｅｌ）法により複数連続
して形成する工程、２：パッケージ外に熱を放散する表
面を陽極酸化したアルミニウムキャップにＬＳＩを搭載
し、キャップを下リードを保護する下絶縁層上に接着す
るとともに、中絶縁層を介して上下に形成した上リード
と下リードの内端部とＬＳＩ上の端子とを金−錫合金結
合あるいははんだ等の接続導体を介して電気的に接続す
る工程、３：キャップ内に封止樹脂を充填し、ＬＳＩと
上記上下リードの内端部を樹脂封止する工程。４：上下
に２分された金型でパッケージ外周の中絶縁層を挟みこ
み、この金型内にフィラー等を入れて前記キャップに熱
膨張率を合わせた弗素系樹脂を加圧・加熱充填すること
により、キャップの側面と封止樹脂を覆うとともに、パ
ッケージの四隅にプリント配線板上の接続パッドと外部
接続ピン下端面との間隔を制御する凸部をもつ図１の成
形樹脂が示す構造とする工程、５：１００本の外部接続
ピンを挿入し、各外部接続ピンの上端部に露出させた４
本の芯導体と上下リードの４本の外端部とを接続導体を
介して電気的に接続する工程、６：外部接続ピンの挿入
・接続部に、前記３の工程で使用した封止樹脂か、前記
４の工程で使用した成形樹脂と同種であってフィラー含
有量が少なく若干柔軟性のある封止樹脂を充填し、接続
部を封止するとともに外部接続ピンを固定する工程、
７：複数連続した基板を個々に分離し、端子数４００と
なるＬＳＩ２個を搭載した外部接続ピン数１００のパッ
ケージを完成する工程。なお、上記外部接続ピンは、図
２に示すように、直径０．３ミリメートルの銅線からな
る４本の芯導体を各々が電気的に絶縁されるように柔軟
性のある弗素系樹脂で覆い、全体としては、直径１．５
ミリメートル、長さ５．０ミリメートルの柔軟性のある
フレキシブルな円筒構造となっている。特に、外部接続
ピン上端部には、上記上下リードの外端部との電気的接
続のために個々の芯導体上面が絶縁体の壁を介して露出
している。また、外部接続ピン下端部には、上記プリン
ト配線板上の接続パッドと電気的接続のために芯導体下
面が露出するとともに側面が絶縁体の壁を介して露出し
ている。なお、上記外部接続ピンは、電線コード状に線
として形成しリールに巻かれた材料を、適当な寸法に切
断するとともに、絶縁体や芯導体の素材に合わせ波長・
出力を調節できるレーザで所望の形状に加工した。(Embodiment 1) This embodiment is an LSI mounting package, which will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a longitudinal sectional view of the completed package, and FIG. 2 is a top view, a side view, and a bottom view of the external connection pins used in this embodiment. First, this example was formed by the following steps. 1: A lead made of copper foil having a thickness of 35 μm is formed above and below via a middle insulating layer made of a flexible fluorine resin material having a thickness of 50 μm, and a thickness of 50 μm is provided to protect the upper and lower leads. The substrate with the upper and lower insulating layers made of fluorine resin
Step of forming a plurality of layers successively by a reel to reel method 2: mounting an LSI on an aluminum cap having an anodized surface that dissipates heat outside the package, and placing the cap on a lower insulating layer that protects a lower lead Bonding and electrically connecting the inner ends of the upper and lower leads formed above and below via the middle insulating layer and the terminal on the LSI via a connection conductor such as gold-tin alloy bonding or solder. 3: A step of filling the cap with a sealing resin and sealing the LSI and the inner ends of the upper and lower leads with the resin. 4: The middle insulating layer on the outer periphery of the package is sandwiched between two upper and lower molds, and a filler or the like is put into the mold, and the cap is filled with a fluorine-based resin having the same coefficient of thermal expansion under pressure and heat. Thereby, the molding resin shown in FIG. 1 covers the side surface of the cap and the sealing resin, and has convex portions at the four corners of the package to control the distance between the connection pad on the printed wiring board and the lower end surface of the external connection pin. 5: Inserting 100 external connection pins and exposing at the upper end of each external connection pin 4
Electrically connecting the two core conductors and the four outer ends of the upper and lower leads via connection conductors; 6: sealing resin used in the above-mentioned step 3 for inserting / connecting the external connection pins. Or a step of filling the sealing resin, which is the same as the molding resin used in the step 4 and has a small filler content and a little flexibility, to seal the connection portion and fix the external connection pin;
7: A step of separating a plurality of continuous substrates individually to complete a package having 100 external connection pins and two LSIs each having 400 terminals. As shown in FIG. 2, the external connection pins cover four core conductors made of a copper wire having a diameter of 0.3 mm with a flexible fluorine resin so as to be electrically insulated from each other. , As a whole, a diameter of 1.5
It has a flexible and flexible cylindrical structure of millimeters and a length of 5.0 millimeters. In particular, at the upper end of the external connection pin, the upper surface of each core conductor is exposed via an insulator wall for electrical connection with the outer ends of the upper and lower leads. At the lower end of the external connection pin, the lower surface of the core conductor is exposed for electrical connection with the connection pad on the printed wiring board, and the side surface is exposed via an insulator wall. The external connection pin is formed as a wire in the form of a wire cord, and the material wound on a reel is cut into appropriate dimensions.
It was processed into a desired shape with a laser whose output could be adjusted.
【０００９】[0009]
【発明の効果】本発明は、微小かつ膨大な数の導体ピン
の品質管理の困難化、パッケージへの取付け工数の増
加、さらにはそのパッケージをプリント配線板上に実装
する技術の艱難化を改善し、搭載する電子部品の大型化
・高集積化、さらにはマルチチップ化によるパッケージ
の大型化・高集積化を可能とする顕著な効果を奏する。According to the present invention, it is difficult to control the quality of a very large and small number of conductor pins, increase the number of steps for mounting the package, and improve the difficulty in mounting the package on a printed wiring board. In addition, there is a remarkable effect that the size and integration of electronic components to be mounted can be increased and the package can be increased in size and integration by multi-chip.
【図１】本発明の実施例であるパッケージの拡大断面図
である。FIG. 1 is an enlarged sectional view of a package according to an embodiment of the present invention.
【図２】本発明の実施例で使用した外部接続ピンの上面
図、側面図、底面図である。FIG. 2 is a top view, a side view, and a bottom view of the external connection pins used in the embodiment of the present invention.
Claims (1)
プリント配線板上に表面実装されるパッケージにおい
て、前記電子部品と電気的に接続したリードの外端部と
接続する前記外部接続ピンを、複数の芯導体を形成した
フレキシブルなピンとし、その芯導体の各々の側面が、
当該外部接続ピンの軸線に垂直な平面上において前記軸
線に向かって絶縁体側面に形成した各凹部の内部で露出
させた、すなわち前記芯導体のそれぞれを互いに絶縁し
分離するフレキシブルな絶縁体の空洞内に露出させたこ
とを特徴とするパッケージ。1. A package mounted with an electronic component and surface-mounted on a printed wiring board via an external connection pin, wherein the external connection pin is connected to an outer end of a lead electrically connected to the electronic component. Is a flexible pin formed of a plurality of core conductors, each side of the core conductor,
The axis is located on a plane perpendicular to the axis of the external connection pin.
Exposed inside each recess formed on the side of the insulator toward the wire
Wherein the core conductors are exposed in a flexible insulator cavity that insulates and separates each of the core conductors from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19321492A JP3146288B2 (en) | 1992-06-26 | 1992-06-26 | package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19321492A JP3146288B2 (en) | 1992-06-26 | 1992-06-26 | package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0613524A JPH0613524A (en) | 1994-01-21 |
| JP3146288B2 true JP3146288B2 (en) | 2001-03-12 |
Family
ID=16304206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19321492A Expired - Fee Related JP3146288B2 (en) | 1992-06-26 | 1992-06-26 | package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3146288B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5010467B2 (en) | 2005-03-17 | 2012-08-29 | 日本電気株式会社 | Film-clad electrical device and method for manufacturing the same |
| WO2007077666A1 (en) | 2005-12-28 | 2007-07-12 | Nec Corporation | Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor |
| US8125081B2 (en) | 2006-01-16 | 2012-02-28 | Nec Corporation | Semiconductor device, printed wiring board for mounting the semiconductor device and connecting structure for these |
-
1992
- 1992-06-26 JP JP19321492A patent/JP3146288B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0613524A (en) | 1994-01-21 |
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