JP3105310B2 - Polycrystalline semiconductor film and thin film transistor manufacturing method - Google Patents
Polycrystalline semiconductor film and thin film transistor manufacturing methodInfo
- Publication number
- JP3105310B2 JP3105310B2 JP03278705A JP27870591A JP3105310B2 JP 3105310 B2 JP3105310 B2 JP 3105310B2 JP 03278705 A JP03278705 A JP 03278705A JP 27870591 A JP27870591 A JP 27870591A JP 3105310 B2 JP3105310 B2 JP 3105310B2
- Authority
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- Japan
- Prior art keywords
- substrate
- film
- silicon
- recesses
- fine powder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Description
【０００１】[0001]
【産業上の利用分野】本発明は、結晶粒径を制御したか
たちで生成させ、しかも結晶粒径がそろった多結晶半導
体膜の作製方法に関するものである。変換装置、薄膜ト
ランジスタ等の半導体装置に用いることができるもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a polycrystalline semiconductor film having a controlled crystal grain size and a uniform crystal grain size. It can be used for a semiconductor device such as a conversion device and a thin film transistor.
【０００２】[0002]
【０００３】従来、多結晶半導体膜を作製する方法とし
ては、例えば珪素の場合、溶融した珪素中から多結晶珪
素の芯を用いて液相成長によってバルク状の多結晶珪素
半導体を得る方法や、気相化学反応法等によって成膜さ
れた非晶質珪素半導体膜を加熱することによって固相成
長させ多結晶珪素半導体を得る方法、さらにはガラス基
板上等に成膜された非晶質珪素半導体膜に対してレーザ
ー照射を行うことによって多結晶珪素半導体膜を得る方
法等が知られている。Conventionally, as a method of manufacturing a polycrystalline semiconductor film, for example, in the case of silicon, a method of obtaining a bulk polycrystalline silicon semiconductor by liquid phase growth from a molten silicon using a polycrystalline silicon core, A method of obtaining a polycrystalline silicon semiconductor by solid phase growth by heating an amorphous silicon semiconductor film formed by a gas phase chemical reaction method or the like, and further, an amorphous silicon semiconductor formed on a glass substrate or the like. A method of obtaining a polycrystalline silicon semiconductor film by performing laser irradiation on the film is known.
【０００４】特に、ガラス基板上等に気相化学反応法で
非晶質半導体膜を成膜し、この非晶質半導体膜を加熱す
ることによって結晶化させる方法（固相成長法と呼ばれ
る）は、低コストであり、大面積化が可能であるという
点で、太陽電池、ＴＦＴ（薄膜トランジスタ）等に応用
することがさかんに研究されている。[0004] In particular, a method of forming an amorphous semiconductor film on a glass substrate or the like by a gas phase chemical reaction method and crystallizing the amorphous semiconductor film by heating (called a solid phase growth method) is known. Application to solar cells, TFTs (thin film transistors), and the like is being actively studied in that they are low-cost and can be made larger.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら上記従来
の固相成長によって得られる多結晶珪素半導体膜は、そ
の核発生数や結晶粒径を制御すことが困難であるという
問題があった。特に、不均一な粒径に起因する欠損の存
在や不純物の存在が問題とされていた。However, the polycrystalline silicon semiconductor film obtained by the conventional solid phase growth has a problem that it is difficult to control the number of nuclei generated and the crystal grain size. In particular, the existence of defects or impurities due to non-uniform particle size has been a problem.
【０００６】[0006]
【課題を解決するための手段】本発明は、結晶核の発生
数と結晶粒径を制御するために珪素の微粉末をこの珪素
の微粉末と概略同じ大きさを有した凹部を設けた基板上
に塗布する工程と、この基板上に塗布された珪素の微粉
末を焼結する工程と、該工程の後非晶質珪素半導体膜を
製膜する工程と、該工程の後加熱することによって前記
非晶質珪素半導体膜を結晶化させる工程とを有すること
を特徴とする多結晶半導体膜作製方法である。In order to control the number of crystal nuclei generated and the crystal grain size, the present invention relates to a method of forming a fine silicon powder on a substrate provided with a recess having substantially the same size as the fine silicon powder. A step of coating the substrate, a step of sintering the fine powder of silicon applied on the substrate, a step of forming an amorphous silicon semiconductor film after the step, and a step of heating after the step. Crystallizing the amorphous silicon semiconductor film.
【０００７】上記本発明の構成において、基板として
は、ガラス基板、単結晶または多結晶のシリコンウェ
ハ、さらには絶縁体または半導体の基板を用いることが
できる。In the structure of the present invention, a glass substrate, a single crystal or polycrystalline silicon wafer, or an insulator or semiconductor substrate can be used as the substrate.
【０００８】珪素の微粉末と概略同じ大きさの凹部を基
板上に設けるというのは、凹部の窪みの部分の大きさを
珪素の微粉末の大きさ（微粉末の直径）と概略合わせる
ということである。Providing a concave portion having substantially the same size as the fine silicon powder on the substrate means that the size of the concave portion of the concave portion is approximately matched with the size of the fine silicon powder (diameter of the fine powder). It is.
【０００９】本発明は、珪素の微粉末を結晶核として珪
素の結晶粒を成長させることによって多結晶珪素膜を形
成することを目的とするものである。そこで、本発明の
構成においては、結晶核となる珪素の微粉末を基板上に
定着させた後に非晶質珪素半導体膜を気相化学反応法等
で成膜し、５５０度〜８００度程度の温度で加熱するこ
とによって結晶化させるのである。It is an object of the present invention to form a polycrystalline silicon film by growing silicon crystal grains using silicon fine powder as crystal nuclei. Therefore, in the structure of the present invention, an amorphous silicon semiconductor film is formed by a gas phase chemical reaction method or the like after fixing a fine powder of silicon serving as a crystal nucleus on a substrate, and a temperature of about 550 to 800 degrees is used. It is crystallized by heating at a temperature.
【００１０】作製される結晶粒径の大きさを制御するに
は、基板上に設けられる凹部の大きさと間隔、さらには
珪素の微粉末の大きさを制御することによって行うこと
ができる。もちろんこの場合、珪素の微粉末に結晶性を
有しているもの（好ましくは単結晶のもの）を用いるこ
とが重要である。なぜならば、この微粉末を結晶核とし
て結晶が成長するからである。[0010] The size of the crystal grain to be produced can be controlled by controlling the size and interval of the concave portions provided on the substrate and the size of the fine silicon powder. Of course, in this case, it is important to use silicon fine powder having crystallinity (preferably single crystal). This is because a crystal grows using this fine powder as a crystal nucleus.
【００１１】本明細書中における結晶の粒径とは、基板
の上面方向からみた結晶の大きさを示すものである。本
発明の構成のように基板上に形成される薄膜状の多結晶
珪素半導体膜は、柱状に成長することが知られており、
本明細書中においてはこの柱状の結晶の柱の直径に相当
する部分を粒径と定義する。また、珪素の微粉末の大き
さは、この微粉末の直径と定義する。In the present specification, the crystal grain size indicates the size of the crystal as viewed from the upper surface direction of the substrate. It is known that a thin-film polycrystalline silicon semiconductor film formed on a substrate as in the configuration of the present invention grows in a columnar shape,
In this specification, a portion corresponding to the diameter of the column of the columnar crystal is defined as a particle size. The size of the fine silicon powder is defined as the diameter of the fine powder.
【００１２】具体的に結晶粒径を制御する方法として
は、基板表面上に設けられる凹部の大きさを変化させる
ことで、その大きさに従った結晶粒を得ることができ
る。もちろんこの場合、凹部の大きさよりも結晶核とな
る凹部の大きさが小さいことが条件である。また、結晶
核となる珪素の微粉末の大きさを変化させることによっ
て結晶粒径の大きさを変化させることがでる。Specifically, as a method of controlling the crystal grain size, the size of the concave portion provided on the substrate surface is changed, so that the crystal grain according to the size can be obtained. Of course, in this case, the condition is that the size of the concave portion serving as a crystal nucleus is smaller than the size of the concave portion. Further, the size of the crystal grain size can be changed by changing the size of the silicon fine powder serving as the crystal nucleus.
【００１３】また、結晶核となる珪素の微粉末同士が結
合して多結晶珪素半導体膜になる場合もあり、この場合
は微粉末の大きさと、結晶粒径の大きさはほとんど同じ
になる。もちろん、結晶は粒状に成長していくのである
から珪素の微粉末を結晶核として成長することに変わり
はない。In some cases, silicon fine powders serving as crystal nuclei are combined with each other to form a polycrystalline silicon semiconductor film. In this case, the size of the fine powder and the size of the crystal grain are almost the same. Of course, since the crystal grows in a granular form, there is no difference in growing the crystal using the fine powder of silicon as a crystal nucleus.
【００１４】結晶粒がそろった状態で多結晶珪素半導体
膜を得ることは、均一な膜質を大面積にわたって必要と
する太陽電池にとっては重要なことである。大粒径の結
晶をそろえることで最良の電気特性を有した多結晶珪素
半導体膜を得ることができる。これは、結晶の粒界すな
わち結晶粒と結晶粒の境に格子欠陥や半導体の電気的特
性に悪影響を与える不純物が存在しており、これら格子
欠陥や不純物の影響を最小限に抑えるために均質に大粒
径の結晶をそろえて設けることによってこの粒界の面積
の割合を最小限にすることができるからである。Obtaining a polycrystalline silicon semiconductor film in a state in which the crystal grains are uniform is important for a solar cell that requires uniform film quality over a large area. By preparing crystals having a large grain size, a polycrystalline silicon semiconductor film having the best electric characteristics can be obtained. This is because lattice defects and impurities that adversely affect the electrical characteristics of the semiconductor are present at the crystal grain boundaries, that is, at the boundaries between the crystal grains, and are homogenized to minimize the effects of these lattice defects and impurities. This is because the proportion of the area of the grain boundary can be minimized by arranging the crystals having a large grain size.
【００１５】[0015]
【実施例】〔実施例１〕本実施例は、図１に示すように
１０μｍ間隔で設けた凹部、別な見方をするならば１０
μｍ間隔で設けられた１０μｍの幅を有する凸部を基板
上に設けたものである。また、基板上に１０μｍ間隔で
凹凸を付けたものであるということもできる。以下その
作製工程を説明する。[Embodiment 1] In this embodiment, recesses provided at intervals of 10 μm as shown in FIG.
The protrusions having a width of 10 μm provided at intervals of μm are provided on a substrate. It can also be said that the substrate is provided with irregularities at intervals of 10 μm. Hereinafter, the manufacturing process will be described.
【００１６】本実施例においては、基板としてコーニン
グ７０５９ガラス基板（以下ガラス基板と記載する）を
用いた。In this embodiment, a Corning 7059 glass substrate (hereinafter referred to as a glass substrate) was used as the substrate.
【００１７】まずガラス基板１上にレジスト２（ポジ型
でもネガ型でもよい）を塗布し、公知のフォトリソグラ
フィー工程を経ることによって図１に示すようなパター
ンをガラス基板上を形成する。そして、化学的にガラス
基板をエッチングすることによってガラス基板１を０．
１μｍ〜２μｍ本実施例においては約０．３μｍの深さ
にエッチングする。そしてレジストを除去することによ
って凹部を形成する。First, a resist 2 (either a positive type or a negative type) is applied on a glass substrate 1 and a known photolithography process is performed to form a pattern as shown in FIG. 1 on the glass substrate. Then, the glass substrate 1 is set to 0.
1 μm to 2 μm In this embodiment, etching is performed to a depth of about 0.3 μm. Then, a concave portion is formed by removing the resist.
【００１８】図１には基板を断面方向から見た断面図が
示されているが、この断面から角度にして９０°異なる
方向から見た断面図も図１と同様である。すなわち、こ
の凹部は碁盤の目のように設けられているのであり、１
０ｍμ間隔に凹部がマトリックス状に設けられているの
である。FIG. 1 is a cross-sectional view of the substrate viewed from a cross-sectional direction. The cross-sectional view of the substrate viewed from a direction different from the cross-section by 90 ° is also the same as FIG. In other words, this recess is provided like a grid, and 1
The recesses are provided in a matrix at intervals of 0 μm.
【００１９】前記工程において形成した深さ約０．３μ
ｍの凹部を有するガラス基板上に大きさが約１０μｍの
珪素の微粉末を有機溶剤に溶かして塗布した。そして３
００度で１時間の時間をかけ有機溶剤を飛ばすことによ
って、珪素の微粉末をガラス基板上に固着（定着）させ
た。このようにして珪素の微粉末をガラス基板上に設け
た凹部に配置させることができた。The depth formed in the above step is about 0.3 μm.
A fine powder of silicon having a size of about 10 μm was dissolved in an organic solvent and applied onto a glass substrate having an m concave portion. And 3
The fine powder of silicon was fixed (fixed) on the glass substrate by removing the organic solvent at 00 ° C. for one hour. In this way, the fine powder of silicon could be arranged in the recess provided on the glass substrate.
【００２０】つぎに、前記工程において凹部に珪素の微
粉末が配置させられたガラス基板上にプラズマ気相反応
方法によって非晶質珪素半導体膜を１０μｍの厚さに形
成した。成膜条件は、 雰囲気 ＳｉＨ4 （流量１０〜１００ｓｃｃｍ） 基板温度 １００〜４００度 成膜圧力 ０．０１〜１．００Ｔｏｒｒ 高周波電力（１３．５６ＭＨｚ） １０〜８０Ｗ である。Next, an amorphous silicon semiconductor film having a thickness of 10 μm was formed on the glass substrate having the fine particles of silicon disposed in the recesses in the above step by a plasma gas phase reaction method. The film forming conditions are as follows: atmosphere: SiH 4 (flow rate: 10 to 100 sccm), substrate temperature: 100 to 400 ° C., film forming pressure: 0.01 to 1.00 Torr, high-frequency power (13.56 MHz), 10 to 80 W.
【００２１】前記工程によって成膜した非晶質珪素半導
体膜を６００度の温度で２４時間加熱することによって
結晶を固相成長させ、多結晶珪素半導体膜をガラス基板
上形成した。この固相成長すなわち非晶質珪素を結晶化
させるための加熱工程は、５５０度から８００度の温度
範囲において可能であり、その加熱時間も膜厚等の成膜
条件の違いによって２時間〜９６時間程度の範囲で可能
である。The amorphous silicon semiconductor film formed in the above step was heated at a temperature of 600 ° C. for 24 hours to grow crystals in a solid phase, thereby forming a polycrystalline silicon semiconductor film on a glass substrate. The solid phase growth, that is, the heating step for crystallizing the amorphous silicon can be performed in a temperature range of 550 ° C. to 800 ° C., and the heating time is 2 hours to 96 hours depending on the film forming conditions such as the film thickness. It is possible within a time range.
【００２２】本実施例において作製した多結晶珪素半導
体膜を断面ＳＥＭ写真によって観察を行ったところ、結
晶の粒径が約１０μｍであり、結晶粒のそろった多結晶
珪素半導体膜を得ることができた。When the polycrystalline silicon semiconductor film produced in this example was observed by a cross-sectional SEM photograph, a polycrystalline silicon semiconductor film having a crystal grain size of about 10 μm and having uniform crystal grains was obtained. Was.
【００２３】〔実施例２〕本実施例は、実施例１と同様
な結晶成長方法を用いることによって、基板側からＰＩ
Ｎ構造を有する光電変換装置すなわち太陽電池を作製し
たものである。[Embodiment 2] In this embodiment, the same crystal growth method as that of Embodiment 1 is used to obtain the PI from the substrate side.
A photoelectric conversion device having an N structure, that is, a solar cell was manufactured.
【００２４】本実施例には、コーニング７０５９ガラス
基板上に高濃度にＮ型の導電型を付与する不純物を添加
した裏面電極となる非晶質半導体、その上にＮ型の導電
型を有する非単結晶半導体膜、さらにＩ型となる真性ま
たは実質的に真性（不純物を人為的に添加していないと
いう意味）の非晶質珪素半導体膜、さらにＰ型の導電型
を有する非晶質半導体膜を積層し、６００度，２４時間
の温度で加熱することによって、多結晶化したものであ
る。In this embodiment, a Corning 7059 glass substrate is provided with an amorphous semiconductor serving as a back electrode in which an impurity imparting an N-type conductivity is added at a high concentration, and a non-electrode having an N-type conductivity on it. A single crystal semiconductor film, an I-type intrinsic or substantially intrinsic (meaning that no impurity is added artificially) amorphous silicon semiconductor film, and further a P-type amorphous semiconductor film Are laminated and heated at a temperature of 600 ° C. for 24 hours to be polycrystallized.
【００２５】本発明の構成のようにガラス基板表面から
結晶核を成長させる場合、前述のように結晶は柱状に成
長するので、上記のようにＮＩＰと異なる導電型を有す
る半導体層を積層しても、層全体を結晶化させることが
できる。すなわち基板とＮ層との界面で珪素の微粉末を
結晶核として発生した結晶は、Ｉ層そしてＰ層と連続的
に柱状に成長していくのである。When a crystal nucleus is grown from the surface of a glass substrate as in the structure of the present invention, the crystal grows in a columnar shape as described above. Therefore, as described above, a semiconductor layer having a conductivity type different from NIP is stacked. Also, the entire layer can be crystallized. In other words, the crystal generated at the interface between the substrate and the N layer using the fine powder of silicon as the crystal nucleus grows continuously and columnarly with the I layer and the P layer.
【００２６】以下本実施における裏面電極並びにＮＩＰ
各層の非晶質珪素半導体の作製条件を示す。電極となる
Ｎ+ 層の成膜条件は、 雰囲気 ＳｉＨ4 （流量５０ｓｃｃｍ）（Ｐ
Ｈ3 １０００ｐｐｍ添加） 基板温度 １００〜４００度 成膜圧力 ０．０１〜１．００Ｔｏｒｒ 高周波電力 １０〜８０Ｗ（１３．５６ＭＨｚ） であり、７０００Åの厚さに成膜した。The back electrode and NIP in this embodiment
The production conditions of the amorphous silicon semiconductor of each layer are shown. The conditions for forming the N + layer serving as an electrode are as follows: atmosphere SiH 4 (flow rate 50 sccm) (P
H 3 1000 ppm added) substrate temperature 100 to 400 degrees deposition pressure 0.01~1.00Torr frequency power 10~80W (13.56MHz), was deposited to a thickness of 7000 Å.
【００２７】Ｎ層の成膜条件は、 雰囲気 ＳｉＨ4 （５０ｓｃｃｍ）（ＰＨ3
１０ｐｐｍ添加） 基板温度 １００〜４００度 成膜圧力 ０．０１〜１．００Ｔｏｒｒ 高周波電力 １０〜８０Ｗ（１３．５６ＭＨｚ） であり、５００Åの厚さに成膜した。The conditions for forming the N layer are as follows: atmosphere SiH 4 (50 sccm) (PH 3
Substrate temperature: 100 to 400 degrees, film forming pressure: 0.01 to 1.00 Torr, high frequency power: 10 to 80 W (13.56 MHz), and a film having a thickness of 500 °.
【００２８】Ｉ層の成膜条件は、 雰囲気 ＳｉＨ4 （１０〜１００ｓｃｃｍ） 基板温度 １００〜４００度 成膜圧力 ０．０１〜１．００Ｔｏｒｒ 高周波電力 １０〜８０Ｗ（１３．５６ＭＨｚ） であり、１０μｍの厚さに成膜した。The film formation conditions for the I layer are as follows: atmosphere SiH 4 (10 to 100 sccm), substrate temperature 100 to 400 degrees, film formation pressure 0.01 to 1.00 Torr, high frequency power 10 to 80 W (13.56 MHz), and 10 μm The film was formed to a thickness.
【００２９】Ｐ層の成膜条件は、 雰囲気 ＳｉＨ4 （５０ｓｃｃｍ）（Ｂ2Ｈ
6 １０ｐｐｍ添加） 基板温度 １００〜４００度 成膜圧力 ０．０１〜１．００Ｔｏｒｒ 高周波電力 １０〜８０Ｗ（１３．５６ＭＨｚ） であり、５００Åの厚さに成膜した。The conditions for forming the P layer are as follows: atmosphere SiH 4 (50 sccm) (B 2 H
6 10 ppm added) Substrate temperature 100 to 400 degrees Deposition pressure 0.01 to 1.00 Torr High frequency power 10 to 80 W (13.56 MHz), and formed a film with a thickness of 500 °.
【００３０】その後、Ｎ2 雰囲気中において６００度の
温度で２４時間加熱し、結晶化を行った。この結晶化の
ための加熱は４５０度〜８００度好ましくは５５０度か
ら７００度の温度で可能である。After that, crystallization was performed by heating at a temperature of 600 ° C. for 24 hours in an N 2 atmosphere. Heating for this crystallization can be performed at a temperature of 450 to 800 degrees, preferably 550 to 700 degrees.
【００３１】本実施例のような構成をとることによっ
て、結晶粒径のそろった多結晶半導体膜を用いた太陽電
池を得ることができた。By employing the structure as in this embodiment, a solar cell using a polycrystalline semiconductor film having a uniform crystal grain size was obtained.
【００３２】[0032]
【発明の効果】本発明の構成のように基板に凹部を周期
的に設け、その凹部に珪素の微粉末を固着させ、その上
に非晶質珪素を成膜し、加熱結晶化させることで、結晶
粒径のそろった多結晶珪素半導体膜を得ることができ
た。そして、本発明の構成をとることによって得られる
多結晶珪素半導体膜は、太陽電池，薄膜トランジスタの
チャネル形成領域やソース，ドレイン領域の半導体層，
他の半導体装置に応用することができる。According to the present invention, a concave portion is periodically provided in a substrate, fine powder of silicon is fixed in the concave portion, amorphous silicon is formed thereon, and heat crystallization is performed. Thus, a polycrystalline silicon semiconductor film having a uniform crystal grain size was obtained. The polycrystalline silicon semiconductor film obtained by adopting the structure of the present invention can be used for forming a semiconductor layer in a channel formation region or a source / drain region of a solar cell or a thin film transistor.
It can be applied to other semiconductor devices.
【００３３】以上の説明においては、珪素を例として説
明を行ってきたが、珪素以外の半導体を用いることも可
能である。そして、非晶質半導体の成膜方法もプラズマ
ＣＶＤ法に限定されず、他のＣＶＤ法やスパッタ法等を
用いてもよい。In the above description, silicon has been described as an example, but a semiconductor other than silicon can be used. The method for forming the amorphous semiconductor is not limited to the plasma CVD method, and another CVD method, a sputtering method, or the like may be used.
【図１】 本発明の構成を用いた実施例１における基板
の加工工程を示すものである。FIG. 1 shows a substrate processing step in Example 1 using the configuration of the present invention.
１ ガラス基板 ２ レジスト 1 Glass substrate 2 Resist
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/18 - 21/20 H01L 21/34 - 21/36 H01L 21/84 ──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/18-21/20 H01L 21/34-21/36 H01L 21/84
Claims (9)
し、 前記有機溶剤を蒸発させ、前記珪素の微粉末を前記基板
上の前記複数の凹部に固着させ、 前記基板上に非晶質珪素膜を形成し、 前記非晶質半導体膜を加熱し、多結晶化させる多結晶半
導体膜作製方法。1. A plurality of recesses are formed on a substrate, and a fine powder of silicon dissolved in an organic solvent is applied on the substrate.
And, wherein the organic solvent is evaporated, the fine powder of the silicon is adhered to the plurality of recesses on the substrate, an amorphous silicon film formed on the substrate, and heating the amorphous semiconductor film And a method for forming a polycrystalline semiconductor film to be polycrystallized.
し、 前記有機溶剤を蒸発させ、前記珪素の微粉末を前記基板
上の前記複数の凹部に固着させ、 前記基板の上に高濃度のＮ型の導電型を付与する不純物
を添加した第一の非晶質珪素膜を形成し、 前記第一の非晶質珪素膜の上方にＮ型の導電型を付与す
る不純物を添加した第二の非晶質珪素膜を形成し、 前記第二の非晶質珪素膜の上方にＩ型となる第三の非晶
質珪素膜を形成し、 前記第三の非晶質珪素膜の上方にＰ型の導電型を付与す
る不純物を添加した第四の非晶質珪素膜を形成し、 前記第一乃至第四の非晶質珪素膜を加熱し、多結晶化さ
せる多結晶半導体膜作製方法。 2. A plurality of concave portions are formed on a substrate, and a fine powder of silicon dissolved in an organic solvent is applied on the substrate.
Then, the organic solvent is evaporated, and the silicon fine powder is applied to the substrate.
An impurity that is fixed to the plurality of recesses above and that imparts a high-concentration N-type conductivity on the substrate;
Is formed, and an N-type conductivity type is imparted above the first amorphous silicon film.
Forming a second amorphous silicon film to which an impurity is added, and forming a third amorphous silicon film above the second amorphous silicon film as an I-type.
Forming a porous silicon film and imparting a P-type conductivity type above the third amorphous silicon film.
Forming a fourth amorphous silicon film to which impurities are added, and heating the first to fourth amorphous silicon films to form a polycrystalline silicon film.
Method for producing a polycrystalline semiconductor film.
末の大きさとは概略同一である請求項１または２に記載
の多結晶半導体膜作製方法。 3. The size of the plurality of recesses and the fine powder of silicon.
3. The size according to claim 1, wherein the size of the powder is substantially the same.
Method for manufacturing a polycrystalline semiconductor film.
ス状に設けられている請求項１乃至３のいずれか一に記
載の多結晶半導体膜作製方法。 4. The substrate according to claim 1 , wherein said plurality of recesses are formed on said substrate.
4. The device according to claim 1, which is provided in the shape of
The method for producing a polycrystalline semiconductor film described above.
多結晶のシリコンウェハまたは絶縁体もしくは半導体のPolycrystalline silicon wafer or insulator or semiconductor
基板である請求項１乃至４のいずれか一つに記載の多結5. The multiple bond according to claim 1, which is a substrate.
晶半導体膜作製方法。Method for manufacturing a crystalline semiconductor film.
し、And 前記有機溶剤を蒸発させ、前記珪素の微粉末を前記基板The organic solvent is evaporated, and the silicon fine powder is applied to the substrate.
上の前記複数の凹部に固着させ、Fixed to the plurality of recesses above, 前記基板上に非晶質珪素膜を形成し、Forming an amorphous silicon film on the substrate, 前記非晶質半導体膜を加熱し、多結晶化させ、多結晶半The amorphous semiconductor film is heated and polycrystallized,
導体膜を作製し、Prepare a conductor film, 前記多結晶半導体膜に、ソース領域、ドレイン領域及びIn the polycrystalline semiconductor film, a source region, a drain region and
チャネル領域を形成することを特徴とする薄膜トランジThin film transistor characterized by forming a channel region
スタ作製方法。Star manufacturing method.
末の大きさとは概略同一である請求項６に記載の薄膜ト7. The thin film transistor according to claim 6, wherein the size of the powder is substantially the same.
ランジスタ作製方法。A method for manufacturing a transistor.
ス状に設けられている請求項６または７に記載の薄膜ト8. The thin film transistor according to claim 6, wherein the thin film transistor is provided in the form of a thin film.
ランジスタ作製方法。A method for manufacturing a transistor.
多結晶のシリコンウェハまたは絶縁体もしくは半導体のPolycrystalline silicon wafer or insulator or semiconductor
基板である請求項６乃至８のいずれか一つに記載の薄膜9. The thin film according to claim 6, which is a substrate.
トランジスタ作製方法。Method for manufacturing transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03278705A JP3105310B2 (en) | 1991-09-30 | 1991-09-30 | Polycrystalline semiconductor film and thin film transistor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03278705A JP3105310B2 (en) | 1991-09-30 | 1991-09-30 | Polycrystalline semiconductor film and thin film transistor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0590159A JPH0590159A (en) | 1993-04-09 |
| JP3105310B2 true JP3105310B2 (en) | 2000-10-30 |
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ID=17601045
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Families Citing this family (2)
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|---|---|---|---|---|
| JP3431647B2 (en) | 1992-10-30 | 2003-07-28 | 株式会社半導体エネルギー研究所 | Semiconductor device, method for manufacturing same, method for manufacturing memory device, and method for laser doping |
| US6667494B1 (en) | 1997-08-19 | 2003-12-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and semiconductor display device |
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