JP3097608B2 - Depletion type semiconductor device and method of manufacturing the same - Google Patents
Depletion type semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP3097608B2 JP3097608B2 JP09181462A JP18146297A JP3097608B2 JP 3097608 B2 JP3097608 B2 JP 3097608B2 JP 09181462 A JP09181462 A JP 09181462A JP 18146297 A JP18146297 A JP 18146297A JP 3097608 B2 JP3097608 B2 JP 3097608B2
- Authority
- JP
- Japan
- Prior art keywords
- shaped groove
- type
- forming
- diffusion region
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ディプレッション
型半導体装置に関し、特に縦型ＭＯＳＦＥＴにおいてチ
ャネル領域がソース領域と同じ導電型になっているディ
プレッション型半導体装置に関する。The present invention relates to a depletion type semiconductor device, and more particularly to a depletion type semiconductor device in which a channel region of a vertical MOSFET has the same conductivity type as a source region.
【０００２】[0002]
【従来の技術】図２は従来からのディプレッション型半
導体装置の一例として、ディプレッション型の縦型ＭＯ
ＳＦＥＴの構造を説明するための工程図である。2. Description of the Related Art FIG. 2 shows an example of a conventional depletion type semiconductor device, which is a depletion type vertical MO.
FIG. 5 is a process diagram for describing the structure of the SFET.
【０００３】この図に示したディプレッション型半導体
装置は縦型２重拡散ＭＯＳＦＥＴ（ＶＤＭＯＳＦＥＴ：
Vertical Double-diffused MOS FET）であり、ゲート電
極６への印加電圧が０Ｖのときオン状態である。ゲート
電極に負の電圧を印加することにより、オフ状態に移行
させることができる。The depletion type semiconductor device shown in FIG. 1 is a vertical double diffusion MOSFET (VDMOSFET:
Vertical Double-diffused MOS FET), and is on when the voltage applied to the gate electrode 6 is 0V. By applying a negative voltage to the gate electrode, the gate electrode can be turned off.
【０００４】以下に、このような従来からのＶＤＭＯＳ
ＦＥＴの製造方法を説明する。The following describes such a conventional VDMOS.
A method for manufacturing an FET will be described.
【０００５】まず図２の（Ａ）に示すように、ドレイン
領域となるＮ型シリコン半導体基板１上にゲート酸化膜
５をマスクとしてセルフアライン方式によりＰ型拡散領
域２と、ソース領域となるＮ型拡散層領域３とを２重拡
散して形成する。First, as shown in FIG. 2A, a P-type diffusion region 2 and an N-type source region are formed on a N-type silicon semiconductor substrate 1 serving as a drain region by a self-alignment method using a gate oxide film 5 as a mask. The mold diffusion layer region 3 is formed by double diffusion.
【０００６】次に図２の（Ｂ）に示すように、ゲート酸
化膜５を一旦除去し、Ｎ型シリコン基板１上の全面ある
いは一部分（図２では、Ｐ型拡散領域２の表面に露出し
た部分を覆う領域）にＮ型不純物を拡散して、チャネル
領域４を形成する。Next, as shown in FIG. 2B, the gate oxide film 5 is once removed, and the entire surface or a part of the gate oxide film on the N-type silicon substrate 1 (in FIG. 2, exposed on the surface of the P-type diffusion region 2). The channel region 4 is formed by diffusing an N-type impurity into the region covering the portion.
【０００７】さらに図２の（Ｃ）に示すように、再度ゲ
ート酸化膜５をチャネル領域４の上部に形成し、更にゲ
ート酸化膜５上にゲート電極６を形成する。次にＮ型拡
散領域３上にソース電極７を形成した後、Ｎ型シリコン
基板１の裏面にドレイン電極８を形成する。As shown in FIG. 2C, a gate oxide film 5 is formed again on the channel region 4, and a gate electrode 6 is formed on the gate oxide film 5. Next, after forming a source electrode 7 on the N-type diffusion region 3, a drain electrode 8 is formed on the back surface of the N-type silicon substrate 1.
【０００８】[0008]
【発明が解決しようとする課題】従来の技術においては
以下の２点について問題が発生する。The conventional technique has the following two problems.
【０００９】第一に、チャネル領域４を形成するにあた
り、Ｎ型不純物をＮ型シリコン基板１上の一部分に形成
するため、Ｐ型拡散領域２の間隔を広げる必要がある
（例えば約１０μｍ）という問題である。First, in forming the channel region 4, it is necessary to increase the interval between the P-type diffusion regions 2 (for example, about 10 μm) in order to form N-type impurities on a part of the N-type silicon substrate 1. It is a problem.
【００１０】その理由としては、高耐圧ＭＯＳＦＥＴ
（例えば、耐圧２００Ｖ以上）の場合、Ｎ型シリコン基
板１の表面濃度が高くなると、空乏層が広がらなくな
り、耐圧が低下してしまう。よって、できるだけ表面濃
度を低くしておくことが望ましいが、Ｎ型不純物をＮ型
シリコン基板１上の一部分に形成する時、Ｐ型拡散領域
２形成時の横広がり（通常拡散深さの０．８５倍）、及
びパターニング工程（ＰＲともいう）での目ずれを考慮
する必要があるためである。[0010] The reason is that high breakdown voltage MOSFET
In the case of (for example, withstand voltage of 200 V or more), if the surface concentration of the N-type silicon substrate 1 increases, the depletion layer does not spread and the withstand voltage decreases. Therefore, it is desirable to keep the surface concentration as low as possible. However, when an N-type impurity is formed in a part of the N-type silicon substrate 1, the P-type diffusion region 2 is formed to have a lateral spread (usually a diffusion depth of 0. This is because it is necessary to consider misalignment in the patterning step (also referred to as PR).
【００１１】第二に、ゲート電極６を通常のエンハンス
メント型ＭＯＳＦＥＴに比べて、チャネル領域４上部に
多めに覆う必要がある。Second, it is necessary to cover the gate electrode 6 over the channel region 4 more than in a normal enhancement type MOSFET.
【００１２】その理由としては、エンハンスメント型Ｍ
ＯＳＦＥＴの場合、ゲート電極（通常ポリシリコン膜）
の形成を拡散領域形成以前に行うためチャネル上部の覆
う幅を比較的小さくできる。しかし、ディプレッション
型ＭＯＳＦＥＴの場合、ゲート電極は拡散領域形成後に
形成するため、パターニング工程での目ずれを考慮する
必要がある。The reason is that the enhancement type M
In the case of OSFET, the gate electrode (usually a polysilicon film)
Is formed before the formation of the diffusion region, the width of the upper portion of the channel can be relatively reduced. However, in the case of the depletion type MOSFET, since the gate electrode is formed after the formation of the diffusion region, it is necessary to consider misalignment in the patterning step.
【００１３】本発明の目的は、上記従来技術の課題に鑑
み、Ｐ型拡散領域の間隔の低減及びパターニング工程で
の目ずれの考慮をなくすディプレッション型半導体装置
及びその製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a depletion type semiconductor device and a method of manufacturing the same, which reduce the distance between P-type diffusion regions and eliminate misalignment in a patterning process in view of the above-mentioned problems in the prior art. .
【００１４】[0014]
【課題を解決するための手段】上記目的を達成するため
に本発明のディプレッション型半導体装置の製造方法
は、Ｎ型半導体基板の一表面にＶ字型溝あるいはＵ字型
溝を形成し、該Ｖ字型溝あるいはＵ字型溝の内周面を第
１の絶縁膜で覆った後、前記Ｖ字型溝あるいはＵ字型溝
の外側の前記Ｎ型半導体基板の表面にＰ型拡散領域を形
成し、該Ｐ型拡散領域の表面を、前記Ｖ字型溝あるいは
Ｕ字型溝の縁部を除いて第２の絶縁膜で覆い、そして、
該第２の絶縁膜で覆われていない前記Ｖ字型溝あるいは
Ｕ字型溝の縁部よりＮ型不純物を拡散またはイオン注入
してチャネル領域を形成した後、前記第２の絶縁膜を除
去し、前記Ｐ型拡散領域の表面にソース領域となるＮ型
拡散領域を形成し、そして、前記第１の絶縁膜を除去
し、前記Ｖ字型溝あるいはＵ字型溝の内周面にゲート
膜、ゲート電極を順次形成し、前記Ｎ型拡散領域上にソ
ース電極を形成し、前記Ｎ型シリコン基板の裏面にドレ
イン電極を形成して縦型ＭＯＳＦＥＴを製造することを
特徴とする。In order to achieve the above object, a method of manufacturing a depletion type semiconductor device according to the present invention.
Is a V-shaped groove or a U-shaped groove on one surface of an N-type semiconductor substrate.
A groove is formed, and the inner peripheral surface of the V-shaped groove or the U-shaped groove is
After covering with the insulating film of No. 1, the V-shaped groove or the U-shaped groove
Forming a p-type diffusion region on the surface of the n-type semiconductor substrate outside
And forming the surface of the P-type diffusion region with the V-shaped groove or
Cover with a second insulating film except for the edge of the U-shaped groove, and
The V-shaped groove not covered with the second insulating film or
Diffusion or ion implantation of N-type impurities from the edge of U-shaped groove
After the formation of the channel region, the second insulating film is removed.
Then, an N-type source region is formed on the surface of the P-type diffusion region.
Forming a diffusion region and removing the first insulating film;
And a gate is provided on the inner peripheral surface of the V-shaped groove or the U-shaped groove.
A film and a gate electrode are sequentially formed, and a silicon layer is formed on the N-type diffusion region.
And a drain electrode is formed on the back surface of the N-type silicon substrate.
Manufacturing of vertical MOSFET by forming in-electrode
Features .
【００１５】[0015]
【００１６】（作用）上記のとおりの発明では、Ｎ型半
導体基板の表面に断面がＶ字型あるいはＵ字型の溝を形
成し、前記Ｖ字型あるいはＵ字型の溝の外側の前記Ｎ型
半導体基板の表面にＰ型拡散領域およびＮ型拡散領域を
この順で積層形成することにより、Ｐ型拡散領域の間隔
が低減される。その結果、従来からのＶＤＭＯＳＦＥＴ
と同特性を得るのにセルサイズを小さくできる。さら
に、ゲート電極をＶ字型あるいはＵ字型の溝の内周面に
形成するので、パターニング工程での目ずれを考慮する
必要もなくなる。(Operation) In the invention described above, a groove having a V-shaped or U-shaped cross section is formed on the surface of the N-type semiconductor substrate, and the N-shaped groove is formed outside the V-shaped or U-shaped groove. By forming a P-type diffusion region and an N-type diffusion region in this order on the surface of the type semiconductor substrate, the distance between the P-type diffusion regions is reduced. As a result, the conventional VDMOSFET
The cell size can be reduced to obtain the same characteristics. Further, since the gate electrode is formed on the inner peripheral surface of the V-shaped or U-shaped groove, there is no need to consider misalignment in the patterning step.
【００１７】[0017]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１８】図１は本発明のディプレッション型半導体
装置の一実施形態による縦型のＵ溝ＭＯＳＦＥＴの構造
を説明するための工程図であり、図２と同一部材には同
一番号が付してある。FIG. 1 is a process diagram for explaining the structure of a vertical U-groove MOSFET according to an embodiment of the depletion type semiconductor device of the present invention. The same members as those in FIG. 2 are denoted by the same reference numerals. .
【００１９】本形態のディプレッション型半導体装置
は、縦型２重拡散ＭＯＳＦＥＴ（ＶＤＭＯＳＦＥＴ）と
同特性を縦型のＵ溝ＭＯＳＦＥＴで実現している。すな
わち、図１の（ｃ）において、Ｎ型シリコン基板１の表
面に断面がＵ字型の溝（以下、Ｕ字型溝という）１１が
形成されている。このＵ字型溝１１の内周面はゲート酸
化膜５で被覆されていて、ゲート酸化膜５上にはゲート
電極６が形成されている。また、Ｕ字型溝１１の外側の
Ｎ型シリコン基板１の表面にはＰ型拡散領域２およびＮ
型拡散領域３がこの順で積層形成されており、このＰ型
拡散領域２に前記Ｕ字型の溝１１の側壁に沿ってチャネ
ル領域４となるＮ型領域が形成されている。このような
形態では、チャネル領域４の形成方向が図２に示したＶ
ＤＭＯＳＦＥＴと異なり、縦方向に形成される。The depletion type semiconductor device of this embodiment realizes the same characteristics as a vertical double diffusion MOSFET (VDMOSFET) by a vertical U-groove MOSFET. That is, in FIG. 1C, a groove 11 having a U-shaped cross section (hereinafter, referred to as a U-shaped groove) 11 is formed on the surface of the N-type silicon substrate 1. The inner peripheral surface of the U-shaped groove 11 is covered with a gate oxide film 5, and a gate electrode 6 is formed on the gate oxide film 5. The surface of the N-type silicon substrate 1 outside the U-shaped groove 11 has a P-type diffusion region 2 and an N-type
D-type diffusion regions 3 are stacked in this order, and an N-type region serving as a channel region 4 is formed in the P-type diffusion region 2 along the side wall of the U-shaped groove 11. In such an embodiment, the direction in which channel region 4 is formed is V V shown in FIG.
Unlike the DMOSFET, it is formed in the vertical direction.
【００２０】次に、本実施形態の製造方法を説明する。Next, the manufacturing method of this embodiment will be described.
【００２１】まず図１の（ａ）に示すように、Ｎ型不純
物が低濃度に添加されてなるＮ型半導体基板１の一表面
にＵ字型溝１１を異方性エッチングにより形成する。First, as shown in FIG. 1A, a U-shaped groove 11 is formed on one surface of an N-type semiconductor substrate 1 to which an N-type impurity is added at a low concentration by anisotropic etching.
【００２２】次に図１の（ｂ）に示すように、Ｕ字型溝
１１の内周面を絶縁膜１２で覆った後、Ｕ字型溝１１の
外側のＮ型シリコン基板１の表面に通常濃度のＰ型拡散
領域２を形成する。次にＰ型拡散領域２表面を、Ｕ字型
溝１１の縁部を除いて絶縁膜１３により覆う。そして、
絶縁膜１３で覆われていないＵ字型溝１１の縁部よりＮ
型不純物を拡散またはイオン注入して、チャネル領域４
となる低濃度のＮ型領域を形成する。Next, as shown in FIG. 1B, after the inner peripheral surface of the U-shaped groove 11 is covered with an insulating film 12, the surface of the N-type silicon substrate 1 outside the U-shaped groove 11 is formed. A P-type diffusion region 2 having a normal concentration is formed. Next, the surface of the P-type diffusion region 2 is covered with the insulating film 13 except for the edge of the U-shaped groove 11. And
N from the edge of the U-shaped groove 11 not covered with the insulating film 13
Channel region 4 by diffusing or ion-implanting
To form a low concentration N-type region.
【００２３】さらに絶縁膜１３を除去し、図１の（ｃ）
に示すようにＰ型拡散領域２表面にソース領域となる高
濃度のＮ型拡散領域３を形成した後、Ｕ字型溝１１の内
周面を覆っていた絶縁膜１２を除去し、Ｕ字型溝１１の
内周面にゲート酸化膜（薄い絶縁膜）５、ゲート電極
（導電膜）６を順次形成する。そしてＮ型拡散領域３上
にソース電極７を形成した後、Ｎ型シリコン基板１の裏
面にドレイン電極８を形成する。Further, the insulating film 13 is removed, and FIG.
After forming a high-concentration N-type diffusion region 3 serving as a source region on the surface of the P-type diffusion region 2, the insulating film 12 covering the inner peripheral surface of the U-shaped groove 11 is removed. A gate oxide film (thin insulating film) 5 and a gate electrode (conductive film) 6 are sequentially formed on the inner peripheral surface of the mold groove 11. Then, after forming the source electrode 7 on the N-type diffusion region 3, the drain electrode 8 is formed on the back surface of the N-type silicon substrate 1.
【００２４】このような形態によれば、従来技術の有す
る問題は解決される。すなわち、本形態においてはチャ
ネル領域４を縦方向に形成していることにより、空乏層
が広がる領域はＵ字型溝１１の下部であり、そしてＵ字
型溝の幅を約１μｍにできるのでＰ型拡散領域２の間隔
を狭くする事ができる。しかもゲート電極６をＵ字型溝
１１表面に形成できるので、パターニング工程での目ず
れを考慮する必要もなくなる。According to such an embodiment, the problems of the prior art can be solved. That is, in the present embodiment, since the channel region 4 is formed in the vertical direction, the region where the depletion layer spreads is below the U-shaped groove 11, and the width of the U-shaped groove can be reduced to about 1 μm. The interval between the mold diffusion regions 2 can be reduced. Moreover, since the gate electrode 6 can be formed on the surface of the U-shaped groove 11, there is no need to consider misalignment in the patterning step.
【００２５】なお、上記の実施形態はゲート膜に酸化膜
を使用したが、例えば窒化膜でもよい。またゲート電極
としてポリシリコン膜を使用したが、アルミ電極でも良
い。また、Ｕ字型溝１１に代えてＶ字型溝であっても良
い。In the above embodiment, an oxide film is used for the gate film. However, for example, a nitride film may be used. Although a polysilicon film is used as the gate electrode, an aluminum electrode may be used. Further, a V-shaped groove may be used instead of the U-shaped groove 11.
【００２６】[0026]
【発明の効果】以上説明したように本発明は、Ｎ型半導
体基板の表面に断面がＶ字型あるいはＵ字型の溝が形成
され、このＶ字型あるいはＵ字型の溝の外側のＮ型半導
体基板の表面にＰ型拡散領域およびＮ型拡散領域がこの
順で積層形成され、このＰ型拡散領域に前記Ｖ字型ある
いはＵ字型の溝の側壁に沿ってチャネル領域となるＮ型
領域が縦方向に形成されている縦型ＭＯＳＦＥＴを構成
するディプレッション型半導体装置を提供することによ
り、Ｐ型拡散領域の間隔の低減及びパターニング工程で
の目ずれを考慮しなくても済むようになる。As described above, according to the present invention, a groove having a V-shaped or U-shaped cross section is formed on the surface of an N-type semiconductor substrate, and an N-shaped groove outside the V-shaped or U-shaped groove is formed. A P-type diffusion region and an N-type diffusion region are formed in this order on the surface of the type semiconductor substrate, and an N-type channel region is formed in the P-type diffusion region along the side wall of the V-shaped or U-shaped groove. By providing a depletion-type semiconductor device that constitutes a vertical MOSFET in which regions are formed in the vertical direction, it is not necessary to consider the reduction of the interval between P-type diffusion regions and misalignment in a patterning process. .
【図１】本発明のディプレッション型半導体装置の一実
施形態による縦型のＵ溝ＭＯＳＦＥＴの構造を説明する
ための工程図である。FIG. 1 is a process diagram for explaining a structure of a vertical U-groove MOSFET according to one embodiment of a depletion type semiconductor device of the present invention.
【図２】従来からのディプレッション型半導体装置の一
例として、ディプレッション型の縦型ＭＯＳＦＥＴの構
造を説明するための工程図である。FIG. 2 is a process diagram for explaining a structure of a depression type vertical MOSFET as an example of a conventional depression type semiconductor device.
１ Ｎ型シリコン基板（ドレイン領域） ２ Ｐ型拡散領域 ３ Ｎ型拡散領域（ソース領域） ４ チャネル領域（Ｎ型領域） ５ ゲート酸化膜 ６ ゲート電極 ７ ソース電極 ８ ドレイン電極 １１ Ｕ字型溝 １２、１３ 絶縁膜 REFERENCE SIGNS LIST 1 N-type silicon substrate (drain region) 2 P-type diffusion region 3 N-type diffusion region (source region) 4 channel region (N-type region) 5 gate oxide film 6 gate electrode 7 source electrode 8 drain electrode 11 U-shaped groove 12 , 13 Insulating film
Claims (1)
いはＵ字型溝を形成し、該Ｖ字型溝あるいはＵ字型溝の
内周面を第１の絶縁膜で覆った後、前記Ｖ字型溝あるい
はＵ字型溝の外側の前記Ｎ型半導体基板の表面にＰ型拡
散領域を形成し、該Ｐ型拡散領域の表面を、前記Ｖ字型
溝あるいはＵ字型溝の縁部を除いて第２の絶縁膜で覆
い、そして、該第２の絶縁膜で覆われていない前記Ｖ字
型溝あるいはＵ字型溝の縁部よりＮ型不純物を拡散また
はイオン注入してチャネル領域を形成した後、前記第２
の絶縁膜を除去し、前記Ｐ型拡散領域の表面にソース領
域となるＮ型拡散領域を形成し、そして、前記第１の絶
縁膜を除去し、前記Ｖ字型溝あるいはＵ字型溝の内周面
にゲート膜、ゲート電極を順次形成し、前記Ｎ型拡散領
域上にソース電極を形成し、前記Ｎ型シリコン基板の裏
面にドレイン電極を形成して縦型ＭＯＳＦＥＴを製造す
る、ディプレッション型半導体装置の製造方法。After forming a V-shaped groove or a U-shaped groove on one surface of an N-type semiconductor substrate and covering an inner peripheral surface of the V-shaped groove or the U-shaped groove with a first insulating film. Forming a P-type diffusion region on the surface of the N-type semiconductor substrate outside the V-shaped groove or the U-shaped groove, and forming a surface of the P-type diffusion region on the surface of the V-shaped groove or the U-shaped groove; Except for the edge, the semiconductor substrate is covered with a second insulating film, and N-type impurities are diffused or ion-implanted from the edge of the V-shaped groove or the U-shaped groove which is not covered with the second insulating film. After forming the channel region, the second
Is removed, an N-type diffusion region serving as a source region is formed on the surface of the P-type diffusion region, and the first insulation film is removed, and the V-shaped groove or the U-shaped groove is removed. Forming a vertical MOSFET by sequentially forming a gate film and a gate electrode on the inner peripheral surface, forming a source electrode on the N-type diffusion region, and forming a drain electrode on the back surface of the N-type silicon substrate; A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09181462A JP3097608B2 (en) | 1997-07-07 | 1997-07-07 | Depletion type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09181462A JP3097608B2 (en) | 1997-07-07 | 1997-07-07 | Depletion type semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1126761A JPH1126761A (en) | 1999-01-29 |
| JP3097608B2 true JP3097608B2 (en) | 2000-10-10 |
Family
ID=16101188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09181462A Expired - Fee Related JP3097608B2 (en) | 1997-07-07 | 1997-07-07 | Depletion type semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3097608B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000357795A (en) * | 1999-06-17 | 2000-12-26 | Nec Kansai Ltd | Manufacture of depression-type semiconductor device |
| JP4678902B2 (en) * | 1999-09-02 | 2011-04-27 | 富士電機システムズ株式会社 | Silicon carbide UMOS semiconductor device and method of manufacturing the same |
| JP4797280B2 (en) * | 2001-05-29 | 2011-10-19 | パナソニック電工株式会社 | Semiconductor device |
| JP2006344759A (en) * | 2005-06-08 | 2006-12-21 | Sharp Corp | Trench type mosfet and its fabrication process |
-
1997
- 1997-07-07 JP JP09181462A patent/JP3097608B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1126761A (en) | 1999-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6614075B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP3221766B2 (en) | Method for manufacturing field effect transistor | |
| KR100244282B1 (en) | Transistor for high voltage and manufactruing method thereof | |
| US5981997A (en) | Horizontal field effect transistor and method of manufacturing the same | |
| US20050205897A1 (en) | High voltage insulated-gate transistor | |
| KR960012539A (en) | Semiconductor device and manufacturing method | |
| JPH0897411A (en) | Lateral trench mos fet having high withstanding voltage and its manufacture | |
| JPH06333942A (en) | Manufacture of transistor | |
| KR950024326A (en) | Semiconductor device having trench structure and manufacturing method thereof | |
| US20020182810A1 (en) | High power semiconductor device and fabrication method thereof | |
| US20210217878A1 (en) | Diffused field-effect transistor | |
| JP3219045B2 (en) | Manufacturing method of vertical MISFET | |
| US5952700A (en) | MOSFET device with unsymmetrical LDD region | |
| US6022790A (en) | Semiconductor process integration of a guard ring structure | |
| US6207518B1 (en) | Method of manufacturing semiconductor device | |
| US20200251590A1 (en) | Semiconductor structure and fabrication method thereof | |
| KR100290913B1 (en) | High voltage devicd and method for manufacturing the same | |
| JPH0237777A (en) | Vertical type field-effect transistor | |
| JP3097608B2 (en) | Depletion type semiconductor device and method of manufacturing the same | |
| KR100227644B1 (en) | Manufacturing method of a transistor | |
| JP3320476B2 (en) | Method for manufacturing semiconductor device | |
| JP2807718B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6875658B2 (en) | High-voltage device with improved punch through voltage and process for same compatible with low-voltage device process | |
| KR20050108201A (en) | Method for manufacturing high voltage transistor | |
| JP3223125B2 (en) | Semiconductor device and method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070811 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080811 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080811 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090811 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090811 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100811 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100811 Year of fee payment: 10 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100811 Year of fee payment: 10 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110811 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110811 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120811 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120811 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130811 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |