JP3097070B2 - Inverter control circuit - Google Patents
Inverter control circuitInfo
- Publication number
- JP3097070B2 JP3097070B2 JP07019395A JP1939595A JP3097070B2 JP 3097070 B2 JP3097070 B2 JP 3097070B2 JP 07019395 A JP07019395 A JP 07019395A JP 1939595 A JP1939595 A JP 1939595A JP 3097070 B2 JP3097070 B2 JP 3097070B2
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- corresponding value
- output voltage
- inverter output
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Inverter Devices (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はインバータの制御回路に
関するもので、さらに詳しく言えば、その出力を系統に
供給するように構成したインバータの制御回路に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter control circuit, and more particularly, to an inverter control circuit configured to supply its output to a system.
【０００２】[0002]
【従来の技術】直流電力を交流電力に変換して系統に供
給するように構成したインバータには、系統に流入する
出力電流の変化によってその波形歪を生じないようにす
る制御回路が設けられている。2. Description of the Related Art An inverter configured to convert DC power into AC power and supply the AC power to a system is provided with a control circuit for preventing waveform distortion due to a change in an output current flowing into the system. I have.
【０００３】上記したインバータは、図２に示したよう
に、直流電源１と、４個のスイッチング素子がブリッジ
接続され、前記直流電源１からの直流電力を交流電力に
変換する主変換部２と、この交流電力による交流電流を
正弦波にする交流フィルター３とからなり、前記交流電
力が供給されるように系統１０が接続されてなる。[0003] As shown in FIG. 2, the above-mentioned inverter has a DC power supply 1 and a main converter 2 having four switching elements connected in a bridge and converting DC power from the DC power supply 1 into AC power. And an AC filter 3 for converting an AC current by the AC power into a sine wave, and a system 10 is connected so that the AC power is supplied.
【０００４】また、上記したインバータの制御回路は、
前記インバータに、その出力電流を検出してインバータ
出力電流対応値を出力するインバータ出力電流検出器４
と、その出力電圧を検出してインバータ出力電圧対応値
を出力するインバータ出力電圧検出器５とを設け、前記
インバータ出力電圧対応値を入力してそれに対応した基
準信号を作成するＰＬＬ回路１１と、この基準信号と前
記インバータ出力電流対応値とを入力し、インバータ出
力電流対応値を基準信号に一致させるような制御信号を
作成する差動増幅器１２と、この制御信号を入力して前
記主変換部２のスイッチング素子を制御するＰＷＭ制御
信号を作成するＰＷＭ制御回路１３とから構成されてな
る。[0004] The above-described inverter control circuit includes:
An inverter output current detector for detecting an output current of the inverter and outputting a value corresponding to the inverter output current;
An inverter output voltage detector 5 that detects the output voltage and outputs an inverter output voltage corresponding value, and a PLL circuit 11 that inputs the inverter output voltage corresponding value and creates a reference signal corresponding thereto. A differential amplifier for inputting the reference signal and the inverter output current corresponding value and generating a control signal for matching the inverter output current corresponding value to the reference signal; And a PWM control circuit 13 for generating a PWM control signal for controlling the two switching elements.
【０００５】なお、前記ＰＷＭ制御信号は図示していな
い駆動回路によって前記スイッチング素子を駆動するた
めの駆動信号に変換され、この駆動信号が各スイッチン
グ素子の駆動入力端子に入力されるように構成されてな
る。The PWM control signal is converted into a drive signal for driving the switching element by a drive circuit (not shown), and the drive signal is input to a drive input terminal of each switching element. It becomes.
【０００６】そして、上記したインバータの制御回路で
は、差動増幅器１２の一方の入力端子に基準信号が入力
されるまでの時間と差動増幅器１２の他方の入力端子に
インバータ出力電流対応値が入力されるまでの時間との
差に起因して、作成される制御信号が不安定になること
があるため、前記差動増幅器１２の出力端子と一方の入
力端子との間に抵抗ＲとコンデンサＣとを並列に接続し
た積分回路を挿入し、前述した時間の差によって制御信
号が不安定にならないようにしている。In the above-described inverter control circuit, the time until the reference signal is input to one input terminal of the differential amplifier 12 and the value corresponding to the inverter output current are input to the other input terminal of the differential amplifier 12. Since the generated control signal may become unstable due to the difference between the time and the time required to perform the operation, a resistor R and a capacitor C may be connected between the output terminal of the differential amplifier 12 and one input terminal. Are connected in parallel to prevent the control signal from becoming unstable due to the time difference described above.
【０００７】[0007]
【発明が解決しようとする課題】上記した従来のインバ
ータの制御回路では、差動増幅器１２の積分回路のコン
デンサＣの充放電時間を利用して基準信号を遅延させて
制御信号の安定化を図っているが、基準信号の振幅の大
小によってコンデンサＣの充放電時間が変化するため、
基準信号の振幅が小の場合、すなわちインバータの出力
電流が小さい場合には、前記充放電時間が長くなって適
切な制御信号を作成することができず、図３および図４
の破線に示したように、インバータの力率と効率が低下
するという問題があった。In the conventional inverter control circuit described above, the reference signal is delayed by utilizing the charging and discharging time of the capacitor C of the integrating circuit of the differential amplifier 12 to stabilize the control signal. However, since the charge and discharge time of the capacitor C changes depending on the amplitude of the reference signal,
When the amplitude of the reference signal is small, that is, when the output current of the inverter is small, the charging / discharging time becomes long, so that an appropriate control signal cannot be created.
As shown by the broken line, there is a problem that the power factor and efficiency of the inverter are reduced.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するた
め、本発明は、直流電源からの直流電力を交流電力に変
換して系統に供給するように構成したインバータに、そ
の出力電流を検出してインバータ出力電流対応値を出力
するインバータ出力電流検出器と、前記系統に流入する
系統電流を検出して系統電流対応値を出力する系統電流
検出器と、前記インバータの出力電圧を検出してインバ
ータ出力電圧対応値を出力するインバータ出力電圧検出
器とを設け、かつ前記インバータを構成するスイッチン
グ素子の制御回路に、前記系統電流対応値とインバータ
出力電圧対応値とを入力し、それぞれを一定の周期でサ
ンプリングして各々のゼロクロスポイントの時間差を算
出し、この時間差が前記サンプリング周期より大のとき
に該時間差に対応した補正信号を作成する位相補正回路
と、この補正信号と前記インバータ出力電圧対応値とを
入力し、インバータ出力電圧対応値に対する系統電流対
応値の位相差を有する基準信号を作成するＰＬＬ回路
と、この基準信号と前記インバータ出力電流対応値とを
入力し、インバータ出力電流対応値を基準信号に一致さ
せるような制御信号を作成する差動増幅器と、この制御
信号を入力して前記スイッチング素子を制御するＰＷＭ
制御信号を作成するＰＷＭ制御回路とを設けたことを特
徴とするものである。In order to solve the above problems, the present invention detects an output current of an inverter configured to convert DC power from a DC power supply into AC power and to supply the AC power to a system. An inverter output current detector for outputting a corresponding value of an inverter output current, a system current detector for detecting a system current flowing into the system and outputting a system current corresponding value, and an inverter for detecting an output voltage of the inverter. An inverter output voltage detector for outputting an output voltage corresponding value, and inputting the system current corresponding value and the inverter output voltage corresponding value to a control circuit of a switching element constituting the inverter, and each of them is provided at a predetermined period. To calculate the time difference between the zero cross points, and when this time difference is greater than the sampling period,
And a phase correction circuit for generating a correction signal corresponding to the time difference , the correction signal and the inverter output voltage corresponding value, and a system current pair corresponding to the inverter output voltage corresponding value.
A PLL circuit for generating a reference signal having a corresponding phase difference, and a difference for inputting the reference signal and the inverter output current corresponding value and generating a control signal for matching the inverter output current corresponding value to the reference signal. And a PWM for receiving the control signal and controlling the switching element
And a PWM control circuit for generating a control signal.
【０００９】[0009]
【作用】本発明によれば、位相補正回路で系統電流対応
値とインバータ出力電圧対応値とをそれぞれ一定の周期
でサンプリングし、各々のゼロクロスポイントの時間差
が前記サンプリング周期より大のときに該時間差に対応
した補正信号を作成し、ＰＬＬ回路でインバータ出力電
圧対応値に対する系統電流対応値の位相差を有する基準
信号を作成しているので、基準信号の振幅が変化しても
基準信号は前記ゼロクロスポイントの時間差に対応して
調整されることになり、差動増幅器で適切な制御信号を
作成することができる。According to the present invention, the phase correction circuit samples the system current corresponding value and the inverter output voltage corresponding value at a constant period, and calculates the time difference between the respective zero cross points.
Is larger than the sampling period, a correction signal corresponding to the time difference is created, and the inverter output voltage is generated by the PLL circuit.
Since the reference signal having the phase difference of the system current corresponding value with respect to the pressure corresponding value is created, even if the amplitude of the reference signal changes, the reference signal is adjusted in accordance with the time difference of the zero cross point, An appropriate control signal can be generated by the differential amplifier.
【００１０】[0010]
【実施例】以下、実施例により説明する。Embodiments will be described below with reference to embodiments.
【００１１】図１は本発明のインバータの制御回路のブ
ロック図で、図２と同じ機能を有する部分には同じ符号
を付して以下の説明を省略する。FIG. 1 is a block diagram of a control circuit for an inverter according to the present invention. Parts having the same functions as in FIG. 2 are denoted by the same reference numerals, and the following description is omitted.
【００１２】本発明の特徴は、インバータから系統１０
に流入する系統電流を検出して系統電流対応値を出力す
る系統電流検出器６を設け、かつインバータの制御回路
に前記系統電流対応値とインバータ出力電圧検出器５か
らのインバータ出力電圧対応値とを入力し、それぞれを
一定の周期でサンプリングして各々のゼロクロスポイン
トの時間差を算出し、この時間差に対応した補正信号を
作成する位相補正回路１４を設けたものである。A feature of the present invention is that an inverter 10
A system current detector 6 for detecting a system current flowing into the inverter and outputting a system current corresponding value, and providing the system current corresponding value and an inverter output voltage corresponding value from the inverter output voltage detector 5 to an inverter control circuit. And a phase correction circuit 14 that samples each of them at a fixed cycle, calculates a time difference between the zero cross points, and creates a correction signal corresponding to the time difference.
【００１３】前記位相補正回路１４は、系統電流対応値
とインバータ出力電圧対応値とを入力し、それぞれを一
定の周期でサンプリングしているので、各々のゼロクロ
スポイントの時間差がサンプリングの周期より大になれ
ばこの時間差に対応した補正信号を作成することができ
る。The phase correction circuit 14 receives a system current corresponding value and an inverter output voltage corresponding value and samples each at a fixed cycle, so that the time difference between the zero cross points is larger than the sampling cycle. If possible, a correction signal corresponding to this time difference can be created.
【００１４】なお、前記サンプリングの周期は、インバ
ータの出力と系統との間の許容可能な位相差と負荷変動
に対するインバータの力率と効率の許容変動範囲とに基
づいて決定されるもので、インバータの出力の周期の３
２分の１以上とするのが好ましい。The sampling cycle is determined on the basis of an allowable phase difference between the output of the inverter and the system and an allowable variation range of the power factor and efficiency with respect to a load variation. Output cycle 3
It is preferable to set it to half or more.
【００１５】そして、前記補正信号を前記インバータ出
力電圧検出器５からのインバータ出力電圧対応値ととも
にＰＬＬ回路１１に入力し、このＰＬＬ回路１１によっ
て前記補正信号に対応した位相差を有する基準信号を作
成しているので、この基準信号はインバータ出力電圧対
応値に対する系統電流対応値の位相差に対応したものに
なる。The correction signal is input to a PLL circuit 11 together with a value corresponding to the inverter output voltage from the inverter output voltage detector 5, and a reference signal having a phase difference corresponding to the correction signal is generated by the PLL circuit 11. Therefore, the reference signal corresponds to the phase difference between the system current corresponding value and the inverter output voltage corresponding value.
【００１６】そして、前記基準信号を前記インバータ出
力電流検出器４からのインバータ出力電流対応値ととも
に差動増幅器１２に入力し、この差動増幅器１２によっ
て前記インバータ出力電流対応値を前記基準信号に一致
させるような制御信号を作成しているので、この制御信
号はインバータ出力電流対応値を系統電流対応値に一致
させるためのものとなる。Then, the reference signal is input to a differential amplifier 12 together with a value corresponding to the inverter output current from the inverter output current detector 4, and the differential amplifier 12 matches the value corresponding to the inverter output current with the reference signal. Since the control signal is generated such that the inverter output current corresponding value matches the system current corresponding value.
【００１７】従って、前記制御信号をＰＷＭ制御回路１
３に入力して主変換部２のスイッチング素子を制御する
ＰＷＭ制御信号を作成し、図示していない駆動回路によ
って前記スイッチング素子を駆動するための駆動信号に
変換し、この駆動信号によって前記スイッチング素子を
駆動すると、インバータの出力電流の位相を系統電流の
位相に一致させるように動作させることができ、インバ
ータの出力電流が小さくなって差動増幅器１２の積分回
路のコンデンサＣの充放電時間が長くなり、それによっ
てインバータの出力電流の位相と系統電流の位相との間
に差を生じても、その差を小さくするような制御信号を
作成することができる。Therefore, the control signal is transmitted to the PWM control circuit 1
3, a PWM control signal for controlling the switching element of the main converter 2 is generated, and converted into a drive signal for driving the switching element by a drive circuit (not shown). Is driven, the phase of the output current of the inverter can be made to match the phase of the system current, the output current of the inverter decreases, and the charging and discharging time of the capacitor C of the integrating circuit of the differential amplifier 12 increases. Therefore, even if a difference occurs between the phase of the output current of the inverter and the phase of the system current, a control signal that reduces the difference can be created.
【００１８】上記した本発明のインバータの制御回路を
用いてインバータを運転して負荷変動させ、その力率お
よび効率を測定したところ、図３および図４の実線に示
したようになった。Using the inverter control circuit of the present invention, the inverter was operated to change the load, and its power factor and efficiency were measured. The results were as shown by the solid lines in FIGS. 3 and 4.
【００１９】図３および図４から、本発明のインバータ
の制御回路は負荷変動させても力率および効率の低下が
ないことがわかる。FIGS. 3 and 4 show that the inverter control circuit of the present invention does not decrease in power factor and efficiency even when the load is changed.
【００２０】[0020]
【発明の効果】上記した如く、本発明のインバータの制
御回路は、差動増幅器の積分回路によってインバータの
出力電流の位相と系統電流の位相との間に差を生じて
も、その差によって力率および効率の低下は生じないの
で、インバータ出力を系統に供給するように構成したイ
ンバータの制御回路に適している。As described above, in the inverter control circuit according to the present invention, even if a difference occurs between the phase of the output current of the inverter and the phase of the system current due to the integration circuit of the differential amplifier, the difference causes a difference in power. Since the rate and efficiency do not decrease, it is suitable for an inverter control circuit configured to supply the inverter output to the system.
【図１】本発明のインバータの制御回路のブロック図で
ある。FIG. 1 is a block diagram of a control circuit of an inverter according to the present invention.
【図２】従来のインバータの制御回路のブロック図であ
る。FIG. 2 is a block diagram of a conventional inverter control circuit.
【図３】負荷変動に対する本発明の制御回路の力率と従
来の制御回路の力率とを比較した図である。FIG. 3 is a diagram comparing a power factor of a control circuit of the present invention with respect to a load change and a power factor of a conventional control circuit.
【図４】負荷変動に対する本発明の制御回路の効率と従
来の制御回路の効率とを比較した図である。FIG. 4 is a diagram comparing the efficiency of the control circuit of the present invention with respect to load fluctuation and the efficiency of a conventional control circuit.
１ 直流電源 ２ 主変換部 ３ 交流フィルター ４ インバータ出力電流検出器 ５ インバータ出力電圧検出器 ６ 系統電流検出器 １０ 系統 １１ ＰＬＬ回路 １２ 差動増幅器 １３ ＰＷＭ制御回路 １４ 位相補正回路 DESCRIPTION OF SYMBOLS 1 DC power supply 2 Main conversion part 3 AC filter 4 Inverter output current detector 5 Inverter output voltage detector 6 System current detector 10 System 11 PLL circuit 12 Differential amplifier 13 PWM control circuit 14 Phase correction circuit
Claims (1)
換して系統に供給するように構成したインバータに、そ
の出力電流を検出してインバータ出力電流対応値を出力
するインバータ出力電流検出器と、前記系統に流入する
系統電流を検出して系統電流対応値を出力する系統電流
検出器と、前記インバータの出力電圧を検出してインバ
ータ出力電圧対応値を出力するインバータ出力電圧検出
器とを設け、かつ前記インバータを構成するスイッチン
グ素子の制御回路に、前記系統電流対応値とインバータ
出力電圧対応値とを入力し、それぞれを一定の周期でサ
ンプリングして各々のゼロクロスポイントの時間差を算
出し、この時間差が前記サンプリング周期より大のとき
に該時間差に対応した補正信号を作成する位相補正回路
と、この補正信号と前記インバータ出力電圧対応値とを
入力し、インバータ出力電圧対応値に対する系統電流対
応値の位相差を有する基準信号を作成するＰＬＬ回路
と、この基準信号と前記インバータ出力電流対応値とを
入力し、インバータ出力電流対応値を基準信号に一致さ
せるような制御信号を作成する差動増幅器と、この制御
信号を入力して前記スイッチング素子を制御するＰＷＭ
制御信号を作成するＰＷＭ制御回路とを設けたことを特
徴とするインバータの制御回路。An inverter configured to convert a DC power from a DC power supply into an AC power and to supply the AC power to a system, to detect an output current of the inverter and to output an inverter output current corresponding value; A system current detector that detects a system current flowing into the system and outputs a system current corresponding value, and an inverter output voltage detector that detects an output voltage of the inverter and outputs an inverter output voltage corresponding value. The system current corresponding value and the inverter output voltage corresponding value are input to a control circuit of a switching element constituting the inverter, and each is sampled at a constant cycle to calculate a time difference between respective zero cross points. When the time difference is larger than the sampling period
And a phase correction circuit for generating a correction signal corresponding to the time difference , the correction signal and the inverter output voltage corresponding value, and a system current pair corresponding to the inverter output voltage corresponding value.
A PLL circuit for generating a reference signal having a corresponding phase difference, and a difference for inputting the reference signal and the inverter output current corresponding value and generating a control signal for matching the inverter output current corresponding value to the reference signal. And a PWM for receiving the control signal and controlling the switching element
And a PWM control circuit for generating a control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07019395A JP3097070B2 (en) | 1995-02-07 | 1995-02-07 | Inverter control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07019395A JP3097070B2 (en) | 1995-02-07 | 1995-02-07 | Inverter control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08223941A JPH08223941A (en) | 1996-08-30 |
| JP3097070B2 true JP3097070B2 (en) | 2000-10-10 |
Family
ID=11998096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07019395A Expired - Lifetime JP3097070B2 (en) | 1995-02-07 | 1995-02-07 | Inverter control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3097070B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG138451A1 (en) * | 2004-05-03 | 2008-01-28 | Singapore Polytechnic | Micro-controller operated pre-regulator for active power factor correction |
-
1995
- 1995-02-07 JP JP07019395A patent/JP3097070B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08223941A (en) | 1996-08-30 |
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