JP3095918B2 - Non-volatile semiconductor memory - Google Patents
Non-volatile semiconductor memoryInfo
- Publication number
- JP3095918B2 JP3095918B2 JP04351216A JP35121692A JP3095918B2 JP 3095918 B2 JP3095918 B2 JP 3095918B2 JP 04351216 A JP04351216 A JP 04351216A JP 35121692 A JP35121692 A JP 35121692A JP 3095918 B2 JP3095918 B2 JP 3095918B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- gate electrode
- memory cell
- data
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電気的書換え可能な不
揮発性半導体メモリに関し、特に各メモリセルに３値以
上のデータを選択的に書き込むことが可能な不揮発性半
導体メモリに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory capable of selectively writing three or more values of data to each memory cell.
【０００２】[0002]
【従来の技術】電気的にデータの書込み及び消去が可能
なＥＥＰＲＯＭと呼ばれる不揮発性メモリが知られてい
る。特に、ＦｌａｓｈＥＥＰＲＯＭと呼ばれるデータを
一括消去可能なＥＥＰＲＯＭがある。このＦｌａｓｈＥ
ＥＰＲＯＭの各メモリセルに、基板の互いに対峙するソ
ース電極とドレイン電極との間にチャネル領域を設け、
このチャネル領域上にトンネル絶縁膜と、浮遊ゲート電
極と、層間絶縁膜を介して制御ゲート電極とがこの順番
に設けられたＭＯＳトランジスタを用いたものがある。2. Description of the Related Art A nonvolatile memory called an EEPROM capable of electrically writing and erasing data is known. In particular, there is an EEPROM called Flash EEPROM which can erase data at once. This FlashE
In each memory cell of the EPROM, a channel region is provided between a source electrode and a drain electrode facing each other on the substrate,
There is a device using a MOS transistor in which a tunnel insulating film, a floating gate electrode, and a control gate electrode are provided in this order via an interlayer insulating film on the channel region.
【０００３】このようなメモリセルへデータを書込むに
は、トンネル絶縁膜を介して浮遊ゲートに電荷を注入
し、セルの閾値電圧を高く設定する（例えばデータ
「１」）か、逆に浮遊ゲート電極から電荷を引抜くこと
により、セルの閾値電圧を低く設定する（データ
「０」）。そして、この記憶されたデータを読出すに
は、上記した高い閾値電圧よりも低く、かつ低い閾値電
圧よりも高い電圧を制御ゲート電極に印加し、センスす
れば良い。In order to write data into such a memory cell, charge is injected into the floating gate through a tunnel insulating film to set the threshold voltage of the cell high (for example, data "1"), or vice versa. The threshold voltage of the cell is set low by extracting charges from the gate electrode (data "0"). Then, in order to read out the stored data, a voltage lower than the high threshold voltage and higher than the low threshold voltage may be applied to the control gate electrode for sensing.
【０００４】上記したように従来のＥＥＰＲＯＭにあっ
ては、１つのメモリセルに対してデータ「０」またはデ
ータ「１」のみを選択的に記憶できるのみであることか
ら、その記憶容量が少なく、近年のデータの増大傾向に
対応して、少ないメモリセルで多くの記憶容量を有する
ＥＥＰＲＯＭの開発が望まれていた。As described above, in the conventional EEPROM, since only data "0" or data "1" can be selectively stored in one memory cell, the storage capacity is small. In response to the increasing trend of data in recent years, development of an EEPROM having a large storage capacity with a small number of memory cells has been desired.
【０００５】[0005]
【発明が解決しようとする課題】本発明は上記したよう
な従来技術の問題点に鑑みなされたものであり、その主
な目的は、取扱いが容易であり、かつ少ないメモリセル
をもって多いデータ量を記憶することが可能な不揮発性
半導体メモリを提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its main object to handle a large amount of data with a small number of memory cells. An object of the present invention is to provide a nonvolatile semiconductor memory capable of storing.
【０００６】[0006]
【課題を解決するための手段】上記した目的は本発明に
よれば、ドレイン電極と、ソース電極と、基板内の前記
各電極間に配置されたチャネル領域と、前記チャネル領
域上に設けられたトンネル絶縁膜と、前記トンネル絶縁
膜上に設けられた浮遊ゲート電極と、前記浮遊ゲート電
極上に層間絶縁膜を介して設けられた制御ゲート電極と
を有するＭＯＳトランジスタをメモリセルとして用い
て、多値デジタルデータを書き込むことが可能な不揮発
性半導体メモリであって、前記ＭＯＳトランジスタの前
記制御ゲート電極に高電圧を印加し、かつ前記ソース電
極をフローティングした状態で、前記ドレイン電極に前
記多値デジタルデータに応じて３種類以上の電圧印加を
行うことにより前記メモリセルの閾値電圧を予め設定さ
れた３つ以上のレベルに選択的に設定する手段を有する
ことを特徴とする不揮発性半導体メモリを提供すること
により達成される。According to the present invention, there is provided a drain electrode, a source electrode, a channel region disposed between the electrodes in a substrate, and a channel region provided on the channel region. a tunnel insulating film, a floating gate electrode provided on the tunnel insulating film, a MOS transistor and a control gate electrode provided via an interlayer insulating film on the floating gate electrode is used as a memory cell, multi A non-volatile semiconductor memory capable of writing value digital data , wherein a high voltage is applied to the control gate electrode of the MOS transistor, and
While floating the electrode, prior to said drain electrode
Apply three or more types of voltage according to multi-valued digital data
By doing so, the threshold voltage of the memory cell is set in advance.
The present invention is achieved by providing a nonvolatile semiconductor memory having means for selectively setting three or more levels .
【０００７】[0007]
【作用】このように、メモリセルの閾値電圧を入力デー
タに対応するレベルのいずれかになるように、ドレイン
電極に印加することにより、チャネル領域から浮遊ゲー
トに注入される電荷量を変化させる。その結果、データ
読出し時に制御ゲートに各閾値電圧よりもやや低い電圧
を順番に印加することにより、各メモリセルに記憶され
たデータを読み出すことができる。As described above, by applying the threshold voltage of the memory cell to one of the levels corresponding to the input data to the drain electrode, the amount of charge injected from the channel region to the floating gate is changed. As a result, the data stored in each memory cell can be read by sequentially applying a voltage slightly lower than each threshold voltage to the control gate at the time of data reading.
【０００８】[0008]
【実施例】以下、本発明の好適実施例を添付の図面につ
いて詳しく説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a preferred embodiment of the present invention.
【０００９】図１は、本発明が適用されたＦｌａｓｈＥ
ＥＰＲＯＭの要部を拡大して示す回路図である。ワード
線Ｗ1には、ＭＯＳトランジスタからなるメモリセルＭ
1、Ｍ2の制御ゲート電極に接続されており、ワード線Ｗ
2には同じくＭＯＳトランジスタからなるメモリセルＭ
3、Ｍ4の制御ゲート電極が接続されている。また、メモ
リセルＭ1、Ｍ3のドレイン電極はビット線Ｂ1に接続さ
れ、メモリセルＭ2、Ｍ4のドレイン電極はビット線Ｂ2
に接続されている。更に、メモリセルＭ1、Ｍ3のソース
電極は、ソース線Ｓ1に接続され、メモリセルＭ2、Ｍ4
のソース電極はソース線Ｓ2に接続されている。FIG. 1 shows a FlashE to which the present invention is applied.
FIG. 2 is an enlarged circuit diagram showing a main part of the EPROM. A word line W1 has a memory cell M composed of a MOS transistor.
1, connected to the control gate electrode of M2 and the word line W
2 is a memory cell M also composed of MOS transistors.
3. The control gate electrode of M4 is connected. The drain electrodes of the memory cells M1 and M3 are connected to the bit line B1, and the drain electrodes of the memory cells M2 and M4 are connected to the bit line B2.
It is connected to the. Further, the source electrodes of the memory cells M1, M3 are connected to the source line S1, and the memory cells M2, M4
Are connected to the source line S2.
【００１０】ここで、各メモリセルＭ1〜Ｍ4のＭＯＳト
ランジスタの構造を簡単に説明すると、図２に示すよう
に、基板１の内部にドレイン領域２と、ソース領域３と
が互いに離隔する位置に設けられ、その間にチャネル領
域４が設けられている。ドレイン領域２の表面には、ド
レイン電極５が設けられ、ソース領域３の表面にはソー
ス電極６が設けられている。チャネル領域４の表面には
二酸化珪素からなるトンネル絶縁膜８と、浮遊ゲート電
極９と、層間絶縁膜１０と、制御ゲート電極１１とがこ
の順番に積層されている。Here, the structure of the MOS transistor of each of the memory cells M1 to M4 will be briefly described. As shown in FIG. 2, a drain region 2 and a source region 3 are located inside a substrate 1 at positions separated from each other. And a channel region 4 is provided therebetween. A drain electrode 5 is provided on the surface of the drain region 2, and a source electrode 6 is provided on the surface of the source region 3. On the surface of the channel region 4, a tunnel insulating film 8 made of silicon dioxide, a floating gate electrode 9, an interlayer insulating film 10, and a control gate electrode 11 are laminated in this order.
【００１１】このようなＦｌａｓｈＥＥＰＲＯＭの各メ
モリセルＭ1〜Ｍ4にデータを書き込む手順を以下に説明
する。ここで、各メモリセルＭ1〜Ｍ4には２進法表示に
よるデータ「００」〜「１１」までの４種類のデータを
書込み／読出しすることが可能なように、これら４種類
のデータに対応して、閾値電圧のレベルを２Ｖ、３Ｖ、
４Ｖ、５Ｖの４つの状態を取り得るようになっている。A procedure for writing data in each of the memory cells M1 to M4 of the flash EEPROM will be described below. Here, each of the memory cells M1 to M4 corresponds to these four types of data so that four types of data "00" to "11" in binary notation can be written / read. The threshold voltage levels are 2V, 3V,
It can take four states of 4V and 5V.
【００１２】例えば、メモリセルＭ1にデータ「１１」
を書き込む場合、ワード線Ｗ1に１２〜１５Ｖ程度の高
電圧を印加し、それ以外のワード線に電圧を印加しない
ようにする。そして、ビット線Ｂ1を接地し、その他の
ビット線を３Ｖとする。このとき、ソース線Ｓ1、Ｓ2を
開放してフローティング状態とする。これにより、メモ
リセルＭ1の制御ゲート電極には１２〜１５Ｖの電圧が
印加され、かつドレイン電極の電圧は０ボルトとなる。
そして、ソース電極はフローティング状態となる。ま
た、制御ゲート電極とドレイン電極との電位差に対応し
た量の電荷が浮遊ゲートに注入され、メモリセルＭ1の
閾値電圧が５Ｖに設定される。For example, the data "11" is stored in the memory cell M1.
Is written, a high voltage of about 12 to 15 V is applied to the word line W1, and no voltage is applied to the other word lines. Then, the bit line B1 is grounded, and the other bit lines are set to 3V. At this time, the source lines S1 and S2 are opened to be in a floating state. As a result, a voltage of 12 to 15 V is applied to the control gate electrode of the memory cell M1, and the voltage of the drain electrode becomes 0 volt.
Then, the source electrode is in a floating state. Also, an amount of charge corresponding to the potential difference between the control gate electrode and the drain electrode is injected into the floating gate, and the threshold voltage of the memory cell M1 is set to 5V.
【００１３】次に、同じくメモリセルＭ1にデータ「１
０」を書き込む場合、ワード線Ｗ1及びソース線Ｓ1は上
記と同様な状態とし、ビット線Ｂ1、即ちドレインに電
位１Ｖのパルス電圧を印加する。これによりメモリセル
Ｍ1の閾値電圧は４Ｖに設定される。同様にして、ドレ
イン電圧を２Ｖとすることにより閾値電圧が３Ｖに設定
され（データ「０１」）、ドレイン電圧を３Ｖとするこ
とにより閾値電圧が２Ｖに設定される（データ「０
０」）。これら本実施例に於けるドレイン電圧とメモリ
セルの閾値電圧との関係を図３に示す。この図により分
かるように、本実施例ではドレイン電圧の電圧レベルに
応じてメモリセルの閾値電圧を２Ｖ、３Ｖ、４Ｖ、５Ｖ
の４つの状態に設定でき、各閾値電圧にデータを対応さ
せることにより、データ「００」〜「１１」の４通りの
データを記憶させることができる。同様にして各メモリ
セルＭ2〜Ｍ4にも４通りのデータを記憶させることがで
きる。Next, the data "1" is similarly stored in the memory cell M1.
When writing "0", the word line W1 and the source line S1 are in the same state as described above, and a pulse voltage of 1 V is applied to the bit line B1, that is, the drain. As a result, the threshold voltage of the memory cell M1 is set to 4V. Similarly, the threshold voltage is set to 3 V by setting the drain voltage to 2 V (data “01”), and the threshold voltage is set to 2 V by setting the drain voltage to 3 V (data “0”).
0 "). FIG. 3 shows the relationship between the drain voltage and the threshold voltage of the memory cell in the present embodiment. As can be seen from this figure, in this embodiment, the threshold voltage of the memory cell is set to 2V, 3V, 4V, 5V in accordance with the voltage level of the drain voltage.
The four states of “00” to “11” can be stored by associating data with each threshold voltage. Similarly, four types of data can be stored in each of the memory cells M2 to M4.
【００１４】上記したように書き込まれたデータを読み
込む際には、例えばワード線Ｗ1に５Ｖを印加して、予
め各レベルに閾値電圧を設定したリファレンスセルとそ
のドレイン電流を比較することによって、各メモリセル
Ｍ1〜Ｍ2がデータ「００」〜「１１」のいずれを記憶し
ているかをセンスすれば良い。When the data written as described above is read, for example, 5 V is applied to the word line W1 and the drain current of each reference cell whose threshold voltage is set in advance is compared with that of the reference cell. It suffices to sense which of the data "00" to "11" is stored in the memory cells M1 to M2.
【００１５】尚、上記実施例に於ては、各メモリセルの
閾値電圧を２Ｖから５Ｖまでの間で４通り設定したが、
更に細分化すれば、より多くのデータを記憶できるよう
になることは云うまでもない。また、上記実施例に於て
はドレイン電圧、即ちパルス高さを変化させることによ
り各メモリセルの閾値電圧を変化させたが、電圧の総印
加時間、即ちパルス幅を変化させることにより、各メモ
リセルの閾値電圧を変化させることも容易に可能である
ことは云うまでもない。更に、本実施例に於けるゲート
電圧、ドレイン電圧と各メモリセルの閾値電圧との関係
は、メモリセルの構造、トンネル絶縁膜の厚さ、層間絶
縁膜の厚さ等により任意に変更されるものである。In the above embodiment, the threshold voltage of each memory cell is set to four values between 2 V and 5 V.
Needless to say, if the data is further subdivided, more data can be stored. In the above embodiment, the threshold voltage of each memory cell was changed by changing the drain voltage, that is, the pulse height. However, by changing the total voltage application time, that is, the pulse width, each memory cell was changed. It goes without saying that the threshold voltage of the cell can be easily changed. Further, the relationship between the gate voltage and the drain voltage and the threshold voltage of each memory cell in the present embodiment is arbitrarily changed depending on the structure of the memory cell, the thickness of the tunnel insulating film, the thickness of the interlayer insulating film, and the like. Things.
【００１６】図４は、本発明が適用された第２の実施例
を示すＥＥＰＲＯＭの説明回路図である。本実施例に於
ては、ｎ本のソース線Ｓ1〜Ｓｎのに各々にカットオフ
用のＭＯＳトランジスタＱ1〜Ｑｎが設けられている。
そして、データを書き込まんとするメモリセルＭ11〜Ｍ
ｍｎのソース電極に接続されたソース線のＭＯＳトラン
ジスタを制御線Ｄ1〜Ｄnによりカットオフすることによ
り各メモリセルのソース電極をフローティング状態とす
るようになっている。それ以外の構造は第１の実施例と
同様である。FIG. 4 is an explanatory circuit diagram of an EEPROM showing a second embodiment to which the present invention is applied. In this embodiment, cut-off MOS transistors Q1 to Qn are provided for each of the n source lines S1 to Sn.
The memory cells M11 to M to which data is to be written
By cutting off the MOS transistor of the source line connected to the mn source electrode by the control lines D1 to Dn, the source electrode of each memory cell is brought into a floating state. Other structures are the same as those of the first embodiment.
【００１７】[0017]
【発明の効果】以上の説明により明らかなように、本発
明による不揮発性半導体メモリによれば、制御ゲート電
極に高電圧を印加し、入力された多値デジタルデータに
応じた３種類以上の電圧印加を行うことにより容易に各
メモリセルの閾値電圧を３つ以上のレベルに選択的に設
定することで、１セルに１ビットを越えるデジタルデー
タを容易に記憶可能となる。従って、従来と同様な量の
メモリセルをもって半導体メモリの記憶容量が著しく向
上することからその効果は大である。また、書込みにフ
ァーラーノードハイムトンネリング法を用いることによ
り、ホットエレクトロン法を用いた場合に比較して、浮
遊ゲートに注入される電荷量を容易に制御することが可
能となる。As is apparent from the above description, according to the nonvolatile semiconductor memory of the present invention, a high voltage is applied to the control gate electrode, and three or more types of voltages corresponding to the input multi-valued digital data are obtained. By applying the voltage, the threshold voltage of each memory cell can be easily selectively set to three or more levels.
Thus, digital data exceeding one bit can be easily stored in one cell . Therefore, the storage capacity of the semiconductor memory is remarkably improved with the same number of memory cells as the conventional one, so that the effect is great. Further, by using the Farrer-Nordheim tunneling method for writing, the amount of charge injected into the floating gate can be easily controlled as compared with the case of using the hot electron method.
【図１】本発明が適用された第１の実施例を示すＥＥＰ
ＲＯＭの要部構成回路図である。FIG. 1 shows an EEP showing a first embodiment to which the present invention is applied.
FIG. 2 is a circuit diagram of a main part configuration of a ROM.
【図２】図１のメモリセルを構成するＭＯＳトランジス
タの構造を示す模式的断面図である。FIG. 2 is a schematic sectional view showing a structure of a MOS transistor forming the memory cell of FIG. 1;
【図３】図１の各メモリセルにデータを書き込む際のド
レイン電極に印加する電圧と各メモリセルの閾値電圧と
の関係を示すグラフである。3 is a graph showing a relationship between a voltage applied to a drain electrode when writing data to each memory cell in FIG. 1 and a threshold voltage of each memory cell;
【図４】本発明が適用された第２の実施例を示す図１と
同様な要部構成回路図である。FIG. 4 is a main part configuration circuit diagram similar to FIG. 1, showing a second embodiment to which the present invention is applied.
１ 基板 ２ ドレイン領域 ３ ソース領域 ４ チャネル領域 ５ ドレイン電極 ６ ソース電極 ８ トンネル絶縁膜 ９ 浮遊ゲート電極 １０ 層間絶縁膜 １１ 制御ゲート電極 Ｗ1〜Ｗn ワード線 Ｂ1〜Ｂn ビット線 Ｓ1〜Ｓn ソース線 Ｍ1〜Ｍ4 メモリセル Ｑ1〜Ｑn カットオフ用ＭＯＳトランジスタ Ｍ11〜Ｍmn メモリセル Ｄ1〜Ｄn 制御線 DESCRIPTION OF SYMBOLS 1 Substrate 2 Drain region 3 Source region 4 Channel region 5 Drain electrode 6 Source electrode 8 Tunnel insulating film 9 Floating gate electrode 10 Interlayer insulating film 11 Control gate electrode W1-Wn Word line B1-Bn Bit line S1-Sn Source line M1- M4 memory cell Q1-Qn cut-off MOS transistor M11-Mmn memory cell D1-Dn control line
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岩佐 昇一 相模原市淵野辺５−10−１ 新日本製鐵 株式会社 エレクトロニクス研究所内 (72)発明者 佐藤 康夫 相模原市淵野辺５−10−１ 新日本製鐵 株式会社 エレクトロニクス研究所内 (56)参考文献 特開 平３−88199（ＪＰ，Ａ) 特開 昭58−86777（ＪＰ，Ａ) 特開 昭47−12256（ＪＰ，Ａ) 特開 平４−25182（ＪＰ，Ａ) 特開 昭63−119097（ＪＰ，Ａ) 特開 昭59−3975（ＪＰ，Ａ) 特開 平５−275659（ＪＰ，Ａ) 特開 平２−264381（ＪＰ，Ａ) 特開 平２−194562（ＪＰ，Ａ) 特開 平２−96369（ＪＰ，Ａ) 特開 平２−40198（ＪＰ，Ａ) 特開 昭63−283072（ＪＰ，Ａ) 特開 昭63−276791（ＪＰ，Ａ) 特開 昭58−86778（ＪＰ，Ａ) 特開 昭58−85565（ＪＰ，Ａ) 特開 昭62−298999（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shoichi Iwasa 5-10-1 Fuchinobe, Sagamihara-shi Nippon Steel Corporation Electronics Research Laboratory (72) Inventor Yasuo Sato 5-10-1 Fuchinobe, Sagamihara-shi Nippon Steel Corporation (56) References JP-A-3-88199 (JP, A) JP-A-58-86777 (JP, A) JP-A-47-12256 (JP, A) JP-A-4-25182 ( JP, A) JP-A-63-119097 (JP, A) JP-A-59-3975 (JP, A) JP-A-5-275659 (JP, A) JP-A-2-264381 (JP, A) JP-A JP-A-2-194562 (JP, A) JP-A-2-96369 (JP, A) JP-A-2-40198 (JP, A) JP-A-63-283072 (JP, A) JP-A-63-276791 (JP , A) JP-A-58-86778 (JP, A) Open Akira 58-85565 (JP, A) JP Akira 62-298999 (JP, A) (58 ) investigated the field (Int.Cl. 7, DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792
Claims (3)
内の前記各電極間に配置されたチャネル領域と、前記チ
ャネル領域上に設けられたトンネル絶縁膜と、前記トン
ネル絶縁膜上に設けられた浮遊ゲート電極と、前記浮遊
ゲート電極上に層間絶縁膜を介して設けられた制御ゲー
ト電極とを有するＭＯＳトランジスタをメモリセルとし
て用いて、多値デジタルデータを書き込むことが可能な
不揮発性半導体メモリであって、 前記ＭＯＳトランジスタの前記制御ゲート電極に高電圧
を印加した状態で、前記ドレイン電極に前記多値デジタ
ルデータに応じた３種類以上の電圧を選択的に印加して
前記メモリセルの閾値電圧を予め設定された３つ以上の
レベルに選択的に設定する手段を有することを特徴とす
る不揮発性半導体メモリ。1. A drain electrode, a source electrode, a channel region disposed between the electrodes in a substrate, a tunnel insulating film provided on the channel region, and provided on the tunnel insulating film. A nonvolatile semiconductor memory in which multi-level digital data can be written using a MOS transistor having a floating gate electrode and a control gate electrode provided on the floating gate electrode via an interlayer insulating film as a memory cell. The multi-level digital signal is applied to the drain electrode in a state where a high voltage is applied to the control gate electrode of the MOS transistor.
According to Le data 3 or more types of voltages selectively applied to <br/> preset three or more threshold voltages of the memory cells
A nonvolatile semiconductor memory having means for selectively setting a level .
トランジスタの前記制御ゲート電極に高電圧を印加し、
かつ前記ソース電極をフローティングした状態で、前記
多値デジタルデータに応じて前記ドレイン電極に印加す
る電圧の印加時間または電圧レベルを変化させて前記メ
モリセルの閾値電圧を予め設定された３つ以上のレベル
に選択的に設定する手段からなることを特徴とする請求
項１に記載の不揮発性半導体メモリ。2. The semiconductor device according to claim 2, wherein said threshold voltage setting means includes :
Applying a high voltage to the control gate electrode of the transistor,
And while floating the source electrode, the
It comprises means for selectively setting the three or more levels of the threshold voltage set in advance in the memory cell application time or the voltage level is changed in voltage applied to the drain electrode in accordance with the multi-valued digital data The nonvolatile semiconductor memory according to claim 1, wherein:
ルス電圧からなり、前記閾値電圧設定手段が、前記ＭＯ
Ｓトランジスタの前記制御ゲート電極に高電圧を印加
し、かつ前記ソース電極をフローティングした状態で、
前記多値デジタルデータに応じて前記パルス電圧のパル
ス高さまたはパルス幅を変化させて前記メモリセルの閾
値電圧を予め設定された３つ以上のレベルに選択的に設
定する手段からなることを特徴とする請求項１に記載の
不揮発性半導体メモリ。3. The method according to claim 2, wherein the voltage applied to the drain electrode comprises a pulse voltage, and
High voltage is applied to the control gate electrode of the S transistor
And, with the source electrode floating,
Selectively set to three or more levels of the threshold voltage set in advance of the pulse voltage pulse height or the memory cell by changing the pulse width in response to the multi-valued digital data
2. The non-volatile semiconductor memory according to claim 1, further comprising means for setting.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04351216A JP3095918B2 (en) | 1992-12-07 | 1992-12-07 | Non-volatile semiconductor memory |
| US08/161,508 US5418743A (en) | 1992-12-07 | 1993-12-06 | Method of writing into non-volatile semiconductor memory |
| US08/387,562 US5596527A (en) | 1992-12-07 | 1995-02-13 | Electrically alterable n-bit per cell non-volatile memory with reference cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04351216A JP3095918B2 (en) | 1992-12-07 | 1992-12-07 | Non-volatile semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06177397A JPH06177397A (en) | 1994-06-24 |
| JP3095918B2 true JP3095918B2 (en) | 2000-10-10 |
Family
ID=18415839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04351216A Expired - Lifetime JP3095918B2 (en) | 1992-12-07 | 1992-12-07 | Non-volatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3095918B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3547245B2 (en) * | 1996-02-01 | 2004-07-28 | シャープ株式会社 | Multi-value writing method for nonvolatile memory |
| JP2000021185A (en) | 1998-06-30 | 2000-01-21 | Sharp Corp | Method for writing to nonvolatile semiconductor memory |
| JP4901827B2 (en) * | 2008-08-22 | 2012-03-21 | ペグレ・セミコンダクターズ・リミテッド・ライアビリティ・カンパニー | Semiconductor storage device, writing method thereof, and storage medium storing writing method |
-
1992
- 1992-12-07 JP JP04351216A patent/JP3095918B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06177397A (en) | 1994-06-24 |
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