JP3085180B2 - Field effect solar cell - Google Patents

Field effect solar cell

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Publication number
JP3085180B2
JP3085180B2 JP08007227A JP722796A JP3085180B2 JP 3085180 B2 JP3085180 B2 JP 3085180B2 JP 08007227 A JP08007227 A JP 08007227A JP 722796 A JP722796 A JP 722796A JP 3085180 B2 JP3085180 B2 JP 3085180B2
Authority
JP
Japan
Prior art keywords
electrode
solar cell
voltage application
substrate
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP08007227A
Other languages
Japanese (ja)
Other versions
JPH09199742A (en
Inventor
信一 村松
寛之 大塚
謙 筒井
光紀 蕨迫
寧 永田
雅彦 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP08007227A priority Critical patent/JP3085180B2/en
Publication of JPH09199742A publication Critical patent/JPH09199742A/en
Application granted granted Critical
Publication of JP3085180B2 publication Critical patent/JP3085180B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、太陽電池、特に単
結晶および多結晶シリコンを用いた電界効果型太陽電池
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly to a field effect solar cell using single crystal and polycrystalline silicon.

【０００２】[0002]

【従来の技術】結晶シリコン太陽電池の光電変換効率の
向上には、一般に半導体中の不純物や欠陥の低減ととも
に、結晶表面におけるキャリヤの再結合低減が重要であ
る。表面再結合の低減のためには熱酸化を行ない、酸化
膜でパッシベーションすることが行われてきた。しか
し、太陽電池作製後の半導体表面は、ミッドギャップ付
近の低密度領域でも１×１０10／ｅＶｃｍ2以上の界面
準位が存在する。このとき、太陽電池の特性は表面電位
にしたがって大きく変化することが知られている。例え
ば、第４回「高効率太陽電池」ワークショップ予稿集
（奈良、１９９４）の４９頁から５２頁に、大塚、上
松、蕨迫により報告されている。特に、表面にほとんど
電位が存在しない通常の動作状態で光電変換効率は大き
く低下し、正または負の電界を印加できれば光電変換効
率は大きく向上する。近年、この問題を解決するために
電界効果型太陽電池が提案されており、電圧印加によっ
て太陽電池特性の大幅な向上が示されている。例えば、
「太陽エネルギーと太陽電池」（Solar Energy and Sol
ar Cells）２９（１９９３）、１７５−１８２に、A.G.
Aberle,S.Glunz and W.Wartaにより報告されている。し
かしながら、実際に電界効果型太陽電池を作製すると、
電界効果を与える電圧印加用電極が大面積であるため、
半導体基板に短絡する不良が多発し、製品として問題が
ない歩留まりを全く得られなかった。2. Description of the Related Art In order to improve the photoelectric conversion efficiency of a crystalline silicon solar cell, it is generally important to reduce impurities and defects in a semiconductor and to reduce recombination of carriers on a crystal surface. To reduce surface recombination, thermal oxidation has been performed and passivation with an oxide film has been performed. However, the semiconductor surface after the production of the solar cell has an interface state of 1 × 10 10 / eVcm 2 or more even in a low density region near the mid gap. At this time, it is known that the characteristics of the solar cell greatly change according to the surface potential. For example, Otsuka, Agematsu, and Warabisako reported on pages 49 to 52 of the 4th "High Efficiency Solar Cell" Workshop Proceedings (Nara, 1994). In particular, the photoelectric conversion efficiency is greatly reduced in a normal operation state where there is almost no potential on the surface, and the photoelectric conversion efficiency is greatly improved if a positive or negative electric field can be applied. In recent years, a field effect solar cell has been proposed to solve this problem, and it has been shown that the characteristics of the solar cell are greatly improved by applying a voltage. For example,
"Solar Energy and Solar Cells"
ar Cells) 29 (1993), 175-182, AG
Reported by Aberle, S. Glunz and W. Warta. However, when actually manufacturing a field effect solar cell,
Since the voltage application electrode that gives the electric field effect has a large area,
There were frequent occurrences of short-circuits to the semiconductor substrate, and no yield was obtained with no problem as a product.

【０００３】[0003]

【発明が解決しようとする課題】上記半導体基板と電圧
印加用電極や他の電極との短絡の原因を明らかにすると
ともに、これらの原因を制御し製品としての歩留まりを
得ることが重要である。It is important to clarify the causes of the short circuit between the semiconductor substrate and the electrodes for voltage application and other electrodes, and to control these causes to obtain a product yield.

【０００４】本発明は、上記問題を解決し、製品の製造
上で問題がない電界効果型太陽電池を得ることを目的と
する。[0004] It is an object of the present invention to solve the above-mentioned problems and to obtain a field-effect solar cell having no problem in the manufacture of products.

【０００５】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

【０００６】上記目的は、第１のシリコン半導体層と第
２のシリコン半導体層からなる接合を有する太陽電池に
おいて、光入射側（表面側）とは反対側（裏面側）の面
に、裏面電極および電圧印加用電極を有し、上記裏面電
極と上記電圧印加用電極とが同一絶縁膜上にないことに
より達成され、また、上記電圧印加用電極が、ふっ酸に
より実質的にエッチングされない材料からなるか、また
は該材料により被覆されていることにより、また、上記
裏面電極が上記電圧印加用電極と異なる種類の導電性材
料からなることにより、また、上記裏面電極が基板に近
い第１絶縁膜上に形成され、上記電圧印加用電極が基板
から遠い第２絶縁膜上に形成されていることにより達成
され、上記電圧印加用電極が基板に近い第１絶縁膜上に
形成され、上記裏面電極が基板から遠い第２絶縁膜上に
形成されていることにより、また、上記電圧印加用電極
が膜厚方向に見て上記裏面電極と実質的に重なり合う部
分がないことにより、さらに、上記電圧印加用電極が上
記裏面電極に部分的に重なり合っており、その重なりは
３μｍ以上で、電圧印加用電極面積の１０％以下である
ことにより達成される。[0006] upper SL objects are achieved by a solar cell having a junction and a first silicon semiconductor layer made of the second silicon semiconductor layer, on the opposite side (back side) of the light incident side (surface side), the back surface This is achieved by having an electrode and a voltage application electrode, wherein the back electrode and the voltage application electrode are not on the same insulating film, and the voltage application electrode is made of hydrofluoric acid.
Consist of a material that is not substantially etched, or
Is covered with the material , the back electrode is made of a different kind of conductive material from the voltage application electrode, and the back electrode is formed on the first insulating film close to the substrate. The voltage application electrode is formed on the second insulating film far from the substrate, the voltage application electrode is formed on the first insulating film near the substrate, and the back electrode is formed from the substrate. By being formed on the distant second insulating film, and by the fact that there is no portion where the voltage applying electrode substantially overlaps with the back electrode when viewed in the film thickness direction, the voltage applying electrode is further It is partially overlapped with the back electrode, and the overlap is achieved by not less than 3 μm and not more than 10% of the area of the electrode for voltage application.

【０００７】[0007]

【発明の実施の形態】本発明は、電圧印加用電極下の絶
縁層にピンホールが生じることを防止し、電圧印加用電
極が裏面電極や基板と短絡するのを防ぐものである。つ
ぎに本発明の概略を、図１により説明する。図１は本発
明による電界効果型太陽電池の構造を示す模式図であ
り、ｐ型結晶シリコン基板１上にｎ型の拡散層２を形成
して接合とする。光入射側の表面は酸化膜４でパッシベ
ーションされるとともに、凹凸構造からなる光閉じ込め
構造や適当な無反射コーティング層５などが形成され、
高濃度のｎ型拡散層３を介して必要最低限の面積で、表
面電極６のフィンガーとバスバーが形成される。上記光
入射側と反対側の裏面側は、パッシベーション酸化膜
４′を形成したのちすぐに耐ふっ酸性の金属層７である
例えばクロム層が形成され、上記クロム層を電圧印加用
電極に加工し、これらのクロム層にコンタクト穴８を形
成し、さらに第２の絶縁層としてＣＶＤ法によりシリコ
ン酸化膜９を形成してコンタクト穴を形成したのち、裏
面電極層１０を形成する。上記構成とすることにより、
ふっ酸でエッチングされないクロム層７があることか
ら、コンタクト穴形成時に第１の絶縁膜であるパッシベ
ーション酸化膜４′にピンホールができる確率が大きく
減少し、電界効果が十分に付与できるようになった。す
なわち、コンタクト穴形成時に裏面側のパッシベーショ
ン酸化膜４′にピンホールを生じることが、本装置を作
製する上で最も大きな問題であることを明らかにし、上
記問題に対する対策を発明したものである。また、第２
の絶縁層であるシリコン酸化膜９を介しての裏面電極１
０と電圧印加用電極（耐ふっ酸性金属層７）間のショー
トも問題になるが、これは直接重なる部分の面積を十分
小さくできるので、上記第１の絶縁膜であるパッシベー
ション酸化膜４′のピンホールに比べて問題にならない
ことが判った。耐ふっ酸性の金属層７としては、アルミ
ニウム／クロムの２層膜を用いることも有効であった。
クロムに比べアルミニウムの方が反射率が高く、より光
の有効利用ができるからである。また、表面側にも透明
導電性酸化膜７′により電圧印加用電極を形成した。こ
の透明導電性酸化膜７′のエッチングがシリコン酸化膜
や無反射コーティング層を腐食しないので、上記透明導
電性酸化膜７′と基板１との短絡も見られなかった。た
だし、電圧印加の効果は裏面側ほど大きくなかった。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention prevents pinholes from being formed in an insulating layer below a voltage application electrode, and prevents the voltage application electrode from being short-circuited to a back electrode or a substrate. Next, the outline of the present invention will be described with reference to FIG. FIG. 1 is a schematic view showing the structure of a field-effect solar cell according to the present invention, in which an n-type diffusion layer 2 is formed on a p-type crystalline silicon substrate 1 to form a junction. The surface on the light incident side is passivated by the oxide film 4, and a light confinement structure having a concavo-convex structure and a suitable anti-reflection coating layer 5 are formed.
The fingers of the surface electrode 6 and the bus bar are formed with a minimum necessary area via the high concentration n-type diffusion layer 3. Immediately after the passivation oxide film 4 'is formed on the back side opposite to the light incident side, a fluorinated metal layer 7, for example, a chromium layer is formed. The chromium layer is processed into a voltage application electrode. Then, a contact hole 8 is formed in these chromium layers, a silicon oxide film 9 is formed as a second insulating layer by a CVD method to form a contact hole, and then a back electrode layer 10 is formed. With the above configuration,
Since there is the chromium layer 7 which is not etched with hydrofluoric acid, the probability that a pinhole is formed in the passivation oxide film 4 'which is the first insulating film when the contact hole is formed is greatly reduced, and the electric field effect can be sufficiently imparted. Was. That is, it has been clarified that the generation of a pinhole in the passivation oxide film 4 'on the back surface side during the formation of the contact hole is the biggest problem in manufacturing the present device, and the inventors have invented a countermeasure against the above problem. Also, the second
Back electrode 1 via silicon oxide film 9 which is an insulating layer of
Although a short circuit between 0 and the voltage application electrode (fluoride-resistant metal layer 7) also poses a problem, since the area of the directly overlapping portion can be sufficiently reduced, the passivation oxide film 4 'which is the first insulating film is not used. It turned out to be no problem compared to pinholes. It was also effective to use a two-layer film of aluminum / chromium as the metal layer 7 having resistance to hydrofluoric acid.
This is because aluminum has a higher reflectance than chromium and can use light more effectively. An electrode for voltage application was also formed on the surface side by a transparent conductive oxide film 7 '. Since the etching of the transparent conductive oxide film 7 'did not corrode the silicon oxide film or the anti-reflection coating layer, no short circuit was observed between the transparent conductive oxide film 7' and the substrate 1. However, the effect of the voltage application was not as large as that of the back side.

【０００８】[0008]

【実施例】つぎに本発明の実施例を図面とともに説明す
る。図２は本発明による構造の電界効果型太陽電池の第
１実施例を説明する概念図、図３は本発明の第２実施例
を説明する概念図、図４は本発明の第３実施例を説明す
る概念図、図５は本発明の第４実施例を説明する概念図
である。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a conceptual diagram illustrating a first embodiment of a field effect solar cell having a structure according to the present invention, FIG. 3 is a conceptual diagram illustrating a second embodiment of the present invention, and FIG. 4 is a third embodiment of the present invention. FIG. 5 is a conceptual diagram illustrating a fourth embodiment of the present invention.

【０００９】参考例 本発明の参考例における電界効果型太陽電池を示す図２
において、その形成工程を（ａ）から（ｅ）にそれぞれ
示す。図２（ａ）に示すように、ｐ型結晶シリコン基板
１の光入射側表面に光閉じ込め用の凹凸構造１１を異方
性エッチングにより形成した。つぎに拡散マスク用の熱
酸化膜１２を０．２μｍ形成し、周知の光食刻法により
高濃度りん拡散部分１３に穴あけを行った。ｎ型の高濃
度拡散層１４をＰＯＣｌ3の熱拡散により０．４μｍ形
成して接合とした。[0009] Figure 2 shows a field effect cell in Reference Example Reference Example present invention
In (a) to (e), the formation steps are shown, respectively. As shown in FIG. 2A, a concavo-convex structure 11 for confining light was formed on the light incident side surface of the p-type crystalline silicon substrate 1 by anisotropic etching. Next, a thermal oxide film 12 for a diffusion mask was formed to a thickness of 0.2 μm, and a hole was formed in the high-concentration phosphorus diffusion portion 13 by a known photo-etching method. An n-type high concentration diffusion layer 14 was formed to a thickness of 0.4 μm by thermal diffusion of POCl 3 to form a junction.

【００１０】つぎに図２（ｂ）に示すように、熱酸化膜
１２を除去し、基板の光入射側の全面にｎ型の低濃度拡
散層１５をＰＯＣｌ3の熱拡散により０．１５μｍ形成
して接合とした。さらに、拡散マスク用の熱酸化膜１６
を０．２μｍ形成した。つぎに図２（ｃ）に示すよう
に、周知の光食刻法を用いて裏面のボロン拡散部分１７
に穴あけを行った。ｐ型の拡散層１８をＢＢｒ3の熱拡
散により０．４μｍ形成して接合とした。ついで図２
（ｄ）に示すように、パッシベーション酸化膜１９を熱
酸化により約０．１μｍ形成した。さらに、電圧印加用
電極材料として耐ふっ酸性金層のＣｒ層２０を０．１μ
ｍ形成し、Ｃｒおよび酸化膜のエッチングにより、表面
および裏面に電極コンタクト用の穴２１および２２を形
成した。裏面のＣｒ層はさらにエッチングを行い電圧印
加用電極２３とした。このとき、表面側のＣｒ層はすべ
てエッチング除去した。さらに、図２（ｅ）に示すよう
に、必要最低限の面積で表面電極２４のフィンガーとバ
スバーをＡｇ電極で形成し、裏面電極層２５をＡｌ電極
で形成した。Next, as shown in FIG. 2B, the thermal oxide film 12 is removed, and an n-type low-concentration diffusion layer 15 is formed to a thickness of 0.15 μm by thermal diffusion of POCl 3 over the entire surface of the substrate on the light incident side. And joined. Further, the thermal oxide film 16 for the diffusion mask is used.
Was formed in a thickness of 0.2 μm. Next, as shown in FIG. 2C, the boron diffusion portion 17 on the back surface is formed by using a well-known optical etching method.
Was drilled. A p-type diffusion layer 18 was formed to a thickness of 0.4 μm by thermal diffusion of BBr 3 to form a junction. Then Figure 2
As shown in (d), a passivation oxide film 19 was formed to a thickness of about 0.1 μm by thermal oxidation. Further, as a voltage application electrode material, a 0.1 μm thick Cr layer 20 of a hydrofluoric acid resistant gold layer was used.
Then, holes 21 and 22 for electrode contact were formed on the front and back surfaces by etching the Cr and oxide films. The Cr layer on the back surface was further etched to form a voltage application electrode 23. At this time, all the Cr layer on the surface side was removed by etching. Further, as shown in FIG. 2E, the fingers and bus bars of the front surface electrode 24 were formed of Ag electrodes and the back electrode layer 25 was formed of Al electrodes with a minimum area.

【００１１】その結果、基板上の５ｃｍ2の素子すべて
において、電界効果用電極２３とシリコン基板１との間
に短絡は生じず、一度に作製した１５枚の基板すべてに
おいて、この部分の短絡は見られなかった。短絡がない
ことは、１００ＫＨｚ〜１ＭＨｚの周波数で容量を測定
し、酸化膜の容量が正しく評価されることで確認した。
短絡を生じるのは絶縁膜にピンホールがあるためと考え
られるが、１００ｃｍ2の基板について多数枚数の評価
を行っても短絡は見られなかったことから、ピンホール
密度は少なくとも１００ｃｍ2に１個程度以下と考えら
れる。そして、このピンホール密度の低減により、１０
ｃｍ角の太陽電池が上記部分の不良により不良品となる
ことはなくなった。As a result, no short circuit occurs between the field effect electrode 23 and the silicon substrate 1 in all the 5 cm 2 elements on the substrate, and the short circuit in this portion occurs in all of the 15 substrates manufactured at a time. I couldn't see it. The absence of a short circuit was confirmed by measuring the capacitance at a frequency of 100 KHz to 1 MHz and correctly evaluating the capacitance of the oxide film.
The short circuit is considered to be caused by pinholes in the insulating film. However, even when a large number of substrates of 100 cm 2 were evaluated, no short circuit was observed. Therefore, the pinhole density was at least one per 100 cm 2. It is considered below. And, due to the reduction of the pinhole density, 10
The cm square solar cell no longer becomes a defective product due to the above-mentioned defective portion.

【００１２】電圧印加用電極２３に１．５Ｖの電圧を印
加し、太陽電池の特性を測定したところ、電圧非印加時
に比べて光電変換効率が７．２％向上した。なお、表面
に光閉じ込め用の凹凸構造をもたない平坦表面素子も形
成したところ、表面反射の影響で光電変換効率は低くな
ったが、電圧印加の効果は凹凸構造がある場合と同様で
あり、平坦構造でも従来よりは高効率が得られた。When a voltage of 1.5 V was applied to the voltage applying electrode 23 and the characteristics of the solar cell were measured, the photoelectric conversion efficiency was improved by 7.2% as compared with when no voltage was applied. In addition, when a flat surface element having no concavo-convex structure for light confinement on the surface was also formed, the photoelectric conversion efficiency was reduced due to the influence of surface reflection, but the effect of voltage application was the same as in the case where there was a concavo-convex structure. Even with a flat structure, higher efficiency than before was obtained.

【００１３】第１実施例参考 例と同様に、ｐ型結晶シリコン基板１にｎ型および
ｐ型拡散を行った。つぎに図３（ａ）に示すように、パ
ッシベーション酸化膜２６を熱酸化により約０．１μｍ
形成した。さらに電圧印加電極用材料として耐ふっ酸性
金属のＣｒ層２７を０．１μｍ形成し、Ｃｒおよび酸化
膜のエッチングにより表面および裏面に電極コンタクト
用の穴２８および２９を形成した。Ｃｒ層はそのまま電
圧印加用電極３０とした。このとき、表面側のＣｒ層は
すべてエッチング除去した。[0013] Similar to the first embodiment in Reference Example was subjected to n-type and p-type diffusion in the p-type crystalline silicon substrate 1. Next, as shown in FIG. 3A, the passivation oxide film 26 is
Formed. Further, a Cr layer 27 of a fluorine-resistant metal was formed as a material for a voltage application electrode to a thickness of 0.1 μm, and holes 28 and 29 for electrode contacts were formed on the front and rear surfaces by etching the Cr and oxide films. The Cr layer was used as the voltage application electrode 30 as it was. At this time, all the Cr layer on the surface side was removed by etching.

【００１４】つぎに図３（ｂ）に示すように、裏面にＴ
ＥＯＳを原料としてｐ−ＣＶＤ法によりシリコン酸化膜
３１を０．５μｍ形成し、裏面電極コンタクト用の穴３
２をエッチングにより形成した。さらに図３（ｃ）に示
すように、Ａｌにより裏面電極３３を蒸着したのち加工
することにより形成した。このとき、電圧印加用電極３
０と裏面電極３３とは、わずかに重なるように配置し
た。さらに、必要最低限の面積で表面電極３４のフィン
ガーとバスバーをＡｇ電極で形成した。Next, as shown in FIG.
A silicon oxide film 31 is formed to a thickness of 0.5 μm by a p-CVD method using EOS as a raw material, and a hole 3 for a back electrode contact is formed.
2 was formed by etching. Further, as shown in FIG. 3C, the back electrode 33 was formed by evaporating the back electrode 33 and then processing it. At this time, the voltage application electrode 3
0 and the back electrode 33 are arranged so as to slightly overlap each other. Further, the finger and the bus bar of the surface electrode 34 were formed of an Ag electrode with a minimum area.

【００１５】上記の結果、電圧印加用電極３０とシリコ
ン基板１の間に短絡が生じないことは参考例と同様であ
り、さらに参考例では、電圧印加用電極２３と裏面電極
２５の間に、基板面内方向に電極金属がない部分を少な
くとも１０μｍのスペースでとる必要があるため、そ
の部分にきた光は反射されずに素子から出てしまう、
その部分には電界効果がかけられない、という問題があ
ったが、これらを解決することができた。その結果、太
陽電池特性において電圧を印加しないときに比べ、光電
変換効率で平均８．５％の向上が見られた。なお、電圧
印加用電極３３と表面電極３４の重なる部分は、原理的
には電圧印加用電極の全体を覆っていてもよい。しか
し、重なりが電圧印加用電極面積の１０％を越えると、
２つの電極間の短絡が数％の確率で見られるようになっ
た。一方、重なりが横方向に３μｍ以下であると、光食
刻時の合わせ誤差もあり光のロスを生じた。[0015] The above results, a short circuit does not occur between the voltage application electrode 30 and the silicon substrate 1 is the same as the reference example, the further reference example, during the voltage application electrode 23 and the back electrode 25, Since it is necessary to take a portion having no electrode metal in the in-plane direction of the substrate with a space of at least 10 μm, light coming to that portion exits the element without being reflected.
There was a problem that the electric field effect could not be applied to that part, but these could be solved. As a result, an average of 8.5% improvement in photoelectric conversion efficiency was observed in the solar cell characteristics as compared to when no voltage was applied. The overlapping portion of the voltage applying electrode 33 and the surface electrode 34 may cover the whole of the voltage applying electrode in principle. However, if the overlap exceeds 10% of the voltage application electrode area,
A short circuit between the two electrodes has been seen with a few percent probability. On the other hand, when the overlap was 3 μm or less in the horizontal direction, there was also an alignment error at the time of optical etching, resulting in light loss.

【００１６】第２実施例参考 例と同様に、ｐ型結晶シリコン基板１にｎ型および
ｐ型拡散を行った。つぎに図４（ａ）に示すように、パ
ッシベーション酸化膜３５を熱酸化により約０．１μｍ
形成し、さらに表面および裏面に電極コンタクト用の穴
を形成した。つぎにＡｌ層を蒸着しエッチング加工して
裏面電極３６とした。さらに、必要最低限の面積で表面
電極３７のフィンガーとバスバーをＡｇ電極で形成し
た。つぎに図４（ｂ）に示すように、裏面にＴＥＯＳを
原料としてｐ−ＣＶＤ法によりシリコン酸化膜３８を
０．３μｍ形成し、電圧印加用電極３９を蒸着法により
形成した。[0016] Similar to the second embodiment reference example was subjected to n-type and p-type diffusion in the p-type crystalline silicon substrate 1. One technique to as shown in FIG. 4 (a), about 0.1μm passivation oxide film 35 by thermal oxidation
Then, holes for electrode contacts were formed on the front and back surfaces. Next, an Al layer was deposited and etched to form a back electrode 36. Further, the finger and the bus bar of the surface electrode 37 were formed of an Ag electrode with a minimum required area. Next, as shown in FIG. 4B, a silicon oxide film 38 was formed on the back surface of the silicon oxide film 38 by a p-CVD method using TEOS as a raw material, and a voltage application electrode 39 was formed by a vapor deposition method.

【００１７】上記の結果、電圧印加用電極３９と、シリ
コン基板１および裏面電極３６の間には、ＴＥＯＳを原
料としてｐ−ＣＶＤ法により形成したシリコン酸化膜３
８が必ず存在し、この膜はエッチング工程がないので、
短絡をほとんど生じないことが判った。さらに光のロス
や、電界効果がかからない部分を生じる問題もなくなっ
た。その結果、太陽電池特性において、電圧を印加しな
い時に比べて光電変換効率で平均７．５％の向上が見ら
れた。As a result, the silicon oxide film 3 formed by p-CVD using TEOS as a raw material is provided between the voltage applying electrode 39 and the silicon substrate 1 and the back surface electrode 36.
8 always exists and this film has no etching process,
It turned out that a short circuit hardly occurred. In addition, there is no problem of loss of light or a portion where an electric field effect is not applied. As a result, in the solar cell characteristics, an average improvement of 7.5% in the photoelectric conversion efficiency was observed as compared with the case where no voltage was applied.

【００１８】[0018]

【００１９】上記各実施例中においては、結晶シリコン
基板としてｐ型基板を用いたが、ｎ型基板であってもよ
く、また、耐ふっ酸性の金属としてはクロムを示した
が、その他、モリブデン、タングステン、白金などであ
ってもよいし、アルミニウム表面を陽極酸化でアルミナ
とし、実質的に耐ふっ酸性とした配線層であっても良い
ことは、本発明の主旨から明らかである。絶縁膜として
も酸化シリコン膜だけでなく、窒化シリコン膜でもよい
しその混合物であってもよい。In each of the above embodiments, a p-type substrate was used as the crystalline silicon substrate. However, an n-type substrate may be used. In addition, chromium is shown as a hydrofluoric acid-resistant metal. It is apparent from the gist of the present invention that the wiring layer may be made of tungsten, platinum, or the like, or may be a wiring layer which is made of alumina by anodic oxidation and is substantially hydrofluoric acid resistant. The insulating film may be not only a silicon oxide film but also a silicon nitride film or a mixture thereof.

【００２０】また、太陽電池の例としては単結晶シリコ
ン太陽電池についてのみ示したが、多結晶シリコン太陽
電池に用いてもよいし、適切な絶縁膜が形成できればＧ
ａＡｓなどの化合物系太陽電池でも有効であることはい
うまでもない。Although only a single-crystal silicon solar cell has been described as an example of a solar cell, it may be used for a polycrystalline silicon solar cell, or if a suitable insulating film can be formed, the G cell may be used.
It goes without saying that compound-based solar cells such as aAs are also effective.

【００２１】[0021]

【発明の効果】上記のように本発明による電界効果型太
陽電池は、第１の半導体層と第２の半導体層からなる接
合を有する太陽電池において、光入射側（表面側）およ
び反対側（裏面側）の両面または片面に、電流取り出し
電極とは別に、絶縁性薄膜を介して電圧印加用電極を有
し、上記絶縁性薄膜は、ピンホールの確率が１００ｃｍ
2に１個以下のレベルにあることにより、電界効果型太
陽電池を歩留りよく製造することが可能になった。As described above, the field-effect solar cell according to the present invention is a solar cell having a junction composed of a first semiconductor layer and a second semiconductor layer, and has a light incident side (front side) and an opposite side (front side). On both sides or one side of the back side), a voltage application electrode is provided via an insulating thin film separately from the current extracting electrode, and the insulating thin film has a pinhole probability of 100 cm.
By in 2 to the level of one or less, it became possible to manufacture with good yield a field effect type solar cell.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による電界効果型太陽電池の構造を説明
する概念図である。FIG. 1 is a conceptual diagram illustrating the structure of a field-effect solar cell according to the present invention.

【図２】本発明の参考例を説明する概念図で、（ａ）〜
（ｅ）はそれぞれの形成工程を示す図である。FIG. 2 is a conceptual diagram illustrating a reference example of the present invention;
(E) is a figure which shows each forming process.

【図３】本発明の第１実施例を説明する概念図で、
（ａ）〜（ｃ）はそれぞれの形成工程を示す図である。FIG. 3 is a conceptual diagram illustrating a first embodiment of the present invention.
(A)-(c) is a figure which shows each forming process.

【図４】本発明の第２実施例を説明する概念図で、
（ａ）および（ｂ）はその形成工程を示す図である。FIG. 4 is a conceptual diagram illustrating a second embodiment of the present invention.
(A) And (b) is a figure which shows the formation process.

【符号の説明】[Explanation of symbols]

１ 第１半導体層 ２、１５、２６、３５ 第２半導体層 ６、２４、３４、３７ 電流取出し電極 １０、２５、３３、３６ 裏面電極４、４‘、９、 １９２６、３５ 絶縁性薄膜７、７‘、 ２３、３０、３７ 電圧印加用電極1 First semiconductor layer 2 , 15, 26 , 35 Second semiconductor layer 6 , 24 , 34 , 37 Current extraction electrode 10 , 25 , 33 , 36 Back surface electrode 4, 4 ', 9, 1926 , 35 Insulating thin film 7, 7 ', 23 , 30 , 37 Voltage application electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 蕨迫 光紀 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所 中央研究所内 (72)発明者 永田 寧 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所 中央研究所内 (72)発明者 坂本 雅彦 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所 中央研究所内 (56)参考文献 特開 昭61−206270（ＪＰ，Ａ) 特開 昭59−115542（ＪＰ，Ａ) 特開 昭64−71152（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 31/04 - 31/078 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuki Warabisako 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masahiko Sakamoto 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (56) References JP-A-61-206270 (JP, A) JP-A-59-115542 ( JP, A) JP-A-64-71152 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 31/04-31/078

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 第１のシリコン半導体層と第２のシリコン
半導体層からなる接合を有する太陽電池において、光入
射側（表面側）とは反対側（裏面側）の面に、裏面電極
および電圧印加用電極を有し、上記裏面電極と上記電圧
印加用電極とが同一絶縁膜上にないことを特徴とする電
界効果型太陽電池。 1. A a first silicon semiconductor layer solar cell having a junction formed of the second silicon semiconductor layer, on the opposite side (back side) of the light incident side (surface side), the back electrode and the voltage A field-effect solar cell having an application electrode, wherein the back electrode and the voltage application electrode are not on the same insulating film. 【請求項２】上記電圧印加用電極は、ふっ酸により実質
的にエッチングされない材料からなるか、または該材料
により被覆されていることを特徴とする請求項１記載の
電界効果型太陽電池。2. The field effect solar cell according to claim 1, wherein said voltage applying electrode is made of a material which is not substantially etched by hydrofluoric acid, or is coated with said material. 【請求項３】 上記裏面電極は、上記電圧印加用電極と異
なる種類の導電性材料からなることを特徴とする請求項
１又は２に記載の電界効果型太陽電池。 Wherein said back electrode, a field effect type solar cell according to claim 1 or 2, characterized in that it consists of different types of conductive material and the voltage application electrode. 【請求項４】 上記裏面電極は、基板に近い第１絶縁膜上
に形成され、上記電圧印加用電極が基板から遠い第２絶
縁膜上に形成されていることを特徴とする請求項１から
請求項３のいずれかに記載の電界効果型太陽電池。 4. The method according to claim 1, wherein the back electrode is formed on a first insulating film close to the substrate, and the voltage applying electrode is formed on a second insulating film far from the substrate. The field-effect solar cell according to claim 3 . 【請求項５】 上記電圧印加用電極は、基板に近い第１絶
縁膜上に形成され、上記裏面電極が基板から遠い第２絶
縁膜上に形成されていることを特徴とする請求項１から
請求項３のいずれかに記載の電界効果型太陽電池。 5. The method according to claim 1, wherein the voltage applying electrode is formed on a first insulating film near the substrate, and the back electrode is formed on a second insulating film far from the substrate. The field-effect solar cell according to claim 3 . 【請求項６】 上記電圧印加用電極は、膜厚方向に見て上
記裏面電極と実質的に重なり合う部分がないことを特徴
とする請求項１から請求項５のいずれかに記載の電界効
果型太陽電池。 Wherein said voltage application electrodes, field effect described as viewed in the thickness direction from claim 1, characterized in that there is no the back electrode substantially overlap portions to claim 5 Solar cells. 【請求項７】 上記電圧印加用電極は、上記裏面電極に部
分的に重なり合っており、その重なりは３μｍ以上で、
電圧印加用電極面積の１０％以下であることを特徴とす
る請求項１から請求項５のいずれかに記載の電界効果型
太陽電池。 7. The voltage application electrode partially overlaps the back electrode, and the overlap is 3 μm or more.
The field effect solar cell according to any one of claims 1 to 5 , wherein the area of the voltage application electrode is 10% or less.
JP08007227A 1996-01-19 1996-01-19 Field effect solar cell Expired - Fee Related JP3085180B2 (en)

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JP3468670B2 (en) * 1997-04-28 2003-11-17 シャープ株式会社 Solar cell and manufacturing method thereof
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US10199524B2 (en) * 2012-01-13 2019-02-05 International Business Machines Corporation Field-effect photovoltaic elements
JP6075667B2 (en) * 2014-05-26 2017-02-08 京セラ株式会社 Solar cell element
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