JP3083881B2 - Surge protection element - Google Patents
Surge protection elementInfo
- Publication number
- JP3083881B2 JP3083881B2 JP03211318A JP21131891A JP3083881B2 JP 3083881 B2 JP3083881 B2 JP 3083881B2 JP 03211318 A JP03211318 A JP 03211318A JP 21131891 A JP21131891 A JP 21131891A JP 3083881 B2 JP3083881 B2 JP 3083881B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- exposed
- semiconductor
- layer
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は通信回路などの弱電回路
のサージ防護に好適するサージ防護素子に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge protection device suitable for surge protection of a light electric circuit such as a communication circuit.
【０００２】[0002]
【従来の技術】通信回路などの弱電回路を正，負サージ
から保護するための手段として、小型安価であって動作
が高速なサージ防護素子、例えば図３（ａ）のように、
Ｐ1 Ｎ1 ＰＮ2 Ｐ3 の５層からなり、図３（ｂ）に示す
如き特性をもつＶBO点弧の両方向サイリスタ型サージ防
護素子が知られている。この素子Ｚは図３（ｃ）のよう
に通信回路などの被保護回路Ｇの線路Ｌ間に接続して使
用され、線路Ｌに侵入した正または負のサージ電圧Ｓ1
Ｓ2 が、素子Ｚの耐圧ＶBOを越えたときターンオンして
素子Ｚに電流を流して、被保護回路Ｇに耐圧ＶBO以上の
電圧が印加されないようにする。また素子Ｚに流れる電
流が減少して素子Ｚの保持電流ＩH を下廻ったとき、直
流電源電圧Ｅと線路抵抗Ｒにもとづく続流を遮断して通
常状態に復旧する動作を行う。2. Description of the Related Art As a means for protecting a weak electric circuit such as a communication circuit from positive and negative surges, a surge protector which is small and inexpensive and operates at high speed, for example, as shown in FIG.
2. Description of the Related Art A bidirectional thyristor-type surge protection element with a VBO firing characteristic comprising five layers of P 1 N 1 PN 2 P 3 and having characteristics as shown in FIG. 3B is known. The element Z is used to connect between the lines L of the protected circuit G such as a communication circuit as in FIG. 3 (c), the line L a positive or negative surge voltage entering the S 1
When S 2 exceeds the withstand voltage V BO of the element Z, it is turned on and a current flows through the element Z so that a voltage higher than the withstand voltage V BO is not applied to the protected circuit G. Further when the current flowing to the element Z is Shitamawa' the holding current I H of the reduced element Z, performs an operation to restore the normal state by blocking the connection flow based on the DC power supply voltage E and the line resistance R.
【０００３】[0003]
【発明が解決しようとする課題】ところでこのようなサ
ージ防護素子により、よりよいサージ防護を行うために
は、素子として次の条件を備えることが要求される。 耐圧ＶBOを直流電源電圧Ｅより大即ちＶBO＞Ｅの条
件を満足しながら、出来る限り小として防護能力の向上
を図る。 素子の保持電流ＩH を、ＩH ＞Ｅ／Ｒを満足しなが
らできる限り大として遮断能力の向上を図る。 サージ電流耐量が大きい。 被保護回路Ｇの通信性能を悪化を招かないようにす
るため、図３（ｃ）のように線路Ｌ間に挿入される素子
のもつ静電容量Ｃを極力小にする。 素子Ｚの耐圧ＶBOは、図３（ａ）の接合Ｊ2 または
Ｊ3 の逆方向耐圧をＶB 、構成トランジスタＮ1 ＰＮ2
の電流増幅率をαとしたとき、耐圧Ｖ BO は ＶBO＝ＶB （１−α）1 n ………（１） ただしｎ：２〜６ によって定まる。このためサージ電圧の立上り速度ｄＶ
／ｄｔが大になると、サージ印加時の動作開始電圧が耐
圧ＶBOによって決定されず、ＶBOより高い電圧ＶCL外１
ＶB となる。従ってよい防護能力をもたせるためＶBO＝
ＶCLに関係を満足させる。 ことが要求される。しかし例えば周知のように耐圧ＶBO
を小にすると、逆に素子Ｚのもつ静電容量Ｃは大になる
など、上記各条件の間に素子の設計上厳しいトレードオ
フの関係があり、従来の両方向サイリスタの構造によっ
ては上記の各条件を同時に満足させることは容易ではな
い。The [0005] Incidentally Such surge protection device, in order to make better surge-proof protection is required to be provided with the following conditions as an element. The withstand voltage V BO is higher than the DC power supply voltage E, that is, while satisfying the condition of V BO > E, and the protection capability is improved as small as possible. The holding current I H of the element is made as large as possible while satisfying I H > E / R to improve the breaking capability. Large surge current capability. To avoid incurring deterioration communication performance of the protected circuit G, as much as possible the small capacitance C with the element to be inserted between the line L as shown in FIG. 3 (c). The breakdown voltage V BO of the element Z is such that the reverse breakdown voltage of the junction J 2 or J 3 in FIG. 3A is V B , and the constituent transistors N 1 PN 2
When the current amplification factor is α , the breakdown voltage V BO is determined by V BO = V B (1−α) 1 n (1) where n: 2 to 6. Therefore, the surge voltage rise speed dV
When / dt becomes large, the operation start voltage at the time of applying a surge is not determined by the breakdown voltage V BO , and the voltage outside the voltage V CL higher than V BO
The V B. Therefore, V BO =
Satisfy the relationship with V CL . Is required. However, for example, as is well known, the withstand voltage V BO
Is small, conversely, the capacitance C of the element Z is large, and there is a strict trade-off relationship in the design of the element between the above conditions, and depending on the structure of the conventional bidirectional thyristor, It is not easy to satisfy the conditions at the same time.
【外１】 [Outside 1]
【０００４】[0004]
【発明の目的】本発明は上記〜の要求のうち、特に
耐圧（ＶBO）＝動作電圧ＶCLの実現と、保持電流ＩH の
増大の実現を図って防護能力と遮断能力を前記従来の両
方向サイリスタ型サージ防護素子より向上させた、サー
ジ防護素子の提示を目的とするものである。It is an object of the present invention to improve the protection capability and the interruption capability by realizing the breakdown voltage (V BO ) = operating voltage V CL and realizing an increase in the holding current I H among the above requirements. It is an object of the present invention to provide a surge protection element which is improved over a two-way thyristor type surge protection element.
【０００５】[0005]
【課題を解決するための手段】本発明の目的は次の手段
により達成される。即ち 図１（ａ）に示すように正
サージＳ1 に対してそれぞれ順方向となるダイオードＤ
1 と一方向サイリスタＴとダイオードＤ2 の直列回路か
らなり、正サージによる電流を線路接続端子ｔ1 からｔ
2 の一方向に流しうる回路と、負サージに対してそれぞ
れ順方向となるダイオードＤ3 と前記一方向サイリスタ
ＴとダイオードＤ4 の直列回路からなり、負サージによ
る電流を線路接続端子ｔ2 からｔ1 の一方向に流す回路
構成とする。そしてこれにより正または負サージ印加時
一方向サイリスタＴに常にＤ1 ，Ｄ2 およびＤ3 ，Ｄ4
のそれぞれ２個のダイオードが直列に入るようにして、
それぞれのダイオードの逆方向耐圧により一方向サイリ
スタＴが、逆方向耐圧をもつのを不要とする。 ダイ
オードＤ1 ，Ｄ2 およびＤ3 ，Ｄ4 により逆方向耐圧を
負担させる上記の回路構成から、一方向サイリスタＴ
を、図１（ｂ）のようにＰ1 Ｎ2 Ｐ3Ｎ4 の４層からな
り、そのＮ2 層とＰ3 層の一部がＰ1 層とＮ4 層を貫通
して表裏面に露呈し、かつこれらの露呈部分がＰ1 層と
Ｎ4 層と共に、金属電極Ｔ1 ，Ｔ2 により短絡した逆導
通型構成とする。そして以下に説明する本発明の一方向
サイリスタの作用説明から明らかなように、一方向サイ
リスタＴの降伏が接合Ｊ2 の単なる降伏、即ち接合Ｊ2
の降伏電圧ＶB を越えたとき始まるようにして、前記従
来素子におけるＶBO＜ＶCLの関係を打破し、また逆方向
耐圧が不要であること、即ち逆導通でよいことから、表
裏面にショートゲート構造Ｆ，Ｈの形成を可能とし、こ
れにより保持電流の増大を図りうるようにして目的を達
成したものである。The object of the present invention is achieved by the following means. Diode D That made respectively forward direction with respect to the positive surge S 1 as shown in FIG. 1 (a)
Consist of a series circuit of the one-way thyristor T and a diode D 2, t the current due to the positive surge from the line connecting terminal t 1
2, a circuit that can flow in one direction, a diode D 3 that becomes forward with respect to the negative surge, and a series circuit of the one-way thyristor T and the diode D 4 , and a current due to the negative surge is transmitted from the line connection terminal t 2. a circuit configuration to flow in one direction of t 1. Thus, when a positive or negative surge is applied, the one-way thyristor T always has D 1 , D 2 and D 3 , D 4
So that each two diodes are in series,
The reverse breakdown voltage of each diode eliminates the need for the unidirectional thyristor T to have a reverse breakdown voltage. From the above circuit configuration in which the diodes D 1 and D 2 and D 3 and D 4 bear the reverse breakdown voltage, the one-way thyristor T
Is composed of four layers of P 1 N 2 P 3 N 4 as shown in FIG. 1 (b), and the N 2 layer and a part of the P 3 layer penetrate the P 1 layer and the N 4 layer and are formed on the front and back surfaces. A reverse conduction type in which the exposed portions are short-circuited by the metal electrodes T 1 and T 2 together with the P 1 layer and the N 4 layer. And as is clear from the action description of one-way thyristor of the present invention described below, the yield of the one-way thyristor T is simply a breakdown of the junction J 2, i.e. the junction J 2
As starting when exceeding the breakdown voltage V B, the break down the relationship V BO <V CL in the conventional device, also possible reverse breakdown voltage is not necessary, i.e. since it is reverse conducting, on the front and back surfaces The object is achieved by enabling the formation of the short gate structures F and H, thereby increasing the holding current.
【０００６】そして、本発明のサージ防護素子の具体的
な構成は、図２に示すように、第１の導電型を有する第
１半導体層と、第２の導電型を有する第２半導体層と、
第１の導電型を有する第３半導体層と、第２の導電型を
有する第４半導体層とが順次に積層された４層構造を有
し、前記第２半導体層の一部が前記第１半導体層を分離
することなく一体形成が維持されるように複数箇所にお
いて該第１半導体層を突き抜けて一方の面に露呈させる
と共に、前記第３半導体層の一部が前記第４半導体層を
分離することなく一体形成が維持されるように複数箇所
において該第４半導体層を突き抜けて他方の面に露呈さ
せ、前記一方の面に露呈された複数個の前記第２半導体
層と前記第１半導体層とを接続した一方の電極と、前記
他方の面に露呈された複数個の前記第３半導体層と前記
第４半導体層とを接続した一方の電極とを備え、かつ前
記一方の電極と接続された複数個の前記第２半導体層と
前記他方の電極と接続された複数個の前記第３半導体層
とは、前記一方の面と他方の面に直交する方向で相互に
重ならないように構成されたものである。 [0006] The specific example of the surge protection element of the present invention is as follows.
The configuration shown in FIG. 2 has a first conductivity type.
One semiconductor layer, a second semiconductor layer having a second conductivity type,
A third semiconductor layer having a first conductivity type;
Has a four-layer structure in which a fourth semiconductor layer is sequentially laminated.
And a part of the second semiconductor layer separates the first semiconductor layer.
At multiple locations so that the integral formation is maintained without
Through the first semiconductor layer to expose it on one surface
In addition, a part of the third semiconductor layer forms the fourth semiconductor layer.
Multiple locations to maintain unitary formation without separation
Pierces through the fourth semiconductor layer and is exposed on the other surface.
The plurality of second semiconductors exposed on the one surface.
One electrode connecting the layer and the first semiconductor layer,
A plurality of the third semiconductor layers exposed on the other surface;
And one electrode connected to the fourth semiconductor layer.
A plurality of the second semiconductor layers connected to the one electrode;
A plurality of the third semiconductor layers connected to the other electrode
Are mutually perpendicular in a direction perpendicular to the one surface and the other surface.
It is configured not to overlap.
【０００７】[0007]
【作用】本発明の一方向サイリスタは次のように動作す
る。即ち図１（ａ）においてダイオードＤ1 ，Ｄ2 を介
して一方向サイリスタＴの金属電極Ｔ1 からＴ2 の方向
に電圧が印加されると、図１（ｂ）に示す一方向サイリ
スタＴの正方向接合Ｊ2は逆バイアスとなり、電圧が接
合Ｊ2 の降伏電圧ＶB に達すると電流Ｉ1 ，Ｉ2が流れ
始める。これらの電流成分はエミッタ直下のＮ2 層とＰ
3 層の実効横方向抵抗ＲN ＲP により、Ｎ2 層とＰ3 層
にそれぞれＲN Ｉ1 ，ＲP Ｉ2 の電圧降下を生じさせ、
これらの電圧降下は接合Ｊ1 を左端に行くに従い正バイ
アスし、また接合Ｊ3 の右端に行くに従い正バイアスす
る。そしてこのバイアス電圧が接合Ｊ2 Ｊ3 の正方向立
上り電圧ＶD 程度になると、接合Ｊ1 とＪ3 からそれぞ
れ正孔と電子の注入が行われてオン状態に移行する。一
方図１（ａ）においてダイオードＤ3 Ｄ4 を介して一方
向サイリスタＴの金属電極Ｔ2 からＴ1 の方向の電圧が
印加されると、図１（ｂ）の一方向サイリスタＴは接合
Ｊ2 の正方向特性を示すのみである。また更にオン状態
からオフ状態に移行する場合には、電流Ｉ1 ，Ｉ2 が減
少して接合Ｊ1 ，Ｊ3 の注入が停止することによりター
ンオフする。従ってこの一方向サイリスタの特性は図１
（ｃ）のようになる。以上から本発明の一方向サイリス
タＴの降伏は単に、ＰＮ接合Ｊ2 の降伏電圧ＶB によっ
て定まるため、前記した従来の素子のように耐圧ＶBOと
動作電圧ＶCLとの間に差を生ずることがなくなり、前記
ＶBO＜ＶCLの問題は解決される。またターンオフは電流
１1 ，Ｉ2 が The one-way thyristor of the present invention operates as follows. That is, when a voltage is applied in the direction from the metal electrode T 1 to T 2 of the one-way thyristor T via the diodes D 1 and D 2 in FIG. 1A, the one-way thyristor T shown in FIG. forward junction J 2 becomes reverse biased, current I 1 when the voltage reaches the breakdown voltage V B of the junction J 2, I 2 starts to flow. These current components are caused by the N 2 layer just below the emitter and the P 2
The three layers of effective lateral resistance R N R P cause a voltage drop of R NI 1 and R P I 2 in the N 2 layer and the P 3 layer, respectively.
These voltage drops are positively biased as it goes the junction J 1 to the left end, and also a positive bias as it goes to the right end of the joint J 3. When the bias voltage becomes about the positive rise voltage V D of the junction J 2 J 3 , holes and electrons are injected from the junctions J 1 and J 3 , respectively, and the junction is turned on. On the other hand, if FIGS. 1 (a) direction of the voltage of the diode D 3 D 4 T 1 from the metal electrode T 2 of the unidirectional thyristor T via the in is applied, one-way thyristor T is bonded J shown in FIG. 1 (b) It only shows a positive direction characteristic of 2 . When the state further shifts from the on state to the off state, the currents I 1 and I 2 decrease, and the injection of the junctions J 1 and J 3 is stopped, thereby turning off. Therefore, the characteristics of this one-way thyristor are shown in FIG.
(C). Simply yield unidirectional thyristors T of the present invention from above, because determined by the breakdown voltage V B of the PN junction J 2, occurs a difference between the breakdown voltage V BO and the operating voltage V CL as in the conventional device described above And the problem of V BO <V CL is solved. In turn-off, current 1 1 and I 2
【数１】 程度以下になったとき、接合Ｊ1 ，Ｊ3 から正孔および
電子の注入が止むので、本発明で保持電流ＩH を増加す
ることができ、しかも本発明の一方向サイリスタでは両
面ショートゲート構造であるので、保持電流ＩH の増大
効果は大きい。またサージ電流耐量はショートゲート部
以外の有効面積できまるから、ショートゲート部の面積
を小さくすればサージ電流耐量に対する影響はない。次
に本発明の一方向サイリスタの実施例について説明す
る。(Equation 1) When the temperature falls below the threshold, injection of holes and electrons from the junctions J 1 and J 3 stops, so that the holding current I H can be increased in the present invention, and the unidirectional thyristor of the present invention has a double-sided short gate structure. Therefore, the effect of increasing the holding current I H is large. Also, the surge current tolerance is determined by the effective area other than the short gate portion. Therefore, if the area of the short gate portion is reduced, the surge current tolerance is not affected. Next, an embodiment of the one-way thyristor of the present invention will be described.
【０００８】[0008]
【実施例】図２（ａ）（ｂ）は拡散法により製造された
本発明の一方向サイリスタの一実施例を示す平面図およ
びそのＡ−Ａ’部断面図である。この例は表面の中心部
と外周４角との５箇所においてＮ2 層の一部をＰ1 層を
貫通させて表面に露呈させ、この露呈Ｎ2 層とＰ1 層と
を金属電極Ｔ1 により短絡し、裏面の外周辺の４箇所に
おいてＰ3 層の１部をＮ4 層を貫通させて裏面に露呈さ
せ、Ｐ3 層の露呈部とＮ4 層とを金属電極Ｔ2 により短
絡したものである。この場合表裏面におけるショートゲ
ート構造Ｆ，Ｈの数が多い程保持電流ＩHが大になるこ
とは明らかであり、また表裏面におけるショートゲート
構造間の距離が小さい程保持電流ＩH の増大効果が大に
なることも明らかである。また安定なターンオンを実現
するためには、最初中央部でターンオンが行われ、これ
が次第に周辺全面に拡がるようにすることが望まれしい
が、それには図２（ａ）中の距離Ｌ1 とＬ2 をＬ 2 ≧２
Ｌ 1 にするのがよい。また以上ではＰ1 Ｎ2 Ｐ3 Ｎ4 の
導電型について説明したが、導電型を逆にしてもよいこ
とは云うまでもない。DETAILED DESCRIPTION FIG. 2 (a) (b) is a plan view and a A-A 'sectional view showing an embodiment of a one-way thyristor of the present invention produced by diffusion. This example is in the center of the surface
A portion of N 2 layer is exposed on the surface by penetrating the P 1 layer, and the exposed N 2 layer and the P 1 layer shorted by metal electrodes T 1 in the five points between the outer square and the back surface outside that a portion of <br/> Oite P 3 layers at four positions near by penetrating the N 4 layer is exposed on the back surface was a exposed portion of the P 3 layer and N 4 layer and short-circuited by the metal electrode T 2 It is. In this case, it is clear that the larger the number of the short gate structures F and H on the front and back surfaces, the larger the holding current I H , and the shorter the distance between the short gate structures on the front and back surfaces, the larger the holding current I H. It is also clear that is large. In order to realize a stable turn-on, turn-on is performed by the first central part, which gradually Shi is desirable to make spreads around the entire surface bur, it is a distance L 1 in FIG. 2 (a) L 2 is L 2 ≧ 2
It is preferable to L 1. In the above, P 1 N 2 P 3 N 4
Although the conductivity type has been described, it goes without saying that the conductivity type may be reversed.
【０００９】[0009]
【発明の効果】以上の説明から明らかなように本発明に
よれば、防護能力が高くしかも遮断能力の高いＶBO点弧
のサージ防護素子を提供できるもので、通信回路などこ
の種弱電回路のサージ防護に用いて大きな効果を発揮す
る。According to apparent the present invention from the above description, as it can provide a surge protection device of high V BO firing of higher Moreover blocking capability protection capability, this type of light electrical circuit such as a communication circuit It is very effective for surge protection.
【図１】本発明のサージ防護素子の説明図である。FIG. 1 is an explanatory view of a surge protection element of the present invention.
【図２】本発明の一実施例の説明図である。FIG. 2 is an explanatory diagram of one embodiment of the present invention.
【図３】従来のサージ防護素子の説明図である。 FIG. 3 is an explanatory diagram of a conventional surge protection element.
Ｚ サージ防護素子 Ｌ 線路 Ｇ 被保護回路 Ｅ 直流電源 Ｒ 線路抵抗 Ｄ1 ，Ｄ2 ，Ｄ3 ，Ｄ4 ダイオード Ｔ 一方向サイリスタ Ｆ，Ｈ ショートゲート構造Z surge protection element L line G the protected circuit E DC power supply R line resistance D 1, D 2, D 3 , D 4 diodes T unidirectional thyristors F, H Short gate structure
Claims (2)
第２の導電型を有する第２半導体層と、第１の導電型を
有する第３半導体層と、第２の導電型を有する第４半導
体層とが順次に積層された４層構造を有し、 前記第２半導体層の一部が前記第１半導体層を分離する
ことなく一体形成が維持されるように複数箇所において
該第１半導体層を突き抜けて一方の面に露呈させると共
に、前記第３半導体層の一部が前記第４半導体層を分離
することなく一体形成が維持されるように複数箇所にお
いて該第４半導体層を突き抜けて他方の面に露呈させ、 前記一方の面に露呈された複数個の前記第２半導体層と
前記第１半導体層とを接続した一方の電極と、前記他方
の面に露呈された複数個の前記第３半導体層と前記第４
半導体層とを接続した一方の電極とを備え、 かつ前記一方の電極と接続された複数個の前記第２半導
体層と前記他方の電極と接続された複数個の前記第３半
導体層とは、前記一方の面と他方の面に直交する方向で
相互に重ならないように構成された サージ防護素子。A first semiconductor layer having a first conductivity type;
A second semiconductor layer having a second conductivity type;
Having a third semiconductor layer and a fourth semiconductor having a second conductivity type
A four-layer structure in which body layers are sequentially stacked, and a part of the second semiconductor layer separates the first semiconductor layer
At multiple locations so that the integral formation is maintained without
When penetrating through the first semiconductor layer and exposing it to one surface,
A part of the third semiconductor layer separates the fourth semiconductor layer;
At multiple locations so that the integral formation is maintained without
And exposing the second semiconductor layer through the fourth semiconductor layer and exposing the second semiconductor layer to the other surface.
One electrode connected to the first semiconductor layer and the other electrode
A plurality of the third semiconductor layers exposed on the surface of
A second electrode connected to the semiconductor layer; and a plurality of the second semiconductors connected to the one electrode.
A plurality of third halves connected to a body layer and the other electrode;
The conductor layer is a direction perpendicular to the one surface and the other surface.
Surge protection elements configured not to overlap each other .
２半導体層は前記第１半導体層のほぼ中心に１個と該第
１半導体層の外周辺に複数個露呈させると共に、前記他
方の面に露呈する複数個の前記第３半導体層は前記第４
半導体層の外周辺に複数個露呈させ、 かつ前記一方の面から前記他方の面を透視した状態で、
前記一方の面のほぼ中心部に露呈する前記第２半導体層
の中心部から前記他方の面の外周辺に露呈する各複数個
の前記第３半導体層の中心部までの距離が、該他方の面
の外周辺に露呈する各複数個の前記第３半導体層の中心
部から前記第４半導体層の外周縁までの距離の２倍以上
になるようにそれぞれ露呈せしめた請求項１に記載のサ
ージ防護素子。 2. The method according to claim 1 , wherein the plurality of first surfaces are exposed on the one surface.
The two semiconductor layers are substantially one at the center of the first semiconductor layer and the first semiconductor layer.
A plurality of semiconductor devices are exposed around the outer periphery of one semiconductor layer,
The plurality of third semiconductor layers exposed on one side are the fourth semiconductor layers.
In a state where a plurality of the semiconductor layers are exposed to the outer periphery, and the other surface is seen through from the one surface,
The second semiconductor layer exposed substantially at the center of the one surface;
A plurality of each exposed from the center of the outer periphery of the other surface
The distance to the center of the third semiconductor layer is the other surface.
Center of each of the plurality of third semiconductor layers exposed to the outer periphery
At least twice the distance from the portion to the outer peripheral edge of the fourth semiconductor layer
2. The service according to claim 1, which is exposed so that
Protection element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03211318A JP3083881B2 (en) | 1991-07-30 | 1991-07-30 | Surge protection element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03211318A JP3083881B2 (en) | 1991-07-30 | 1991-07-30 | Surge protection element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0536979A JPH0536979A (en) | 1993-02-12 |
| JP3083881B2 true JP3083881B2 (en) | 2000-09-04 |
Family
ID=16603967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03211318A Expired - Fee Related JP3083881B2 (en) | 1991-07-30 | 1991-07-30 | Surge protection element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3083881B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8378545B2 (en) | 2005-08-26 | 2013-02-19 | Hoganas Ab (Publ) | Electrical rotary machine assembly with stator core sections |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003041236A1 (en) * | 2001-11-07 | 2003-05-15 | Shindengen Electric Manufacturing Co., Ltd. | Surge protecting semiconductor device |
| EP1453094A4 (en) * | 2001-11-07 | 2006-08-23 | Shindengen Electric Mfg | Surge protection semiconductor device |
| KR100559938B1 (en) * | 2004-01-28 | 2006-03-13 | 광전자 주식회사 | transient voltage suppressor diode |
| JP5532538B2 (en) | 2008-02-04 | 2014-06-25 | 三菱電機株式会社 | Protection circuit |
| JP5658960B2 (en) * | 2010-09-28 | 2015-01-28 | 新電元工業株式会社 | Semiconductor device |
| CN104412339B (en) * | 2012-07-05 | 2017-10-17 | 保险丝公司 | Crow bar device for voltage transient circuit protection |
-
1991
- 1991-07-30 JP JP03211318A patent/JP3083881B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8378545B2 (en) | 2005-08-26 | 2013-02-19 | Hoganas Ab (Publ) | Electrical rotary machine assembly with stator core sections |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0536979A (en) | 1993-02-12 |
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