JP3069621B2 - Lead frame and manufacturing method thereof - Google Patents
Lead frame and manufacturing method thereofInfo
- Publication number
- JP3069621B2 JP3069621B2 JP35819092A JP35819092A JP3069621B2 JP 3069621 B2 JP3069621 B2 JP 3069621B2 JP 35819092 A JP35819092 A JP 35819092A JP 35819092 A JP35819092 A JP 35819092A JP 3069621 B2 JP3069621 B2 JP 3069621B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- chip
- lead frame
- slit
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はチップをパッドの所定位
置に精度よく、且つ迅速に搭載でき、またボンディング
ワイヤ−を短くできるリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame capable of accurately and quickly mounting a chip on a predetermined position of a pad and shortening a bonding wire.
【０００２】[0002]
【従来の技術】半導体装置は、例えばリードフレームの
パッドにチップを接着剤を介し固着搭載し、その後、チ
ップ端子とリードフレームのインナーリードをボンディ
ングワイヤ−で溶接接続し、樹脂封止を行って製造され
る。2. Description of the Related Art In a semiconductor device, for example, a chip is fixedly mounted on a pad of a lead frame via an adhesive, and then a chip terminal and an inner lead of the lead frame are welded and connected by a bonding wire, and resin sealing is performed. Manufactured.
【０００３】半導体装置は高機能化、小型化および薄手
化することを要請されている。この対応にチップの高集
積度化、リードの多ピン化、パッケ−ジ樹脂厚みの減少
等が図られている。[0003] There is a demand for a semiconductor device having higher function, smaller size, and thinner. In order to cope with this, a higher degree of integration of the chip, an increase in the number of leads of the lead, a reduction in the thickness of the package resin, and the like have been attempted.
【０００４】特にチップが高集積度になるものでは信号
処理の高速化、さらには短絡を防ぐためにボンディング
ワイヤ−を短くすることが試みられている。例えば特開
平２−１３９９５４号公報に記載のようにパッドを支持
するサポ−トバ−を下方に押し曲げ、パッドに搭載した
チップとインナーリードの垂直方向の距離を狭めて、ボ
ンディングワイヤ−を短くし短絡を防止している。In particular, when the chip has a high degree of integration, attempts have been made to increase the speed of signal processing and to shorten the bonding wires in order to prevent short circuits. For example, as described in Japanese Patent Application Laid-Open No. 2-139954, a support bar for supporting a pad is pressed and bent downward to reduce a vertical distance between a chip mounted on the pad and an inner lead, thereby shortening a bonding wire. Short circuit is prevented.
【０００５】[0005]
【この発明が解決しようとする課題】ところで、ワイヤ
−ボンディングは微細な金属線でチップ端子とインナー
リードを接続するが、その際、チップがパッドの所定位
置に精度よく搭載されていないと溶接接続作業が高速下
にできない。またパッドが傾いたり、反りを呈している
とチップの姿勢も影響を受けワイヤ−ボンディング作業
に支障を及ぼす。In the wire bonding, a chip terminal and an inner lead are connected by a fine metal wire. At this time, if the chip is not accurately mounted at a predetermined position on a pad, a welding connection is made. Work cannot be performed at high speed. If the pad is tilted or warped, the position of the chip is also affected, which hinders the wire-bonding operation.
【０００６】半導体装置はワイヤ−ボンディング後に樹
脂封止されるが、薄型化のために樹脂封止厚みを薄くす
る。この際、樹脂と金属製のリードフレームは熱膨張率
が異なり、樹脂封止固め等での温度上昇で熱応力が発生
し反りやクラックが生じることがある。[0006] A semiconductor device is sealed with a resin after wire-bonding, and the thickness of the resin sealing is reduced to reduce the thickness. In this case, the resin and the metal lead frame have different coefficients of thermal expansion, and thermal stress is generated due to a rise in temperature due to resin sealing and consolidation, so that warping or cracking may occur.
【０００７】本発明はチップをパッドの所定位置に精度
よく且つ迅速に搭載でき、例えピン数が多くてもワイヤ
−ボンデイングが高速にて行え、ボンディングワイヤ−
も短くでき、また、樹脂封止固め時など温度変化を受け
た場合には熱膨張差に基づく熱応力を解放でき信頼性の
優れた半導体装置を作れるリードフレームを目的とす
る。According to the present invention, a chip can be accurately and quickly mounted on a predetermined position of a pad, and even if the number of pins is large, wire bonding can be performed at a high speed, and a bonding wire can be formed.
Another object of the present invention is to provide a lead frame capable of releasing a thermal stress based on a difference in thermal expansion when a temperature change is caused, for example, at the time of hardening with resin sealing, and capable of manufacturing a semiconductor device having excellent reliability.
【０００８】[0008]
【課題を解決するための手段】本発明の要旨は、パッド
内の１部を下げたリードフレームにおいて、パッドのチ
ップ搭載予定箇所を挟さむ４辺にコ−ナ−の１部を除き
スリットが形成されているとともに、スリット途切れ部
が屈曲されチップ搭載予定箇所を下げたリードフレーム
にある。他の要旨は、パッド内の１部を下げるリードフ
レームの製造方法において、パッドのチップ搭載予定箇
所を挟さむ４辺にコ−ナ−の１部を除いてスリットを穿
設し、その後、コ−ナ−のスリット途切れ部を押し下げ
加工しパッド内のチップ搭載予定箇所を下げるリードフ
レームの製造方法にある。SUMMARY OF THE INVENTION The gist of the present invention is that, in a lead frame in which a part of a pad is lowered, a slit is formed on four sides sandwiching a chip mounting portion of the pad except for a part of a corner. It is formed on a lead frame in which a portion where a slit is to be cut is bent and a portion where a chip is to be mounted is lowered. Another point is that, in a method of manufacturing a lead frame in which a part of a pad is lowered, slits are formed on four sides of a pad where a chip is to be mounted, excluding a part of a corner. The present invention is directed to a method of manufacturing a lead frame in which a portion where a chip is to be mounted in a pad is lowered by pressing down a broken portion of a slit of a knife.
【０００９】[0009]
【作用】本発明ではパッドのチップ搭載予定箇所を挟む
４辺にコ−ナ−の１部を除きスリットを連続的または断
続的に穿設しているから、チップを所定位置に精度よ
く,且つ迅速に搭載できる。チップ搭載予定箇所はコ−
ナ−のスリット途切れ部の狭幅にて接続し支承されてい
る部分を押し下げ加工で屈曲し下げられているので、ボ
ンディングワイヤ−を短くでき、また前記狭幅の加工で
は加工力を小さくできサポ−トバ−の負荷が下がって変
形せずパッドに傾きや反りを生じない。According to the present invention, the slits are continuously or intermittently formed on the four sides of the pad where the chip is to be mounted, except for a part of the corner, so that the chip can be accurately positioned at a predetermined position. Can be mounted quickly. The chip mounting location is
Since the part which is connected and supported by the narrow width of the slit break part of the nail is bent down by pressing down, the bonding wire can be shortened, and the processing force can be reduced in the narrow width processing, and the support can be reduced. -The load on the bar is reduced and the pad is not deformed and the pad is not tilted or warped.
【００１０】パッドに前記スリットが穿設されているか
ら、樹脂封止固め時などで高温化し熱応力を生じても、
直ちに解放しクラックの発生がなく半導体装置の信頼性
を永く維持できる。またスリットで区画されたチップ搭
載予定箇所とチップの面積は殆ど等しいので樹脂封止等
での温度上昇と降下の熱履歴を受けても熱膨張・収縮の
絶対的な寸法の変化が小さくチップ剥離や反りを生じな
い。[0010] Since the above-mentioned slit is formed in the pad, even if the temperature becomes high and the thermal stress is generated at the time of resin sealing and hardening, etc.,
The semiconductor device is immediately released and cracks are not generated, and the reliability of the semiconductor device can be maintained for a long time. Also, since the chip mounting area divided by the slit is almost the same as the chip area, the absolute dimensional change in thermal expansion and contraction is small even when subjected to the thermal history of temperature rise and fall due to resin sealing etc. Does not cause warping.
【００１１】[0011]
【実施例】次に、本発明について１実施例に基づき図面
を参照し詳細に説明する。図面において、１はプレスま
たはエッチングでパターンが形成されたリードフレーム
で、２はパッド、３はインナーリード、４はアウターリ
ード、５はタイバ−、６はサポ−トバ−である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on one embodiment with reference to the drawings. In the drawings, 1 is a lead frame on which a pattern is formed by pressing or etching, 2 is a pad, 3 is an inner lead, 4 is an outer lead, 5 is a tie bar, and 6 is a support bar.
【００１２】７は前記パッド２に穿設したスリットで、
チップ搭載予定箇所８を挟さみ４辺にコ−ナ−の１部を
除き形成している。スリット７はパッド２に対して横方
向に形成したスリット７ａと縦方向に形成したスリット
７ｂでは幅を変え、この実施例では横方向スリット７ａ
を幅広としている。該幅を変えることで両スリット７
ａ、７ｂ間の途切れ部９を長方形状とし、その後、チッ
プ搭載予定箇所８を押し下げ加工する際、パッド２に傾
きを生じさせず且つサポ−トバ−６に荷重を掛けず小さ
な加工力できるようにしている。Reference numeral 7 denotes a slit formed in the pad 2;
Except for a part of the corner, the chip mounting portion 8 is sandwiched between the four sides. The width of the slit 7 is changed between a slit 7a formed in the horizontal direction and a slit 7b formed in the vertical direction with respect to the pad 2. In this embodiment, the width of the slit 7a is changed.
Is wide. By changing the width, both slits 7
A break 9 between a and 7b is formed in a rectangular shape. Thereafter, when the chip mounting portion 8 is pressed down, the pad 2 is not inclined and a small processing force can be applied without applying a load to the support bar 6. I have to.
【００１３】前記スリット７は実施例ではチップ搭載予
定箇所８の側面に連続的に形成しているが、これに限ら
ず断続的に形成してもよい。In the embodiment, the slit 7 is formed continuously on the side surface of the portion 8 where the chip is to be mounted. However, the present invention is not limited to this, and the slit 7 may be formed intermittently.
【００１４】１０はパッド部内押し下げ成形加工部で、
前記スリット７ａ、７ｂ間の狭幅な途切れ部９を図３に
示すようなパンチ１１とダイ１２により押し曲げ下げ屈
曲した箇所である。当該成形加工部１０は押し下げら
れ、または板厚が若干薄くなって押し下げられチップ搭
載予定箇所８を下方に位置させる。これではサポ−トバ
−６を変形することなくパッド２のチップ搭載予定箇所
８が下げられボンディングワイヤ−を短くできる。Reference numeral 10 denotes a press-down forming portion in the pad portion.
This is a place where a narrow gap 9 between the slits 7a and 7b is pushed down and bent by a punch 11 and a die 12 as shown in FIG. The forming section 10 is pushed down, or the sheet thickness is slightly reduced and pushed down, so that the chip mounting scheduled portion 8 is positioned below. Thus, the chip mounting portion 8 of the pad 2 can be lowered without deforming the support bar 6, and the bonding wire can be shortened.
【００１５】なお、１３はパッド２全体を押し下げたサ
ポ−トバ−押し下げ部で公知のディプレスである。Reference numeral 13 denotes a well-known depressing portion which is a support bar press-down portion which presses down the entire pad 2.
【００１６】１４はチップ搭載予定箇所８に搭載された
チップで、前記スリット７ａ、７ｂで位置が明示される
から所定位置に精度よく且つ迅速に搭載できる。１５は
チップ端子とインナーリード３を接続したボンディング
ワイヤ−である。Reference numeral 14 denotes a chip mounted on the intended chip mounting position 8, which can be accurately and quickly mounted at a predetermined position since the position is clearly indicated by the slits 7a and 7b. Reference numeral 15 denotes a bonding wire connecting the chip terminal and the inner lead 3.
【００１７】その後、インナーリード３を含む内側のパ
ッド２、チップ１４部を樹脂封止し半導体装置１６が製
造される。Thereafter, the semiconductor device 16 is manufactured by sealing the inner pads 2 including the inner leads 3 and the chip 14 with resin.
【００１８】[0018]
【発明の効果】本発明のリードフレームはパッド内にス
リットを設けチップ搭載予定箇所を区切っているので、
チップを所定位置に高精度且つ迅速に搭載できる。また
チップ搭載予定箇所は傾きや反りを生じることなく押し
下げられ、ボンディングワイヤ−の短縮および半導体装
置の薄型化を図れる等の効果がある。According to the lead frame of the present invention, a slit is provided in a pad to separate a portion where a chip is to be mounted.
The chip can be mounted at a predetermined position with high accuracy and speed. Further, the chip mounting portion is pushed down without causing inclination or warpage, which has effects such as shortening of bonding wires and thinning of a semiconductor device.
【図１】本発明の１実施例によるリードフレームを示す
図。FIG. 1 is a view showing a lead frame according to an embodiment of the present invention.
【図２】本発明の１実施例でのパッド部を拡大して示す
図。FIG. 2 is an enlarged view showing a pad portion according to one embodiment of the present invention.
【図３】本発明の１実施例でのチップ搭載予定箇所の押
し下げ加工を示す図。FIG. 3 is a diagram illustrating a pressing process of a chip mounting scheduled portion according to an embodiment of the present invention.
【図４】図２におけるパッドのＸ−Ｘ断面を示す図。FIG. 4 is a diagram showing a section taken along line XX of the pad in FIG. 2;
【図５】本発明のリードフレームを用いた半導体装置を
示す図。FIG. 5 is a diagram showing a semiconductor device using the lead frame of the present invention.
１ リードフレーム ２ パッド ３ インナーリード ４ アウターリード ５ タイバ− ６ サポ−トバ− ７ スリット ８ チップ搭載予定箇所 ９ 途切れ部 １０ パッド部内押し下げ成形加工部 １１ パンチ １２ ダイ １３ サポ−トバ−押し下げ部 １４ チップ １５ ボンディングワイヤ− １６ 半導体装置 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Pad 3 Inner lead 4 Outer lead 5 Tie bar 6 Support bar 7 Slit 8 Chip mounting planned place 9 Break part 10 Pad part press-down forming part 11 Punch 12 Die 13 Support bar press-down part 14 Chip 15 Bonding wire-16 Semiconductor device
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉柳 寿治 福岡県北九州市八幡西区小嶺２丁目10番 １号 株式会社三井ハイテック内 (56)参考文献 特開 平２−84758（ＪＰ，Ａ) 特開 平４−22162（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/50 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toshiharu Yoshiyanagi 2-10-1, Komine, Yawatanishi-ku, Kitakyushu-shi, Fukuoka Mitsui High-Tech Co., Ltd. (56) References JP-A-2-84758 (JP, A) Kaihei 4-22162 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 23/50
Claims (2)
において、パッドのチップ搭載予定箇所を挟さむ４辺に
コ−ナ−の１部を除きスリットが形成されているととも
に、スリット途切れ部が屈曲されチップ搭載予定箇所を
下げたことを特徴とするリードフレーム。In a lead frame in which a part of a pad is lowered, slits are formed on four sides sandwiching a chip mounting portion of the pad except for a part of a corner, and a slit break part is formed. A lead frame characterized by being bent and lowering a portion where a chip is to be mounted.
の製造方法において、パッドのチップ搭載予定箇所を挟
さむ４辺にコ−ナ−の１部を除いてスリットを穿設し、
その後、コ−ナ−のスリット途切れ部を押し下げ加工し
パッド内のチップ搭載予定箇所を下げることを特徴とす
るリードフレームの製造方法。2. A method of manufacturing a lead frame for lowering a part of a pad, wherein slits are formed on four sides of a pad on which a chip is to be mounted, excluding a part of a corner,
Thereafter, a method of manufacturing a lead frame, wherein a portion of the corner where the slit is cut off is pushed down to lower a chip mounting portion in the pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35819092A JP3069621B2 (en) | 1992-12-25 | 1992-12-25 | Lead frame and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35819092A JP3069621B2 (en) | 1992-12-25 | 1992-12-25 | Lead frame and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06196615A JPH06196615A (en) | 1994-07-15 |
| JP3069621B2 true JP3069621B2 (en) | 2000-07-24 |
Family
ID=18458002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35819092A Expired - Fee Related JP3069621B2 (en) | 1992-12-25 | 1992-12-25 | Lead frame and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3069621B2 (en) |
-
1992
- 1992-12-25 JP JP35819092A patent/JP3069621B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06196615A (en) | 1994-07-15 |
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