JP3050059B2 - Multilayer ceramic capacitors - Google Patents
Multilayer ceramic capacitorsInfo
- Publication number
- JP3050059B2 JP3050059B2 JP6243799A JP24379994A JP3050059B2 JP 3050059 B2 JP3050059 B2 JP 3050059B2 JP 6243799 A JP6243799 A JP 6243799A JP 24379994 A JP24379994 A JP 24379994A JP 3050059 B2 JP3050059 B2 JP 3050059B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- capacitor
- multilayer ceramic
- internal
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、積層セラミックコンデ
ンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor.
【０００２】[0002]
【従来の技術】一般に積層セラミックコンデンサは、セ
ラミックグリーンシートならびにセラミックグリーンシ
ート上に内部電極ペーストを印刷したシートを積み重ね
た後、加圧させて積層体とし、次に焼成し、焼結体の両
端部に内部電極と接続される外部電極を設けた構造であ
る。2. Description of the Related Art In general, a multilayer ceramic capacitor is obtained by stacking ceramic green sheets and sheets on which an internal electrode paste is printed on ceramic green sheets, pressurizing to form a laminate, and then firing and sintering both ends of the sintered body. This is a structure in which an external electrode connected to the internal electrode is provided in the portion.
【０００３】中高圧積層セラミックコンデンサ（１ＫＶ
級以上）では、直列式の電極構造を形成し、有効層１層
あたりにかかる電圧を半減させ絶縁破壊を発生しにくく
していた。[0003] Medium to high voltage monolithic ceramic capacitors (1KV
Or higher), a series electrode structure was formed, the voltage applied to each effective layer was reduced by half, and dielectric breakdown was less likely to occur.
【０００４】[0004]
【発明が解決しようとする課題】上記従来の構成では、
高電圧で使用する場合、内部電極の端部に電界が集中し
やすいため、内部電極の端部で絶縁破壊が発生しやすい
という問題点を有していた。In the above-mentioned conventional configuration,
When used at a high voltage, the electric field tends to concentrate on the ends of the internal electrodes, and therefore, there is a problem that dielectric breakdown easily occurs at the ends of the internal electrodes.
【０００５】本発明は、内部電極の端部で発生する絶縁
破壊を防止し、絶縁破壊電圧を向上させた積層セラミッ
クコンデンサを提供することを目的とするものである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer ceramic capacitor in which dielectric breakdown occurring at an end of an internal electrode is prevented and dielectric breakdown voltage is improved.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明は、相対向する端面に至るように２個の第１の
内部電極を形成した第１の誘電体層と、端部に至らない
ように第２の内部電極を形成した誘電体層とを交互に積
層した積層体と、この積層体の端部に外部電極を形成し
たものであり、第１の内部電極は、容量電極と、この容
量電極の幅よりも小さい幅で、前記第１の誘電体層のコ
ーナー部に延長され、前記外部電極に接続された少なく
とも１個の導出電極とからなり、第２の内部電極は、一
対の容量電極と、この容量電極をつなぐとともにこの容
量電極よりも小さい幅の少なくとも１つの導出電極とか
らなるものである。In order to achieve the above object, the present invention provides a first dielectric layer having two first internal electrodes formed so as to reach opposite end faces; A laminate in which dielectric layers on which second internal electrodes are formed alternately so as not to reach, and an external electrode formed at an end of the laminate, wherein the first internal electrode is a capacitor electrode And at least one lead-out electrode having a width smaller than the width of the capacitor electrode and extending to a corner of the first dielectric layer and connected to the external electrode. , A pair of capacitance electrodes, and at least one lead-out electrode connecting the capacitance electrodes and having a width smaller than the capacitance electrodes.
【０００７】[0007]
【作用】この構成によると、内部電極端部への電界集中
が緩和されるため、絶縁破壊電圧が向上する。According to this structure, the electric field concentration on the end of the internal electrode is reduced, so that the dielectric breakdown voltage is improved.
【０００８】[0008]
（実施例１）以下、本発明の第１の実施例について図面
を参照しながら説明する。Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
【０００９】図１，２，３，４には本発明の一実施例に
おける積層セラミックコンデンサの断面図が示されてい
る。この積層セラミックコンデンサの製造方法について
説明する。FIGS. 1, 2, 3 and 4 are sectional views of a multilayer ceramic capacitor according to an embodiment of the present invention. A method for manufacturing the multilayer ceramic capacitor will be described.
【００１０】まず、キャリアフィルム上に誘電体セラミ
ックススラリーをリバースロールコータにより成形し、
乾燥してセラミックグリーンシートを構成した。次に、
セラミックグリーンシートをキャリアフィルムから剥離
し、セラミックグリーンシート上に内部電極用ペースト
をスクリーン印刷により図５に示すパターンＫで印刷乾
燥し、その上に、セラミックグリーンシートを積層し、
このグリーンシート上に、図６に示すパターンＮを用い
て内部電極用ペーストを印刷乾燥した。この工程を繰り
返すことにより積層を行った。このように積層したセラ
ミックグリーンシートの上側および下側に必要に応じて
内部電極用ペーストが印刷されていないセラミックグリ
ーンシートを所定枚数積層した。次に、積層したセラミ
ックグリーンシートをプレスしてお互いに圧着し、積層
体を構成した。次に、この積層体を切断し、バインダア
ウト、焼成を行い、その後、外部電極を塗布、焼き付け
し、Ｎｉメッキ、Ｓｎ−Ｐｂメッキを行い、積層セラミ
ックコンデンサとした。得られた積層セラミックコンデ
ンサは、静電容量１００ｐＦ，Ｑ １２００，ＩＲ１＊
１０13Ωであった。この積層セラミックコンデンサの絶
縁破壊電圧を測定し、その結果を（表１）に示す。First, a dielectric ceramic slurry is formed on a carrier film by a reverse roll coater.
After drying, a ceramic green sheet was formed. next,
The ceramic green sheet is peeled off from the carrier film, the paste for the internal electrode is printed and dried on the ceramic green sheet in a pattern K shown in FIG. 5 by screen printing, and the ceramic green sheet is laminated thereon.
The internal electrode paste was printed and dried on this green sheet using the pattern N shown in FIG. By repeating this process, lamination was performed. On the upper and lower sides of the thus laminated ceramic green sheets, a predetermined number of ceramic green sheets on which the internal electrode paste was not printed were laminated as necessary. Next, the laminated ceramic green sheets were pressed and pressed together to form a laminate. Next, the laminated body was cut, binder-out and firing were performed, and then external electrodes were applied and baked, and Ni plating and Sn-Pb plating were performed to obtain a multilayer ceramic capacitor. The obtained multilayer ceramic capacitor has a capacitance of 100 pF, Q1200, IR1 *.
It was 10 13 Ω. The dielectric breakdown voltage of this multilayer ceramic capacitor was measured, and the results are shown in (Table 1).
【００１１】[0011]
【表１】 [Table 1]
【００１２】（比較例１）まず、キャリアフィルム上に
誘電体セラミックススラリーをリバースロールコータに
より成形、乾燥しセラミックグリーンシートを構成し
た。次に、セラミックグリーンシートをキャリアフィル
ムから剥離し、セラミックグリーンシート上に、内部電
極ペーストをスクリーン印刷により図７に示すパターン
Ｙで印刷乾燥し、その上に、セラミックグリーンシート
を積層し、このグリーンシート上に図７に示すパターン
Ｙを長さ方向にずらし、内部電極ペーストを印刷乾燥し
た。この工程を繰り返すことにより積層を行った。積層
したセラミックグリーンシートはプレスしてお互いに圧
着し、積層体を構成した。以降は実施例１と同様にして
積層セラミックコンデンサを得たが、これが従来例タイ
プとなる。Comparative Example 1 First, a dielectric ceramic slurry was formed on a carrier film by a reverse roll coater and dried to form a ceramic green sheet. Next, the ceramic green sheet is peeled off from the carrier film, the internal electrode paste is printed and dried on the ceramic green sheet in a pattern Y shown in FIG. 7 by screen printing, and a ceramic green sheet is laminated thereon. The pattern Y shown in FIG. 7 was shifted in the length direction on the sheet, and the internal electrode paste was printed and dried. By repeating this process, lamination was performed. The laminated ceramic green sheets were pressed and pressed together to form a laminate. Thereafter, a multilayer ceramic capacitor was obtained in the same manner as in Example 1, but this was the conventional type.
【００１３】得られた積層セラミックコンデンサを用い
て実施例１と同様に絶縁破壊電圧を測定した結果を（表
１）に示す。The results of measuring the dielectric breakdown voltage using the obtained multilayer ceramic capacitor in the same manner as in Example 1 are shown in Table 1.
【００１４】この（表１）から明らかなように、本発明
の積層セラミックコンデンサは絶縁破壊電圧が向上する
ことができる。As apparent from Table 1, the multilayer ceramic capacitor of the present invention can improve the dielectric breakdown voltage.
【００１５】本実施例においては、図１，図２に示す様
に２種類の内部電極２ａ，２ｂを誘電体セラミック層１
を挟んで交互に積層しており、この積層セラミックコン
デンサの図２におけるＡ−Ａの断面図が図３、Ｂ−Ｂの
断面図が図４に示されている。図１に示す導出電極４を
端面と側面とのコーナー部に引き出すことにより、図２
に示す内部電極２ｂの端部から誘電体セラミック層１を
挟んで導出電極４までの電気力線が長くなるので、電界
の集中を従来よりも緩和することができる。In this embodiment, as shown in FIGS. 1 and 2, two types of internal electrodes 2a and 2b are
Are laminated alternately, and FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2 and FIG. 4 is a cross-sectional view taken along the line BB of this multilayer ceramic capacitor. By drawing out the lead-out electrode 4 shown in FIG. 1 to the corner between the end face and the side face, FIG.
Since the lines of electric force from the end of the internal electrode 2b to the lead-out electrode 4 with the dielectric ceramic layer 1 interposed therebetween become longer, the concentration of the electric field can be reduced as compared with the conventional case.
【００１６】なお、本実施例においては、１個の容量電
極５に対し、導出電極４を２個設けたが、外部電極３と
容量電極５との導通が取れ、電界の集中が緩和できれば
その個数はいくらでもよい。本実施例においては、容量
電極５のコーナーに丸みをもたせた構造としたが、これ
も電界集中を起こりにくくするためのものである。In the present embodiment, two lead-out electrodes 4 are provided for one capacitor electrode 5, but if the external electrode 3 and the capacitor electrode 5 can be electrically connected and the concentration of the electric field can be reduced, this is not the case. Any number may be used. In this embodiment, the corners of the capacitor electrode 5 are rounded, but this is also for preventing the electric field concentration from occurring.
【００１７】[0017]
【発明の効果】以上、本発明は内部電極端部への電界集
中を緩和することにより、絶縁破壊電圧が向上するもの
である。As described above, according to the present invention, the dielectric breakdown voltage is improved by alleviating the electric field concentration on the end of the internal electrode.
【図１】本発明の一実施例における積層セラミックコン
デンサの横断面図FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.
【図２】本発明の一実施例における積層セラミックコン
デンサの横断面図FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor according to one embodiment of the present invention.
【図３】本発明の一実施例における積層セラミックコン
デンサのＡ−Ａ断面図FIG. 3 is a sectional view taken along line AA of the multilayer ceramic capacitor in one embodiment of the present invention.
【図４】本発明の一実施例における積層セラミックコン
デンサのＢ−Ｂ断面図FIG. 4 is a sectional view taken along line BB of the multilayer ceramic capacitor in one embodiment of the present invention.
【図５】本発明の一実施例における内部電極を印刷する
ためのスクリーンパターン図FIG. 5 is a screen pattern diagram for printing internal electrodes according to an embodiment of the present invention.
【図６】本発明の一実施例における内部電極を印刷する
ためのスクリーンパターン図FIG. 6 is a screen pattern diagram for printing internal electrodes according to an embodiment of the present invention.
【図７】従来の内部電極を印刷するためのスクリーンパ
ターン図FIG. 7 is a screen pattern diagram for printing a conventional internal electrode.
１ 誘電体セラミック層 ２ａ 内部電極 ２ｂ 内部電極 ３ 外部電極 ４ 導出電極 ５ 容量電極 DESCRIPTION OF SYMBOLS 1 Dielectric ceramic layer 2a Internal electrode 2b Internal electrode 3 External electrode 4 Outgoing electrode 5 Capacitance electrode
フロントページの続き (56)参考文献 特開 昭60−170924（ＪＰ，Ａ) 特開 平１−220421（ＪＰ，Ａ) 実開 昭58−97830（ＪＰ，Ｕ) 実開 昭58−177929（ＪＰ，Ｕ) 実開 昭58−189522（ＪＰ，Ｕ) 実開 平３−39820（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01G 4/00 - 4/42 Continuation of the front page (56) References JP-A-60-170924 (JP, A) JP-A-1-220421 (JP, A) JP-A-58-97830 (JP, U) JP-A-58-177929 (JP) , U) Japanese Utility Model 1983-189522 (JP, U) Japanese Utility Model Application Hei 3-39820 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01G 4/00-4/42
Claims (1)
する端面に設けた第１の誘電体層と、１個の第２の内部
電極を端部に非接触の状態で設けた第２の誘電体層とを
複数枚交互に積層した積層体と、この積層体の前記第１
の内部電極の露出した端面に設けた外部電極とを備え、
前記第１の内部電極は、それぞれ容量電極と、この容量
電極の幅よりも小さい幅で、前記第１の誘電体層のコー
ナー部に延長されて、前記外部電極に接続された少なく
とも１個の導出電極とからなり、前記第２の電極は、一
対の容量電極とこの容量電極同士を接続するとともにこ
の容量電極の幅よりも小さい幅の少なくとも１つの導出
電極とからなる積層セラミックコンデンサ。1. A first dielectric layer having two first internal electrodes provided on opposite end faces, and a second dielectric layer having one second internal electrode provided at an end in a non-contact state. A laminate in which a plurality of dielectric layers are alternately laminated with each other;
An external electrode provided on the exposed end face of the internal electrode,
The first internal electrodes each include a capacitor electrode and at least one capacitor electrode having a width smaller than the width of the capacitor electrode and extending to a corner of the first dielectric layer and connected to the external electrode. A multilayer ceramic capacitor comprising a lead-out electrode, wherein the second electrode comprises a pair of capacitor electrodes and at least one lead-out electrode having a width smaller than the width of the capacitor electrode and connecting the capacitor electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6243799A JP3050059B2 (en) | 1994-10-07 | 1994-10-07 | Multilayer ceramic capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6243799A JP3050059B2 (en) | 1994-10-07 | 1994-10-07 | Multilayer ceramic capacitors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08111343A JPH08111343A (en) | 1996-04-30 |
| JP3050059B2 true JP3050059B2 (en) | 2000-06-05 |
Family
ID=17109124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6243799A Expired - Fee Related JP3050059B2 (en) | 1994-10-07 | 1994-10-07 | Multilayer ceramic capacitors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3050059B2 (en) |
-
1994
- 1994-10-07 JP JP6243799A patent/JP3050059B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08111343A (en) | 1996-04-30 |
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