JP3044053B2 - Method of forming semiconductor device and method of arranging external terminals of semiconductor chip - Google Patents

Method of forming semiconductor device and method of arranging external terminals of semiconductor chip

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Publication number
JP3044053B2
JP3044053B2 JP20084790A JP20084790A JP3044053B2 JP 3044053 B2 JP3044053 B2 JP 3044053B2 JP 20084790 A JP20084790 A JP 20084790A JP 20084790 A JP20084790 A JP 20084790A JP 3044053 B2 JP3044053 B2 JP 3044053B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
external terminals
semiconductor device
wires
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP20084790A
Other languages
Japanese (ja)
Other versions
JPH0485947A (en
Inventor
彰信 渡邊
俊恭 秋山
義弘 野中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20084790A priority Critical patent/JP3044053B2/en
Publication of JPH0485947A publication Critical patent/JPH0485947A/en
Application granted granted Critical
Publication of JP3044053B2 publication Critical patent/JP3044053B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H01L2224/49173—Radial fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49177—Combinations of different arrangements
    • H01L2224/49179—Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に、自動配置配線シ
ステム（Design Automation）及びこれにより開発や設
計が支援された半導体装置に適用して有効な技術に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] relates to a semiconductor device, in particular, automatic placement and routing system (D esign A utomation) and thereby applied to a semiconductor device which is assisted by the development and design It is about effective technology.

〔従来の技術〕[Conventional technology]

ゲートアレイ方式、スタンダードセル方式等の方式で
開発や設計がなされた所謂特定用途向けIC（Applicatio
n Specific IC）の需要が高い。この種のICの開発や設
計に際しては開発期間を短縮するためにDAの支援が不可
欠である。So-called application-specific ICs ( A pplicatio) that have been developed and designed using the gate array method, standard cell method, etc.
n S pecific IC) of high demand. When developing or designing this type of IC, DA support is essential to shorten the development period.

前記ICは、QFP構造、PLCC構造、PGA構造等の構造を採
用するパッケージ内に封止され、半導体装置として構成
される。ICは平面方形状の単結晶珪素からなる所謂半導
体チップで構成される。この半導体チップの中央部分に
は前記DAで自動的に設計された回路システム例えば論理
回路システムが搭載される。半導体チップの周囲には前
記回路システムに入出力段回路を介在して接続される複
数個の外部端子（ボンディングパッド）が配列される。
入出力段回路、外部端子の夫々は、回路システムと同様
にDAで自動的に配置される。入出力段回路は、予じめ基
本設計がなされたセル（入出力段回路セル）をDAで自動
的に配列するので、隣接する入出力段回路間の間隔は他
の入出力段回路間の間隔と実質的に同一で形成される。
同様に、外部端子は、予じめ基本設計がなされたセル
（外部端子セル）をDAで自動的に配列するので、隣接す
る外部端子間の間隔は他の外部端子間の間隔と実質的に
同一で形成される。The IC is sealed in a package adopting a structure such as a QFP structure, a PLCC structure, and a PGA structure, and is configured as a semiconductor device. The IC is constituted by a so-called semiconductor chip made of single-crystal silicon having a square planar shape. A circuit system automatically designed by the DA, for example, a logic circuit system is mounted on a central portion of the semiconductor chip. A plurality of external terminals (bonding pads) connected to the circuit system via an input / output stage circuit are arranged around the semiconductor chip.
Each of the input / output stage circuit and the external terminal is automatically arranged by DA similarly to the circuit system. The input / output stage circuit automatically arranges the cells (input / output stage circuit cells) for which the basic design was made in advance by DA, so the space between adjacent input / output stage circuits is It is formed substantially the same as the interval.
Similarly, the external terminals automatically arrange cells (external terminal cells) that have been designed in advance by DA, so that the distance between adjacent external terminals is substantially equal to the distance between other external terminals. The same is formed.

例えば、QFP構造を採用するパッケージは、中央部分
に前記半導体チップを配置し、この半導体チップの外周
囲に複数本のインナーリードを配列する。半導体チップ
の周辺に配置された外部端子、その外周囲に配置された
インナーリードの夫々はボンディングワイヤを介して電
気的に接続される。パッケージの一般的な設計は半導体
チップの中心からの放射線上にインナーリードを配置す
る手法を採用する。この設計手法は、半導体チップの小
さい間隔で配列された外部端子から大きい間隔で配列さ
れたアウターリードまでの間において無駄な空領域を極
力低減でき、レイアウト効率を高められる。この種の設
計手法はファインピッチ化が要求される数百本程度のア
ウターリード本数を有するパッケージに特に採用され
る。QFP構造を採用するパッケージ本体はトアンスファ
モールド法で成型された樹脂で形成される。パッケージ
内には半導体チップ、インナーリード及びボンディング
ワイヤの夫々が配置され、これらは気密封止される。For example, in a package adopting the QFP structure, the semiconductor chip is arranged at a central portion, and a plurality of inner leads are arranged around the semiconductor chip. The external terminals arranged around the semiconductor chip and the inner leads arranged around the outside are electrically connected via bonding wires. The general design of a package employs a method of arranging inner leads on radiation from the center of a semiconductor chip. According to this design method, useless empty areas can be reduced as much as possible from the external terminals arranged at small intervals to the outer leads arranged at large intervals on the semiconductor chip, and the layout efficiency can be improved. This type of design method is particularly adopted for a package having about several hundred outer leads which requires a fine pitch. The package body adopting the QFP structure is formed of resin molded by the transfer molding method. Each of the semiconductor chip, the inner leads and the bonding wires is arranged in the package, and these are hermetically sealed.

このように構成される、QFP構造を採用するパッケー
ジが使用される半導体装置は、前述のように数百本程度
の多ピン化が進むと、ボンディングワイヤ間の短絡が多
発する。このような短絡はワイヤ相互の間隔が小さい部
分にて多く発生し、通常のボンディングでは半導体チッ
プからリードに向かってワイヤが放射状に形成されるの
で、半導体チップの外部端子部分にて相互のワイヤの間
隔が最も小さくなっている。即ち、半導体チップの中心
点から外部端子の接続部を結んだ放射状の線の外延によ
ってボンディングワイヤを近似した場合に、隣接するワ
イヤ相互の間隔がとる最小値は、隣接する外部端子の接
続部からこの外延線におろした垂線の長さによって近似
することができる（以下、これを最小間隔という）。こ
のボンディングワイヤ間の間隔は、外部端子の配列方向
と前記放射線とが交差してなす角度が直角に近づくにつ
れ大きくなり、直角から離れるにつれて小さくなる。つ
まり、半導体チップの辺の中央部分に配列された外部端
子に接続されるボンディングワイヤ間の間隔が最大とな
り、半導体チップの角部に配列された外部端子に接続さ
れるボンディングワイヤ間の間隔が最小となる。このた
め、前述のボンディングワイヤ間の短絡は、半導体チッ
プの角部に配列された外部端子に接続されるボンディン
グワイヤ間で多発する。As described above, in a semiconductor device using a package adopting the QFP structure configured as described above, as the number of pins increases to about several hundred, short-circuiting between bonding wires frequently occurs. Such short-circuits often occur in portions where the distance between the wires is small, and in normal bonding, the wires are formed radially from the semiconductor chip toward the leads. The interval is the smallest. That is, when the bonding wire is approximated by the extension of a radial line connecting the connection part of the external terminal from the center point of the semiconductor chip, the minimum value of the interval between adjacent wires is determined by the connection part of the adjacent external terminal. The distance can be approximated by the length of the perpendicular drawn to the outer extension (hereinafter, this is referred to as a minimum interval). The distance between the bonding wires increases as the angle between the direction in which the external terminals are arranged and the radiation intersects approaches a right angle, and decreases as the distance from the right angle increases. That is, the interval between the bonding wires connected to the external terminals arranged at the center of the side of the semiconductor chip is the largest, and the interval between the bonding wires connected to the external terminals arranged at the corners of the semiconductor chip is the smallest. Becomes For this reason, the short circuit between the bonding wires described above frequently occurs between the bonding wires connected to the external terminals arranged at the corners of the semiconductor chip.

この種の技術課題を解決する技術としては、特開昭60
−46041号公報に開示された技術が有効である。この公
報に開示された技術は、半導体チップの中央部分に配列
される外部端子間の間隔を密にし、角部分に配列される
外部端子間の間隔を疎にする。すなわち、前記公報に開
示された技術は、半導体チップの辺の角部分のボンディ
ングワイヤ間の間隔を広げ、ボンディングワイヤ間の短
絡を防止できる。As a technique for solving this kind of technical problem, Japanese Unexamined Patent Publication No.
The technique disclosed in -46041 is effective. According to the technique disclosed in this publication, the interval between external terminals arranged in a central portion of a semiconductor chip is made small, and the interval between external terminals arranged in a corner portion is made small. In other words, the technique disclosed in the above publication increases the distance between the bonding wires at the corners of the sides of the semiconductor chip, and can prevent a short circuit between the bonding wires.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、本発明者は、前述の公報に開示された
技術について、以下の問題点を見出した。However, the present inventors have found the following problems with the technology disclosed in the above-mentioned publication.

前記半導体装置の半導体チップに配列された外部端子
は、DAの支援による開発中或は設計中において、DAによ
る自動処理を中断し又はその終了後に作業者がDAを操作
する所謂人手作業（人為的作業）に基づいて疎密に変更
される。このため、半導体装置の開発工数或は設計工数
に人手作業が付加されるだけでなく、人手作業はDAによ
る自動処理に比べて長時間を要するので、半導体装置の
開発期間が増大する。The external terminals arranged on the semiconductor chip of the semiconductor device are so-called manual operations (artificial work) in which the automatic processing by the DA is interrupted during the development or design with the support of the DA or the operator operates the DA after the termination. Changes) based on the work). For this reason, not only manual work is added to the development man-hour or design man-hour of the semiconductor device, but also the manual work requires a longer time than the automatic processing by the DA, so that the development period of the semiconductor device is increased.

また、前記半導体装置の開発に人手作業が付加される
と、人為的なミスを誘発し易く、半導体装置の信頼性が
低下する。Further, if manual work is added to the development of the semiconductor device, a human error is likely to be caused, and the reliability of the semiconductor device is reduced.

また、前記半導体装置のボンディングワイヤ間の間隔
は半導体チップの辺の角部において広がるが、すべての
ボンディングワイヤ間の間隔については配慮されておら
ず、ボンディングワイヤ間の間隔にばらつきがある。こ
のため、半導体チップの辺の限定された領域内におい
て、角部のボンディングワイヤ間の間隔を広げた場合、
逆に中央部分のボンディングワイヤ間の間隔が狭くな
り、この領域でボンディングワイヤ間に短絡が生じる。Further, the spacing between the bonding wires of the semiconductor device widens at the corners of the sides of the semiconductor chip, but the spacing between all the bonding wires is not considered, and the spacing between the bonding wires varies. For this reason, when the interval between the bonding wires at the corners is increased in a limited area of the side of the semiconductor chip,
Conversely, the distance between the bonding wires in the central portion is reduced, and a short circuit occurs between the bonding wires in this region.

本発明の目的は、DAによる開発や設計が支援される半
導体装置において、ワイヤ間の短絡を低減し、電気的信
頼性を向上することが可能な技術を提供することにあ
る。An object of the present invention is to provide a technique capable of reducing a short circuit between wires and improving electrical reliability in a semiconductor device whose development and design are supported by DA.

本発明の他の目的は、DAにより開発や設計が支援され
る半導体装置において、開発期間を短縮することが可能
な技術を提供することにある。Another object of the present invention is to provide a technique capable of shortening a development period in a semiconductor device whose development and design are supported by DA.

本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述及び添付図面によって明らかになるであ
ろう。The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

〔課題を解決するための手段〕[Means for solving the problem]

本願において開示される発明のうち、代表的なものの
概要を簡単に説明すれば、下記のとおりである。The outline of a typical invention disclosed in the present application is briefly described as follows.

（１）平面方形状の半導体チップの外周囲に、半導体チ
ップの中心からの放射線上にボンディング領域が設けら
れたリードを配列し、これらのリードのボンディング領
域と前記半導体チップの周辺に沿って配列された外部端
子の夫々をワイヤで接続する半導体装置の形成方法にお
いて、前記半導体チップのサイズ及び外部端子の数を含
む配置情報から、外部端子の間隔を均一とした場合のボ
ンディングワイヤ相互の最小間隔の平均値を求める段階
と、このワイヤ間の最小間隔の平均値に基づき、外部端
子に接続されるワイヤとそれに隣接する他のワイヤ相互
の間隔を均一化して外部端子を配列する段階とを備え
る。(1) Leads having bonding regions provided on the outer periphery of a semiconductor chip having a planar rectangular shape on the radiation from the center of the semiconductor chip are arranged, and are arranged along the bonding regions of these leads and the periphery of the semiconductor chip. In the method for forming a semiconductor device in which each of the external terminals is connected by a wire, the minimum distance between the bonding wires when the distance between the external terminals is made uniform from the arrangement information including the size of the semiconductor chip and the number of the external terminals. And arranging the external terminals by equalizing the distance between the wire connected to the external terminal and other wires adjacent thereto based on the average value of the minimum distance between the wires. .

（２）平面方形状の半導体チップの外周囲に、半導体チ
ップの中心からの放射線上にボンディング領域が設けら
れたリードを配列し、これらのリードのボンディング領
域と、前記半導体チップの周辺に沿って配列された外部
端子の夫々をワイヤで接続する半導体装置に使用される
前記半導体チップの外部端子の配置方法であって、前記
半導体チップの各辺に外部端子を等間隔に配置した場合
のチップサイズを見積もる工程と、前記チップサイズの
算出結果、外部端子数の情報に基づき、隣接するワイヤ
間の間隔の平均値を算出し、各ワイヤが前記半導体チッ
プの中心からの放射線上に張られたと仮定した場合に各
ワイヤ間の間隔が実質的に同一となるように、前記半導
体チップの外部端子を、辺の中央部から角部に向かって
前記平均値より順次広くなる間隔で配置しなおす工程と
を備える。(2) Leads having bonding regions provided on the outer periphery of the semiconductor chip having a planar rectangular shape on the radiation from the center of the semiconductor chip are arranged, and the bonding regions of these leads and the periphery of the semiconductor chip are arranged. A method of arranging external terminals of a semiconductor chip used in a semiconductor device in which each of arranged external terminals is connected by a wire, wherein a chip size when external terminals are arranged at equal intervals on each side of the semiconductor chip And calculating the chip size, calculating the average value of the spacing between adjacent wires based on the information on the number of external terminals, and assuming that each wire is placed on the radiation from the center of the semiconductor chip. In this case, the external terminals of the semiconductor chip are arranged in order from the average value from the center of the side to the corner so that the spacing between the wires becomes substantially the same. And a re-arranged at widens interval step.

〔作用〕[Action]

上述した手段によれば、前記自動配置配線システムを
使用し、半導体チップのサイズの算出結果、外部端子数
の夫々の情報から自動的に隣接する外部端子間の間隔を
変更し、自動的に隣接するワイヤ間の最小間隔をこれ以
外のワイヤ間の最小間隔と実質的に同一に設定できるの
で、人手作業を廃止し、半導体装置の開発期間を短縮で
きる。また、人手作業に基づく人為的なミスをなくした
ので、半導体装置の開発における信頼性を向上できる。According to the above-described means, the interval between the adjacent external terminals is automatically changed from the calculation result of the size of the semiconductor chip and the respective information of the number of external terminals by using the automatic placement and routing system, so that the automatic Since the minimum distance between the wires to be formed can be set to be substantially the same as the minimum distance between the other wires, manual work can be eliminated and the development period of the semiconductor device can be shortened. In addition, since human errors due to manual work are eliminated, reliability in the development of a semiconductor device can be improved.

以下、本発明の構成について、DAの支援で開発或は設
計された半導体チップをQFP構造を採用するパッケージ
に封止した半導体装置に本発明を適用した一実施例とと
もに説明する。Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor device in which a semiconductor chip developed or designed with the support of a DA is sealed in a package adopting a QFP structure.

なお、実施例を説明するための全図において、同一機
能を有するものは同一符号を付け、その繰り返しの説明
は省略する。In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

〔発明の実施例〕(Example of the invention)

本発明の一実施例であるQFP構造を採用するパッケー
ジで構成された半導体装置の構造を第１図（要部平面
図）及び第２図（断面図）で示す。1 (a plan view of a main part) and FIG. 2 (a cross-sectional view) show a structure of a semiconductor device constituted by a package adopting a QFP structure according to an embodiment of the present invention.

第２図に示すように、QFP構造のパッケージで構成さ
れる半導体装置１は半導体チップ（IC）２を樹脂６で気
密封止する。半導体チップ２はタブ3A上に接着層４を介
在し搭載される。接着層４としては例えばAgペースト或
はAu−Si共晶合金が使用される。As shown in FIG. 2, in a semiconductor device 1 composed of a package having a QFP structure, a semiconductor chip (IC) 2 is hermetically sealed with a resin 6. The semiconductor chip 2 is mounted on the tab 3A with an adhesive layer 4 interposed. As the bonding layer 4, for example, an Ag paste or an Au-Si eutectic alloy is used.

前記半導体チップ２は、第１図及び第２図に示すよう
に、平面方形状（本実施例ではほぼ正方形）の単結晶珪
素で形成される。半導体チップ２の中央部分には回路シ
ステム23が搭載される。本実施例において、回路システ
ム23は論理回路システム及びその周囲に配列された入出
力段回路（入出力バッファ回路）で構成される。また、
回路システム23は論理回路システム及び記憶回路システ
ムを混在してもよい。半導体チップ２の平面方形状の各
辺に沿った周辺には複数個の外部端子（ボンディングパ
ッド）21が配列される。外部端子21は、平面形状が実質
的に方形状で構成され、回路システム23の入出力段回路
を介して論理回路システムに接続される。外部端子21
は、論理回路システム、入出力段回路の夫々を結線する
例えば２、３又は４層構造の配線層のうちの最上層の配
線層と同一層で形成される。この外部端子21の配列につ
いては、インナーリード（3B）との相関々係があるの
で、後に詳述する。前記各配線層の配線は例えばアルミ
ニウムにSi、又はSi及びCuが添加されたアルミニウム合
金膜で形成される。各配線層の間、最上層の配線層上の
夫々にはパッシベーション膜22が構成される。As shown in FIGS. 1 and 2, the semiconductor chip 2 is formed of single-crystal silicon having a square planar shape (substantially square in this embodiment). A circuit system 23 is mounted on a central portion of the semiconductor chip 2. In this embodiment, the circuit system 23 includes a logic circuit system and input / output stage circuits (input / output buffer circuits) arranged around the logic circuit system. Also,
The circuit system 23 may include both a logic circuit system and a storage circuit system. A plurality of external terminals (bonding pads) 21 are arranged around the semiconductor chip 2 along each side of the planar square. The external terminal 21 has a substantially square planar shape, and is connected to the logic circuit system via the input / output stage circuit of the circuit system 23. External terminal 21
Are formed in the same layer as the uppermost wiring layer of the wiring layers having a two-, three-, or four-layer structure for connecting the logic circuit system and the input / output stage circuit, for example. The arrangement of the external terminals 21 has a correlation with the inner leads (3B), and will be described later in detail. The wiring of each wiring layer is formed of, for example, an aluminum alloy film obtained by adding Si or Si and Cu to aluminum. Between each wiring layer, a passivation film 22 is formed on each of the uppermost wiring layers.

前記半導体チップ21の外周囲には、第１図及び第２図
に示すように、複数本のインナーリード3Bが配列され
る。インナーリード3Bは、第１図に示すように、半導体
チップ21の中心点Ｏからの放射線（同第１図中、一点鎖
線で示す）上に配置される。前記放射線上にインナーリ
ード3Bを配置する手法は、半導体チップ２、アウターリ
ード3Cの夫々の間において、無駄な空領域を極力低減で
き、レイアウト効率を高めることができる。前記放射線
上には少なくともインナーリード3Bの半導体チップ２側
のボンディング領域が配置されていればよい。前記イン
ナーリード3Bのボンディング領域と反対側にはアウター
リード3Cが一体に構成される（電気的に接続される）。
前記タブ3A（図示しないがタブ吊りリードを含む）、イ
ンナーリード3B、アウターリード3Cの夫々は同一のリー
ドフレームから切断及び成型されたものである。このリ
ードフレームは例えばFe−Ni合金、Cu系合金等の金属材
料で構成される。A plurality of inner leads 3B are arranged around the outer periphery of the semiconductor chip 21, as shown in FIGS. As shown in FIG. 1, the inner leads 3B are arranged on radiation (indicated by a dashed line in FIG. 1) from a center point O of the semiconductor chip 21. The method of arranging the inner leads 3B on the radiation can minimize wasteful empty areas between the semiconductor chip 2 and the outer leads 3C, and can improve layout efficiency. It is sufficient that at least the bonding region of the inner lead 3B on the semiconductor chip 2 side is arranged on the radiation. An outer lead 3C is integrally formed (electrically connected) on the side of the inner lead 3B opposite to the bonding area.
The tab 3A (not shown, including a tab suspension lead), the inner lead 3B, and the outer lead 3C are each cut and molded from the same lead frame. The lead frame is made of, for example, a metal material such as an Fe-Ni alloy or a Cu-based alloy.

前記半導体チップ２の外部端子21、インナーリード3B
のボンディング領域の夫々はボンディングワイヤ５を介
して電気的に接続される。ボンディングワイヤ５は、例
えばAuワイヤ、Cuワイヤ又はAlワイヤが使用され、熱圧
着に超音波振動を併用したボンディング方法によりボン
ディングされる。External terminals 21 of the semiconductor chip 2, inner leads 3B
Are electrically connected via bonding wires 5. As the bonding wire 5, for example, an Au wire, a Cu wire, or an Al wire is used, and the bonding is performed by a bonding method using ultrasonic vibration in combination with thermocompression bonding.

このボンディングワイヤ５とその配列方向に隣接する
他のボンディングワイヤ５との間の最小間隔（最小離隔
寸法）ｈは、前者のボンディングワイヤ５の外部端子21
との接続部（ボンディング部分）と、他方の後者のボン
ディングワイヤ５の前記接続部から前者のボンディング
ワイヤ５に対して直角をなす線上に存在する部分との間
の間隔である。この隣接するボンディングワイヤ５間の
最小間隔ｈはいずれのボンディングワイヤ５間において
も実質的に同一に構成される（均一化される）。The minimum distance (minimum separation dimension) h between the bonding wire 5 and another bonding wire 5 adjacent in the arrangement direction is the external terminal 21 of the former bonding wire 5.
Is a distance between the connection portion (bonding portion) and the portion of the other bonding wire 5 on the line perpendicular to the connection portion from the connection portion of the latter bonding wire 5. The minimum distance h between the adjacent bonding wires 5 is substantially the same (uniform) between any of the bonding wires 5.

このように、隣接するボンディングワイヤ５間の最小
間隔ｈの均一化は、同第１図に示すように、半導体チッ
プ２の辺の中央部から角部に向って、半導体チップ２の
外部端子21の配列方向に隣接する外部端子21間の間隔を
順次広げることで達成できる。具体的には、半導体チッ
プ２の中心点Ｏから辺の中心を通過する中心線Ｏ−OH上
又はそれに最っとも近接した位置に配置された外部端子
21（１）と半導体チップ２の角部に向って配置された次
段の外部端子21（２）との間の間隔（配列ピッチ）ｘ
（１）に対して、半導体チップ２の角部に近い外部端子
21（ｉ）とそれよりも角部側の次段の外部端子21（ｉ＋
１）との間の間隔ｘ（ｉ）が広く構成される。外部端子
21（２）乃至外部端子21（ｉ）までの間において、各外
部端子21間の間隔は、半導体チップ２の辺の中心から角
部に向って順次広く構成される。このボンディングワイ
ヤ５間の最小間隔ｈを均一化するための半導体チップ２
の外部端子21の配列は、後に詳述するが、DAで自動的に
行われる。In this manner, the uniformization of the minimum distance h between the adjacent bonding wires 5 is achieved by, as shown in FIG. 1, the external terminals 21 of the semiconductor chip 2 from the center to the corner of the side of the semiconductor chip 2. Can be achieved by sequentially increasing the interval between the external terminals 21 adjacent in the arrangement direction. Specifically, an external terminal disposed on or closest to a center line O-OH passing through the center of the side from the center point O of the semiconductor chip 2
The interval (arrangement pitch) x between the terminal 21 (1) and the next-stage external terminal 21 (2) arranged toward the corner of the semiconductor chip 2
External terminals near the corners of the semiconductor chip 2 with respect to (1)
21 (i) and the external terminal 21 (i +
1) is widely configured. External terminal
From 21 (2) to the external terminal 21 (i), the interval between the external terminals 21 is sequentially widened from the center of the side of the semiconductor chip 2 to the corner. The semiconductor chip 2 for equalizing the minimum distance h between the bonding wires 5
The arrangement of the external terminals 21 is automatically performed by the DA, as described later in detail.

前記半導体チップ２、タブ3A、インナーリード3B及び
ボンディングワイヤ５は樹脂６で気密封止される。樹脂
６は、トランスファモールド法で形成され、例えばフェ
ノール硬化型のエポキシ系樹脂で形成される。The semiconductor chip 2, the tab 3A, the inner lead 3B, and the bonding wire 5 are hermetically sealed with a resin 6. The resin 6 is formed by a transfer molding method, and is formed of, for example, a phenol-curable epoxy resin.

次に、前述の半導体装置１のQFP構造を採用するパッ
ケージに封止された半導体チップ２の形成方法につい
て、第３図（DAで取り扱うための計算モデル図）、第４
図（形成方法全体のプロセスフロー図）及び第５図（形
成方法の一部のプロセスフロー図）を使用し、簡単に説
明する。Next, a method of forming the semiconductor chip 2 sealed in a package adopting the QFP structure of the semiconductor device 1 will be described with reference to FIG. 3 (a calculation model diagram for handling by DA) and FIG.
A brief description will be given with reference to FIG. 5 (process flow diagram of the entire forming method) and FIG. 5 (process flow diagram of a part of the forming method).

まず、半導体チップ２に搭載する回路システムの論理
設計を行い、論理回路図を作成する。First, a logic design of a circuit system mounted on the semiconductor chip 2 is performed, and a logic circuit diagram is created.

次に、第４図に示すように、前述論理回路図に基づ
き、DAで取り扱える論理回路情報として、この論理回路
情報をDAに入力し、DAでの自動化処理を開始する＜11
＞。Next, as shown in FIG. 4, based on the above-described logic circuit diagram, the logic circuit information is input to the DA as logic circuit information that can be handled by the DA, and the automation processing by the DA is started. <11
>.

次に、前記論理回路情報に基づき、DAのメモリ空間内
に仮想的に設定された半導体チップ（２）の領域上に回
路システム（23）の論理回路システム及び入出力段回路
をDAで自動的に配置すると共に、前記入出力段回路を介
して論理回路システムに接続される外部端子（21）をDA
で自動的に配置する＜12＞。この処理工程において配置
される外部端子は、その配列方向に隣接する外部端子間
の間隔がすべての領域において実質的に同一で配置され
る（均等に配置される）。Next, based on the logic circuit information, the DA automatically places the logic circuit system and the input / output stage circuit of the circuit system (23) on the area of the semiconductor chip (2) virtually set in the memory space of the DA. And an external terminal (21) connected to a logic circuit system via the input / output stage circuit is connected to DA.
<12> to place automatically. The external terminals arranged in this processing step are arranged so that the intervals between adjacent external terminals in the arrangement direction are substantially the same in all regions (evenly arranged).

次に、前記論理回路システムの各論理回路間、外部端
子と入出力段回路との間、入出力段回路と論理回路との
間等を接続する結線をDAで自動的に配置する＜13＞。Next, connections between the respective logic circuits of the logic circuit system, between the external terminals and the input / output stage circuits, between the input / output stage circuits and the logic circuits, etc. are automatically arranged by the DA <13>. .

次に、前記回路システム及び外部端子が配置され、し
かも結線が配置された半導体チップに基づき、この半導
体チップのサイズを算出する＜14＞。この半導体チップ
のサイズ情報としては、前記第１図に示す少なくとも以
下の情報を算出する。Next, based on the semiconductor chip on which the circuit system and the external terminals are arranged and the connection is arranged, the size of the semiconductor chip is calculated <14>. As the size information of the semiconductor chip, at least the following information shown in FIG. 1 is calculated.

1.情報a:中心線Ｏ−OH上における半導体チップの中心点
Ｏから外部端子の配列位置の中心までの距離。1. Information a: distance from the center point O of the semiconductor chip on the center line O-OH to the center of the arrangement position of the external terminals.

2.情報b:中心点Ｏから半導体チップの最っとも角部に配
置された外部端子の配列位置の中心までの距離。2. Information b: distance from the center point O to the center of the arrangement position of the external terminals arranged at the corners of the semiconductor chip.

3.情報c:中心線Ｏ−OHから半導体チップの最っとも角部
に配置された外部端子の配列位置の中心までの距離（外
部端子列の長さ）。3. Information c: the distance from the center line O-OH to the center of the arrangement position of the external terminals arranged at the corners of the semiconductor chip (the length of the external terminal row).

4.情報L:中心線Ｏ−OHからそれに最っとも近い位置に配
置された外部端子までの距離。4. Information L: The distance from the center line O-OH to the external terminal located closest to it.

5.情報n:中心線Ｏ−OHから半導体チップの角部までに配
置された外部端子数。5. Information n: the number of external terminals arranged from the center line O-OH to the corner of the semiconductor chip.

次に、第４図に示すように、前記半導体チップのサイ
ズ情報に基づき、予じめ外部端子間の間隔が均等に配置
された外部端子の配置位置を変更し（半導体チップの角
部に近づくにつれ外部端子間の間隔を広くし）、前記第
１図に示すように、隣接するボンディングワイヤ（５）
間の最小間隔ｈをすべて均一化する＜15＞。このボンデ
ィングワイヤ間の最小間隔ｈを均一化する処理は、第５
図に示すプロセスフローにしたがい、DAで自動的に行わ
れる。Next, as shown in FIG. 4, based on the size information of the semiconductor chip, the arrangement positions of the external terminals in which the intervals between the external terminals are uniformly arranged are changed in advance (to approach the corners of the semiconductor chip). As shown in FIG. 1, the distance between the external terminals is increased.
The minimum interval h between them is all uniformed <15>. The process of equalizing the minimum distance h between the bonding wires is performed in the fifth step.
This is automatically performed by DA according to the process flow shown in the figure.

まず、前記半導体チップのサイズ情報に基づき、DAで
の自動化処理を開始する＜151＞。初めに、前記ボンデ
ィングワイヤ間の最小間隔ｈの下限値（min）を０に設
定し、上限値（max）を情報ｃ及び情報ｎの除算により
設定する＜152＞。この上限値及び下限値に基づき、ボ
ンディングワイヤ間の最小間隔ｈの平均値を算出する＜
153＞。First, based on the size information of the semiconductor chip, the automatic processing by the DA is started <151>. First, the lower limit (min) of the minimum distance h between the bonding wires is set to 0, and the upper limit (max) is set by dividing the information c and the information n <152>. An average value of the minimum distance h between the bonding wires is calculated based on the upper limit value and the lower limit value.
153>.

次に、前記サイズ情報の情報ｎに基づき、半導体チッ
プの一辺に配置された外部端子数を判定する＜154＞。
外部端子数が奇数の場合（つまり、中心線Ｏ−OH上に外
部端子が配置される場合）、情報Ｌは０に設定される＜
155＞。外部端子数が偶数の場合（第１図及び第３図に
示すように、半導体ペレットの辺の中心部に配置された
外部端子間を中心線Ｏ−OHが通過する場合）、情報Ｌは
前記最小間隔ｈの２分の１に設定される＜156＞。Next, the number of external terminals arranged on one side of the semiconductor chip is determined based on the information n of the size information <154>.
When the number of external terminals is odd (that is, when the external terminals are arranged on the center line O-OH), the information L is set to 0 <
155>. When the number of external terminals is an even number (as shown in FIGS. 1 and 3, when the center line O-OH passes between the external terminals arranged at the center of the side of the semiconductor pellet), the information L is <156> set to one half of the minimum interval h.

次に、半導体チップの外部端子間を計算するために、
計算プログラムのループの変数ｉを０に設定し、総和ｙ
（０）＝Ｌを設定し、最初に計算される外部端子の位置
決めを行う＜157＞。外部端子間の間隔ｘ（ｉ）は中心
線Ｏ−OH上（奇数の場合）又は中心線Ｏ−OHに最っとも
近い（偶数の場合）外部端子から数えてｉ番目とｉ＋１
番目の外部端子間の距離を表す。総和ｙ（ｉ）は前記ｉ
番目までの間隔ｘ（ｉ）の合計を表す。ただし、ｙ
（０）は、中心線Ｏ−OHから第１番目の外部端子までの
距離を表している。Next, in order to calculate the distance between the external terminals of the semiconductor chip,
The variable i of the loop of the calculation program is set to 0, and the sum y
(0) = L is set, and positioning of the external terminal calculated first is performed <157>. The interval x (i) between the external terminals is the i-th and i + 1 counting from the external terminal on the center line O-OH (in the case of an odd number) or closest to the center line O-OH (in the case of an even number).
Represents the distance between external terminals. The sum y (i) is the i
Represents the sum of the intervals x (i) up to the th. Where y
(0) represents the distance from the center line O-OH to the first external terminal.

次に、配列されたすべての外部端子間の間隔ｘ（ｉ）
を計算するために、ループ変数ｉ＝ｉ＋１を設定し＜15
8＞、半導体チップの辺の中心部から角部に向って配列
された各外部端子間の間隔ｘ（ｉ）を算出する＜159
＞。外部端子間の間隔ｘ（ｉ）は、第３図に示すよう
に、三角形の相似の原理を利用し、以下の式から算出で
きる。Next, the interval x (i) between all the arranged external terminals
Is set to set the loop variable i = i + 1 <15
8> calculating the distance x (i) between the external terminals arranged from the center of the side of the semiconductor chip toward the corner <159
>. As shown in FIG. 3, the interval x (i) between the external terminals can be calculated from the following equation using the similarity principle of a triangle.

間隔ｘ（ｉ）：最小間隔ｈ＝情報b:情報ａ 次に、算出された外部端子の間隔ｘ（ｉ）の総和ｙ
（ｉ）を算出する＜160＞。Interval x (i): minimum interval h = information b: information a Next, the sum y of the calculated external terminal intervals x (i)
(I) is calculated <160>.

この外部端子間の間隔ｘ（ｉ）及び間隔ｘ（ｉ）の総
和ｙ（ｉ）の算出は、半導体チップの辺の中心部に配置
された外部端子から最っとも角部に配置された外部端子
の手前まで（情報ｎ−１まで）繰返し行われる＜161
＞。The calculation of the distance x (i) between the external terminals and the sum y (i) of the distances x (i) is based on the external terminals disposed at the center of the side of the semiconductor chip and the external terminals disposed at the corners at the most. Repeated up to the terminal (up to information n-1) <161
>.

そして、前記外部端子間の間隔ｘ（ｉ）及び間隔ｘ
（ｉ）の総和ｙ（ｉ）の算出がすべて行われた後、予じ
め設定された外部端子列の長さである情報ｃと総和ｙ
（ｉ）とが比較され＜162＞、両者の値が等しい場合に
は第５図に示す処理工程が終了する＜165＞。情報ｃに
比べて総和ｙ（ｉ）が小さい場合又情報ｃに比べて総和
ｙ（ｉ）が大きい場合は、情報ｃ、総和ｙ（ｉ）の夫々
が等しくなるまで、繰返し処理が行われる。And a distance x (i) and a distance x between the external terminals.
After all the sums y (i) of (i) are calculated, information c, which is the length of the external terminal row set in advance, and sum y
(I) is compared with <162>, and if the two values are equal, the processing step shown in FIG. 5 ends <165>. When the sum y (i) is smaller than the information c or when the sum y (i) is larger than the information c, the repetition processing is performed until the information c and the sum y (i) become equal.

次に、前記外部端子間の間隔を変更し、ボンディング
ワイヤ間の最小間隔ｈを均一化した後、第４図に示すよ
うに、主に外部端子、回路システムの入出力段回路の夫
々の結線の配置を外部端子の配置位置の変更に併せて変
更する＜16＞。Next, the distance between the external terminals is changed and the minimum distance h between the bonding wires is made uniform, and then, as shown in FIG. <16> in accordance with the change of the arrangement position of the external terminals.

次に、この結線の配置の変更に基づき、半導体チップ
のサイズが変化したか否かを確認し＜17＞、半導体チッ
プのサイズに変化がない場合にはDAに基づく自動化処理
が終了する＜18＞。半導体チップのサイズに変化がある
場合には半導体チップのサイズの算出＜14＞から再度処
理を行う。Next, it is confirmed whether or not the size of the semiconductor chip has changed based on the change in the arrangement of the connections <17>. If the size of the semiconductor chip has not changed, the automation process based on DA ends <18>. >. If there is a change in the size of the semiconductor chip, the process is performed again from the calculation of the size of the semiconductor chip <14>.

これら一連のDAに基づく自動化処理が終了すると、DA
での半導体チップの開発或は設計が完了する。When the automation process based on these DAs is completed, DA
The development or design of the semiconductor chip is completed.

これ以後は、前記DAで作成された情報で製造用マスク
を製作し、半導体製造プロセスにより半導体チップを製
作する。そして、リードフレームに完成した半導体チッ
プを搭載し、ボンディング工程、樹脂封止工程、リード
フレームの切断成型工程の夫々を施すことにより、前記
第２図に示す半導体装置が完成する。Thereafter, a manufacturing mask is manufactured using the information created by the DA, and a semiconductor chip is manufactured by a semiconductor manufacturing process. The semiconductor device shown in FIG. 2 is completed by mounting the completed semiconductor chip on the lead frame and performing each of a bonding step, a resin sealing step, and a cutting and molding step of the lead frame.

このように、平面方形状の半導体チップ２の外周囲
に、半導体チップ２の中心点Ｏからの放射線上にボンデ
ィング領域が設けられたインナーリード3Bを配列し、こ
のインナーリード3Bのボンディング領域、前記半導体チ
ップ２の周辺に沿って配列された外部端子21の夫々をボ
ンディングワイヤ５で接続する半導体装置１において、
前記半導体ペレット２の周辺の外部端子21を、辺の中央
部から角部に向って順次広い間隔ｘ（ｉ）で配列し、こ
の外部端子21に接続されるボンディングワイヤ５とそれ
に隣接する他のボンディングワイヤ５との最小間隔ｈ
を、これ以外のボンディングワイヤ５間の最小間隔ｈと
実質的に同一に構成する。この構成により、前記半導体
チップ２の外部端子21に接続されるボンディングワイヤ
５とそれに隣接する他のボンディングワイヤ５との間の
最小間隔ｈをすべてのボンディングワイヤ５間において
実質的に同一にし（均一化し）、半導体チップ２の辺の
限定された領域内においてボンディングワイヤ５間の離
隔寸法のマージン（許容値）を高められるので、ボンデ
ィングワイヤ５間の短絡を低減し、半導体装置１の電気
的信頼性を向上できる。As described above, the inner leads 3B provided with the bonding areas on the radiation from the center point O of the semiconductor chip 2 are arranged around the outer periphery of the semiconductor chip 2 having a planar rectangular shape, and the bonding area of the inner leads 3B is In the semiconductor device 1 in which each of the external terminals 21 arranged along the periphery of the semiconductor chip 2 is connected by the bonding wire 5,
The external terminals 21 around the semiconductor pellet 2 are sequentially arranged at a wide interval x (i) from the center of the side to the corner, and the bonding wire 5 connected to the external terminal 21 and another adjacent to the bonding wire 5 are arranged. Minimum distance h from bonding wire 5
Is substantially the same as the minimum distance h between the other bonding wires 5. With this configuration, the minimum distance h between the bonding wire 5 connected to the external terminal 21 of the semiconductor chip 2 and another bonding wire 5 adjacent thereto is made substantially the same between all the bonding wires 5 (uniformly). ), The margin (permissible value) of the separation dimension between the bonding wires 5 can be increased in a limited area of the side of the semiconductor chip 2, so that the short circuit between the bonding wires 5 is reduced and the electrical reliability of the semiconductor device 1 is reduced. Performance can be improved.

また、平面方形状の半導体チップ２の外周囲に、半導
体チップ２の中心点Ｏからの放射線上にボンディング領
域が設けられたインナーリード3Bを配列し、このインナ
ーリード3Bのボンディング領域、前記半導体チップ3Bの
周辺に沿って配列された外部端子21の夫々をボンディン
グワイヤ５で接続する半導体装置１の形成方法におい
て、DAのメモリ空間内に仮想的に設定された半導体チッ
プ（２）の中央部分に回路システム（23）を配置すると
共に、前記半導体チップの周辺に前記回路システムに接
続される複数の外部端子（21）をそれに隣接する他の外
部端子との間隔がこれ以外の外部端子間の間隔と実質的
に同一で配置する段階＜12＞と、この回路システム、外
部端子の夫々が配置された半導体チップのサイズを算出
する段階＜14＞と、この半導体チップのサイズの算出結
果、配置される外部端子数の夫々の情報から隣接するボ
ンディングワイヤ５間の最小間隔ｈの平均値を算出し、
このボンディングワイヤ５間の最小間隔ｈの平均値に基
づき、前記同一間隔に配列された外部端子の配列を変更
する段階＜15＞（＜151＞〜＜165＞）とを備える。この
構成により、DAを使用し、半導体チップのサイズの算出
結果、外部端子数の夫々の情報から自動的に隣接する外
部端子間の間隔を変更し、自動的に隣接するボンディン
グワイヤ５間の最小間隔ｈをこれ以外のボンディングワ
イヤ５間の最小間隔ｈと実質的に同一に設定できるの
で、人手作業を廃止し、半導体装置１の開発期間を短縮
できる。また、人手作業に基づく人為的なミスをなくし
たので、半導体装置１の開発における信頼性を向上でき
る。Further, inner leads 3B provided with a bonding region on the outer periphery of the semiconductor chip 2 having a planar rectangular shape on the radiation from the center point O of the semiconductor chip 2 are arranged, and the bonding region of the inner leads 3B, In the method for forming the semiconductor device 1 in which each of the external terminals 21 arranged along the periphery of the 3B is connected by the bonding wire 5, the external terminal 21 is disposed at the center of the semiconductor chip (2) virtually set in the memory space of the DA. A circuit system (23) is arranged, and a plurality of external terminals (21) connected to the circuit system around the semiconductor chip are spaced from other external terminals adjacent thereto by a distance between other external terminals. A step <12> of substantially arranging the circuit system and the size of the semiconductor chip on which each of the external terminals is disposed, and a step <14> of calculating the size of the semiconductor chip. Chip size calculation result of an average value of the minimum gap h between the bonding wire 5 adjacent the number of external terminals of each of the information arranged,
Changing the arrangement of the external terminals arranged at the same interval based on the average value of the minimum intervals h between the bonding wires 5 <15>(<151> to <165>). With this configuration, the distance between adjacent external terminals is automatically changed from the information on the number of external terminals and the result of calculation of the size of the semiconductor chip using the DA, and the minimum distance between the adjacent bonding wires 5 is automatically adjusted. Since the interval h can be set to be substantially the same as the minimum interval h between the other bonding wires 5, manual work can be eliminated and the development period of the semiconductor device 1 can be shortened. In addition, since human errors due to manual work are eliminated, reliability in the development of the semiconductor device 1 can be improved.

また、前記半導体装置１の形成方法において、予じめ
回路システム及び外部端子を等間隔で配置する段階＜12
＞と、この後、半導体チップのサイズを算出する段階＜
14＞を行い、この半導体チップのサイズの算出結果に基
づいて外部端子の位置を変更する段階＜15＞とを備え
る。この構成により、予じめ外部端子の配置位置を変更
してボンディングワイヤ５間の最小間隔ｈを均一化し、
この後に回路システムを自動的に配置する場合に比べ
て、DAで自動的に配置された回路システムのサイズに合
せて外部端子の配置位置を変更したので、回路システム
23の配置において無駄な空領域を低減し、レイアウト効
率を高められる。In the method of forming the semiconductor device 1, the step of arranging the circuit system and the external terminals at equal intervals in advance <12.
> And thereafter, the step of calculating the size of the semiconductor chip <
14> and changing the position of the external terminal based on the calculation result of the size of the semiconductor chip <15>. With this configuration, the minimum distance h between the bonding wires 5 is made uniform by changing the arrangement positions of the external terminals in advance.
Compared to the case where the circuit system was automatically arranged after this, the arrangement position of the external terminals was changed according to the size of the circuit system automatically arranged by DA.
In the arrangement of 23, useless empty area can be reduced and layout efficiency can be improved.

以上、本発明者によってなされた発明を、前記実施例
に基づき具体的に説明したが、本発明は、前記実施例に
限定されるものではなく、その要旨を逸脱しない範囲に
おいて種々変更可能であることは勿論である。As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

例えば、本発明は、前記第１図に示す半導体装置にお
いて、隣接するインナーリード3Bが配置される２本の放
射線のなす角度をそれ以外の２本の放射線のなす角度と
実質的に同一に設定してもよい。For example, according to the present invention, in the semiconductor device shown in FIG. 1, the angle formed by two radiations at which the adjacent inner leads 3B are arranged is set substantially equal to the angle formed by the other two radiations. May be.

また、本発明は、QFP構造以外にPLCC構造、PGA構造等
を採用する樹脂封止型半導体装置、或はセラミック封止
型半導体装置に適用できる。Further, the present invention can be applied to a resin-encapsulated semiconductor device or a ceramic-encapsulated semiconductor device employing a PLCC structure, a PGA structure, or the like in addition to the QFP structure.

〔発明の効果〕〔The invention's effect〕

本願において開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

DAにより開発や設計が支援される半導体装置におい
て、ワイヤ間の短絡を低減し、電気的信頼性を向上でき
る。In a semiconductor device whose development and design are supported by DA, short circuit between wires can be reduced, and electrical reliability can be improved.

DAにより開発や設計が支援される半導体装置におい
て、開発期間を短縮できる。In a semiconductor device whose development and design are supported by DA, the development period can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

第１図は、本発明の一実施例であるQFP構造を採用する
パッケージで構成された半導体装置の要部平面図、 第２図は、前記半導体装置の断面図、 第３図は、DAで取り扱うための計算モデル図、 第４図は、前記半導体装置の形成方法を説明する全体の
プロセスフロー図、 第５図は、前記半導体装置の形成方法を説明するための
一部のプロセスフロー図である。 図中、１…半導体装置、２…半導体チップ、21…外部端
子、23…回路システム、3B…インナーリード、５…ボン
ディングパッド、６…樹脂である。FIG. 1 is a plan view of a main part of a semiconductor device constituted by a package adopting a QFP structure according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device, and FIG. FIG. 4 is an overall process flow diagram illustrating a method of forming the semiconductor device, and FIG. 5 is a partial process flow diagram illustrating a method of forming the semiconductor device. is there. In the figure, 1 denotes a semiconductor device, 2 denotes a semiconductor chip, 21 denotes an external terminal, 23 denotes a circuit system, 3B denotes an inner lead, 5 denotes a bonding pad, and 6 denotes a resin.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−105349（ＪＰ，Ａ) 特開 昭56−122144（ＪＰ，Ａ) 特開 昭61−212050（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/82 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-105349 (JP, A) JP-A-56-122144 (JP, A) JP-A-61-212050 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 21/82

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】平面方形状の半導体チップの外周囲に、半
導体チップの中心からの放射線上にボンディング領域が
設けられたリードを配列し、これらのリードのボンディ
ング領域と前記半導体チップの周辺に沿って配列された
外部端子の夫々をワイヤで接続する半導体装置の形成方
法において、 前記半導体チップのサイズ及び外部端子の数を含む配置
情報から、外部端子の間隔を均一とした場合のボンディ
ングワイヤ相互の最小間隔の平均値を求める段階と、 このワイヤ間の最小間隔の平均値に基づき、外部端子に
接続されるワイヤとそれに隣接する他のワイヤ相互の間
隔を均一化して外部端子を配列する段階とを備えたこと
を特徴とする半導体装置の形成方法。1. A semiconductor device according to claim 1, further comprising: a plurality of leads having bonding regions provided on the outer periphery of the semiconductor chip having a rectangular shape on the radiation from the center of the semiconductor chip, along the bonding regions of these leads and the periphery of the semiconductor chip. The method of forming a semiconductor device in which each of the external terminals arranged in a line is connected by a wire, the bonding wires having a uniform interval between the external terminals are determined based on arrangement information including the size of the semiconductor chip and the number of external terminals. A step of obtaining an average value of the minimum intervals; and a step of arranging the external terminals by equalizing the intervals between the wires connected to the external terminals and other wires adjacent thereto based on the average values of the minimum intervals between the wires. A method for forming a semiconductor device, comprising: 【請求項２】平面方形状の半導体チップの外周囲に、半
導体チップの中心からの放射線上にボンディング領域が
設けられたリードを配列し、これらのリードのボンディ
ング領域と、前記半導体チップの周辺に沿って配列され
た外部端子の夫々をワイヤで接続する半導体装置に使用
される前記半導体チップの外部端子の配置方法であっ
て、 前記半導体チップの各辺に外部端子を等間隔に配置した
場合のチップサイズを見積もる工程と、 前記チップサイズの算出結果、外部端子数の情報に基づ
き、隣接するワイヤ間の間隔の平均値を算出し、各ワイ
ヤが前記半導体チップの中心からの放射線上に張られた
と仮定した場合に各ワイヤ間の間隔が実質的に同一とな
るように、前記半導体チップの外部端子を、辺の中央部
から角部に向かって前記平均値より順次広くなる間隔で
配置しなおす工程とを備えたことを特徴とする半導体チ
ップの外部端子の配置方法。2. The semiconductor device according to claim 1, further comprising a plurality of leads arranged on the outer periphery of the semiconductor chip having a rectangular shape and having bonding regions formed on the radiation from the center of the semiconductor chip. A method of arranging external terminals of the semiconductor chip used in a semiconductor device for connecting each of the external terminals arranged along a wire, wherein the external terminals are arranged at equal intervals on each side of the semiconductor chip. Estimating the chip size, calculating the chip size, calculating the average value of the spacing between adjacent wires based on the information on the number of external terminals, and setting each wire on the radiation from the center of the semiconductor chip. The external terminals of the semiconductor chip are averaged from the center to the corners of the side so that the spacing between the wires becomes substantially the same when it is assumed that Method of arranging the external terminals of the semiconductor chip, characterized in that a step of repositioning in a more sequential widens spacing.
JP20084790A 1990-07-27 1990-07-27 Method of forming semiconductor device and method of arranging external terminals of semiconductor chip Expired - Lifetime JP3044053B2 (en)

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JP20084790A JP3044053B2 (en) 1990-07-27 1990-07-27 Method of forming semiconductor device and method of arranging external terminals of semiconductor chip

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Application Number Priority Date Filing Date Title
JP20084790A JP3044053B2 (en) 1990-07-27 1990-07-27 Method of forming semiconductor device and method of arranging external terminals of semiconductor chip

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Publication Number Publication Date
JPH0485947A JPH0485947A (en) 1992-03-18
JP3044053B2 true JP3044053B2 (en) 2000-05-22

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