JP3036486B2 - Failure analysis method for integrated circuit and failed integrated circuit assembly - Google Patents
Failure analysis method for integrated circuit and failed integrated circuit assemblyInfo
- Publication number
- JP3036486B2 JP3036486B2 JP9274703A JP27470397A JP3036486B2 JP 3036486 B2 JP3036486 B2 JP 3036486B2 JP 9274703 A JP9274703 A JP 9274703A JP 27470397 A JP27470397 A JP 27470397A JP 3036486 B2 JP3036486 B2 JP 3036486B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- analysis
- pads
- tape
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、集積回路の故障解
析方法および故障集積回路組立体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit failure analysis method and a failed integrated circuit assembly.
【０００２】[0002]
【従来の技術】従来のＬＳＩ等の集積回路の故障解析技
術においては、主にＬＳＩチップ表面からのテスタ等で
絞り込まれた被疑故障箇所に対してＥＢテスタでの測
定、プローバによる探針、エミッション顕微鏡観察など
を行い、故障箇所の特定を行っている。2. Description of the Related Art In a conventional failure analysis technique for an integrated circuit such as an LSI, a suspicious fault spot narrowed down mainly by a tester or the like from the surface of an LSI chip is measured by an EB tester, a probe by a prober, and an emission. The failure location is identified by microscopic observation.
【０００３】[0003]
【発明が解決しようとする課題】従来の技術では、故障
箇所の特定が困難になりつつある。そのため、チップ裏
面からの故障解析（チップ裏面から、エミッション、Ｏ
ＢＩＣ、ＯＢＩＲＣＨ法等の発光を検出する解析）を組
み合わせて行うことが必要となりつつある。その理由
は、ＬＳＩの多層化のため、チップ表面からの解析のみ
では、上層配線が邪魔となり、被疑故障箇所の測定、観
測ができないからである。In the prior art, it is becoming difficult to specify a failure location. Therefore, failure analysis from the back of the chip (emission, O
It is becoming necessary to perform a combination of BIC, OBIRCH analysis, and other analysis for detecting light emission. The reason for this is that, due to the multi-layered LSI, the analysis of only the chip surface hinders the upper layer wiring, so that the suspected fault location cannot be measured and observed.
【０００４】従来技術の第２の問題点は、一度パッケー
ジに組み立てられたＬＳＩの故障解析を行う場合、チッ
プ裏面からの解析と表面からの解析を組み合わせて行う
ことが難しいことである。特に裏面解析を行うことが難
しい。A second problem of the prior art is that it is difficult to perform a failure analysis of an LSI once assembled in a package by combining an analysis from the back surface of the chip with an analysis from the front surface. In particular, it is difficult to perform backside analysis.
【０００５】その理由はＬＳＩがフェイスアップで取り
付けられた場合、開封するだけで、表面からの解析は行
うことができるが、裏面解析を行うことはできない。裏
面解析を行うためには、チップをパッケージから取り外
す必要があるが、パッケージから取り外してしまうと、
解析に必要な電源や信号をチップに印加することができ
なくなる。また、ＬＳＩがフェイスダウンで取り付けら
れた場合は、チップ裏面を研磨するときにリードにダメ
ージを与えないで行うことが難しく、このときリードが
切れると解析ができなくなることがある。また、表面か
らの解析を行うためには別のパッケージにフェイスアッ
プで組み立て直す必要があるためである。[0005] The reason is that when the LSI is mounted face-up, the analysis can be performed from the front surface only by opening the package, but the back surface analysis cannot be performed. In order to perform backside analysis, it is necessary to remove the chip from the package, but if it is removed from the package,
Power and signals required for analysis cannot be applied to the chip. In addition, when the LSI is mounted face down, it is difficult to polish the back surface of the chip without damaging the leads. At this time, if the leads are cut, analysis may not be performed. In addition, in order to perform analysis from the surface, it is necessary to reassemble face-up into another package.
【０００６】本発明の目的は、特に一度パッケージに組
み立てられた故障ＬＳＩに対して裏面解析と表面からの
解析を必要に応じて容易に行うことができる故障解析方
法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a failure analysis method capable of easily performing backside analysis and analysis from the front side as needed, particularly for a faulty LSI once assembled in a package.
【０００７】[0007]
【課題を解決するための手段】本発明の故障解析方法
は、パッケージからＬＳＩを取り外した後にＬＳＩの解
析に必要な電源、グランド、信号を印加するのに必要な
パターンが形成され、さらに両面に貫通スルーホールを
通してパッドを備えているＴＡＢテープを用いて、チッ
プ側のパッドとテープ側のリードを接続して、ＴＣＰを
形成する。According to the failure analysis method of the present invention, after removing an LSI from a package, a pattern necessary for applying a power supply, a ground, and a signal required for the analysis of the LSI is formed. Using a TAB tape provided with a pad through the through-hole, the pad on the chip side and the lead on the tape side are connected to form TCP.
【０００８】このＴＣＰに信号を印加するためにソケッ
トを作成し、ソケットに取り付けたポゴピンとＴＣＰの
パッドを接触させる。A socket is formed for applying a signal to the TCP, and a pogo pin attached to the socket is brought into contact with a TCP pad.
【０００９】裏面解析を行う場合は、チップをフェイス
ダウンでソケットに取り付けて電源電圧や信号を印加
し、また、表面からのＥＢテスタ等の解析を行う場合に
は、チップをフェイスアップでソケットに取り付けて、
電源電圧や信号を印加して解析を行う。[0009] When performing a back surface analysis, the chip is mounted face down to a socket to apply a power supply voltage and a signal. When an EB tester or the like is analyzed from the front side, the chip is mounted face up to the socket. Attach,
Analysis is performed by applying a power supply voltage or signal.
【００１０】パッケージに組み立てられたＬＳＩを取り
外してＴＣＰに組み立て直して、ソケットに取り付け
て、裏面解析に必要な電源電圧や信号をＬＳＩに印加す
ることができるようになり、ソケットに取り付けるチッ
プの向きを変えることで、裏面解析と表面からの解析と
を容易に使い分けることができるようになる。[0010] The LSI assembled in the package is removed, reassembled in TCP, mounted in a socket, and a power supply voltage and a signal required for back surface analysis can be applied to the LSI. By changing the value, it is possible to easily use the back side analysis and the front side analysis.
【００１１】[0011]
【発明の実施の形態】次に本発明の実施の形態について
図面を参照して詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１２】図１は故障ＬＳＩを本発明のＴＣＰに組み
立てた時の断面図、図２は裏面解析時のＴＣＰをソケッ
トに取り付けた時の断面図および図３は表面から解析時
のＴＣＰをソケットに取り付けた時の断面図である。FIG. 1 is a cross-sectional view when a faulty LSI is assembled into a TCP of the present invention, FIG. 2 is a cross-sectional view when a TCP is mounted on a socket when analyzing a back surface, and FIG. It is sectional drawing at the time of attaching to.
【００１３】図１において、ＬＳＩチップ１は、図４に
示す集積回路パッケージ（ＱＦＰ、ＰＧＡ等）１６を開
封して取り出した故障ＬＳＩチップであり、裏面解析を
行えるようにその裏面が鏡面研磨されている。ＴＡＢ
（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）テ
ープ３には、ＬＳＩチップ１の解析に必要な電源配線パ
ターン、グランド（接地）配線パターン、信号配線パタ
ーンが形成されている。さらに、ＴＡＢテープ３の両面
には貫通スルーホール６を介して接続されたパッド５が
設けられている。ＩＬＢパッド２とＴＡＢテープ３上の
リード４の先端とは、位置合わせ後にボンディングツー
ルでリード４およびＩＬＢパッド２を加圧しながら加熱
することにより、接合される。In FIG. 1, an LSI chip 1 is a faulty LSI chip obtained by opening the integrated circuit package (QFP, PGA, etc.) 16 shown in FIG. 4, and its back surface is mirror-polished so that back surface analysis can be performed. ing. TAB
On the (Tape Automated Bonding) tape 3, a power supply wiring pattern, a ground (ground) wiring pattern, and a signal wiring pattern necessary for analysis of the LSI chip 1 are formed. Further, pads 5 connected to both sides of the TAB tape 3 via through-holes 6 are provided. The ILB pad 2 and the tip of the lead 4 on the TAB tape 3 are joined by positioning and heating the lead 4 and the ILB pad 2 while applying pressure with a bonding tool.
【００１４】このような構成の組立体において、ＬＳＩ
チップ１の裏面解析（エミッション観察、ＯＢＩＣ法、
ＯＢＩＲＣＨ法等）を行う場合には、まず、図２に示す
ように、ＬＳＩチップ１をフェイスダウンでＴＡＢテー
プ３のパッド５とポゴピン（バネ圧により上下動可能な
端子）８とが接触するようにソケット７に置き、カバー
９で押さえつける。In the assembly having such a configuration, the LSI
Backside analysis of chip 1 (emission observation, OBIC method,
In the case of performing the OBIRCH method or the like, first, as shown in FIG. 2, the pads 5 of the TAB tape 3 and the pogo pins (terminals which can be moved up and down by spring pressure) 8 are brought into contact with the LSI chip 1 face down. Then, place it on the socket 7 and hold it down with the cover 9.
【００１５】一方、ＬＳＩチップ１の表面から解析（Ｅ
Ｂテスタ、プローバによる探針等）を行う場合には、図
３に示すように、ＬＳＩチップ１をフェイスアップでＴ
ＡＢテープ３のパッド５とポゴピン８とが接触するよう
にソケット７に置き、カバー９で押さえつける。On the other hand, an analysis (E
B tester, prober using a prober, etc.), as shown in FIG.
The pad 5 of the AB tape 3 is placed on the socket 7 so that the pad 5 and the pogo pin 8 are in contact with each other.
【００１６】次に、上述した実施の形態についてさらに
具体的に説明する。Next, the above-described embodiment will be described more specifically.
【００１７】パッケージ１６がＰＧＡであるとすると、
このＰＧＡは、ＬＳＩチップ１をＴＡＢでフェイスダウ
ンに実装し、ＡｌＮ（チッ化アルミ）のキャップ１２で
カバーしてダイボディングと封止が行われる構造となっ
ている。ダイボンディング材には、例えば、Ａｇ（銀）
エポキシ接着剤が使用される。ＬＳＩチップ１は次のよ
うにして、取り外される。キャップ１２の周辺のコバー
リング１３をミニター等で切断する。キャップを下側に
して３５０℃に加熱したホットプレート上に１０分置
き、基板を持ち上げて、ＬＳＩチップ１をキャップ１２
から剥がす。ＴＡＢリード１４を切断してＬＳＩチップ
１を取り出す。ＬＳＩチップ１の裏面に残ったＡｇエポ
キシ接着剤を除去した後、研磨剤を用いて裏面を研磨す
る。室温で発煙硝酸にＬＳＩチップ１を浸して、モール
ドを除去する。ＩＬＢパッド２上に残ったリードを除去
してＬＳＩチップ１単体にする。If the package 16 is PGA,
The PGA has a structure in which an LSI chip 1 is mounted face down with TAB and covered with a cap 12 made of AlN (aluminum nitride) to perform die bonding and sealing. For the die bonding material, for example, Ag (silver)
Epoxy adhesive is used. The LSI chip 1 is removed as follows. The Kovar ring 13 around the cap 12 is cut with a mini-turter or the like. Place the cap on the hot plate heated to 350 ° C. for 10 minutes, lift the substrate, and place the LSI chip 1 in the cap 12.
Remove from The TAB lead 14 is cut and the LSI chip 1 is taken out. After the Ag epoxy adhesive remaining on the back surface of the LSI chip 1 is removed, the back surface is polished using an abrasive. The LSI chip 1 is immersed in fuming nitric acid at room temperature to remove the mold. The lead remaining on the ILB pad 2 is removed to make the LSI chip 1 alone.
【００１８】ＴＡＢテープ３の各配線パターンの材料は
銅箔を加工し、その上に金めっきされたものが使用され
る。貫通スルーホール６は銅めっきで形成される。ＬＳ
Ｉチップ１とＴＡＢテープ３との接合は、ＬＳＩチップ
１を加熱したボンディングステージ上に載せて、ＩＬＢ
パッド２とＴＡＢテープ３のリード４の先端との位置を
合わせてボンディングツールに超音波と荷重を加えてリ
ード４とＩＬＢパッド２とを接合させる。The material of each wiring pattern of the TAB tape 3 is formed by processing a copper foil and plating it with gold. The through hole 6 is formed by copper plating. LS
The bonding between the I chip 1 and the TAB tape 3 is performed by placing the LSI chip 1 on a heated bonding stage,
The position of the pad 2 and the tip of the lead 4 of the TAB tape 3 are aligned, and an ultrasonic wave and a load are applied to the bonding tool to join the lead 4 and the ILB pad 2 together.
【００１９】[0019]
【発明の効果】本発明の効果は、故障ＬＳＩチップの表
面からの解析と裏面からの解析とを同一のパッケージで
行うことができるので、表面からの解析と裏面からの解
析との使い分けが容易になるというものである。The effect of the present invention is that the analysis from the front side and the analysis from the back side of the faulty LSI chip can be performed in the same package, so that the analysis from the front side and the analysis from the back side can be easily used properly. It is to become.
【００２０】その理由は、故障ＬＳＩチップをパッケー
ジから取り外して、両面にパッド５を備えたＴＣＰに組
み立て直すため、ＬＳＩチップの表面および裏面のどち
らを上側にしても、解析に必要な電源電圧や信号をパッ
ド５から印加することが可能になるためである。The reason is that the faulty LSI chip is removed from the package and reassembled into a TCP having the pads 5 on both sides, so that the power supply voltage and the power supply required for the analysis can be obtained regardless of whether the front side or the back side of the LSI chip is on the upper side. This is because a signal can be applied from the pad 5.
【図１】本発明の組立方法で故障ＬＳＩをＴＣＰに組み
立てた時の断面図である。FIG. 1 is a cross-sectional view when a failed LSI is assembled into a TCP by the assembling method of the present invention.
【図２】裏面解析を行う時のＴＣＰをソケットに載せた
時の断面図である。FIG. 2 is a cross-sectional view when a TCP is mounted on a socket when performing back surface analysis.
【図３】表面解析を行う時のＴＣＰをソケットに載せた
時の断面図である。FIG. 3 is a cross-sectional view when a TCP for performing a surface analysis is placed on a socket.
【図４】故障ＬＳＩを実装したＰＧＡの断面図である。FIG. 4 is a sectional view of a PGA on which a failed LSI is mounted.
１ ＬＳＩチップ ２ ＩＬＢパッド ３ ＴＡＢテープ ４ リード ５ パッド ６ 貫通スルーホール ７ ソケット ８ ポゴピン ９ カバー １０ ＬＳＩチップ裏面 １１ ＬＳＩチップ表面 １２ キャップ １３ コバーリング １４ ＴＡＢリード １５ 基板 １６ ＰＧＡ REFERENCE SIGNS LIST 1 LSI chip 2 ILB pad 3 TAB tape 4 lead 5 pad 6 through through hole 7 socket 8 pogo pin 9 cover 10 LSI chip back surface 11 LSI chip surface 12 cap 13 Kovarring 14 TAB lead 15 substrate 16 PGA
Claims (4)
工程と、貫通するスルーホールで接続されたパッドを両
面に設けたＴＡＢテープに前記集積回路を取り付けた組
立体を形成する工程と、この組立体の前記パッドと接触
させるためのバネ圧により上下動可能な端子を設けたソ
ケットに前記組立体をフェイスダウンまたはフェイスア
ップで取り付ける工程と、前記集積回路の表面または裏
面から解析を行う工程とを含むことを特徴とする集積回
路の故障解析方法。1. A step of removing a faulty integrated circuit from a package, a step of forming an assembly in which the integrated circuit is mounted on a TAB tape provided on both sides with pads connected by penetrating through holes, and a step of forming the assembly. A step of mounting the assembly face-down or face-up on a socket provided with a terminal capable of moving up and down by a spring pressure for bringing the pad into contact with the pad, and a step of performing analysis from the front surface or the back surface of the integrated circuit. A failure analysis method for an integrated circuit, comprising:
はプローバによる探針により行うことを特徴とする請求
項１記載の集積回路の故障解析方法。2. The method according to claim 1, wherein the analysis from the surface is performed by a probe using an EB tester or a prober.
察、ＯＢＩＣ法またはＯＢＩＲＣＨ法で行うことを特徴
とする請求項１記載の集積回路の故障解析方法。3. The failure analysis method for an integrated circuit according to claim 1, wherein the analysis from the back surface is performed by emission observation, OBIC method, or OBIRCH method.
と、 該テープの他方の面に形成され前記複数の第１のパッド
と一対一対応にする複数の第２のパッドと、 前記複数の第１のパッドのそれぞれと前記複数の第２の
パッドの対応する一つとを接続するスルーホールと、 前記テープ上に形成され、前記複数の第１のパッドと前
記集積回路とを電気的に接続する配線パターンとを備え
たことを特徴とする故障集積回路組立体。4. A failed integrated circuit, a TAB tape to which the integrated circuit is attached, a plurality of first pads formed on one surface of the tape, and a plurality of first pads formed on the other surface of the tape. A plurality of second pads in one-to-one correspondence with a plurality of first pads; a through hole connecting each of the plurality of first pads to a corresponding one of the plurality of second pads; A faulty integrated circuit assembly, comprising: a wiring pattern formed on a tape for electrically connecting the plurality of first pads to the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9274703A JP3036486B2 (en) | 1997-10-07 | 1997-10-07 | Failure analysis method for integrated circuit and failed integrated circuit assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9274703A JP3036486B2 (en) | 1997-10-07 | 1997-10-07 | Failure analysis method for integrated circuit and failed integrated circuit assembly |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11111759A JPH11111759A (en) | 1999-04-23 |
| JP3036486B2 true JP3036486B2 (en) | 2000-04-24 |
Family
ID=17545392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9274703A Expired - Fee Related JP3036486B2 (en) | 1997-10-07 | 1997-10-07 | Failure analysis method for integrated circuit and failed integrated circuit assembly |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036486B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004214248A (en) | 2002-12-27 | 2004-07-29 | Renesas Technology Corp | Socket |
| JP2008232768A (en) | 2007-03-19 | 2008-10-02 | Fujitsu Ltd | Board for evaluation and failure portion detecting method |
-
1997
- 1997-10-07 JP JP9274703A patent/JP3036486B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11111759A (en) | 1999-04-23 |
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