JP3031330B2 - Ceramic package - Google Patents
Ceramic packageInfo
- Publication number
- JP3031330B2 JP3031330B2 JP9926198A JP9926198A JP3031330B2 JP 3031330 B2 JP3031330 B2 JP 3031330B2 JP 9926198 A JP9926198 A JP 9926198A JP 9926198 A JP9926198 A JP 9926198A JP 3031330 B2 JP3031330 B2 JP 3031330B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- ceramic
- ceramic substrate
- thermal expansion
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子を高密
度に配線基板に実装することを可能にするとともに、熱
膨張係数の異なる配線基板に実装する際、この熱膨張係
数差に起因する接続信頼性の低下を改善するセラミック
・パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to mount a semiconductor element on a wiring board at a high density and, when mounting the semiconductor elements on wiring boards having different thermal expansion coefficients, a connection caused by this difference in the thermal expansion coefficient. The present invention relates to a ceramic package that improves reliability.
【０００２】[0002]
【従来の技術】従来、半導体素子はＴＳＯＰ、ＱＦＰや
ＴＡＢといったパッケージ形態で配線基板に表面実装さ
れてきたが、電子機器の小型、軽量化に伴い、より実装
面積を小さくすることが求められてきている。このよう
な要求に対して、半導体素子をチップサイズパッケージ
として配線基板にバンプ接続する技術が用いられるよう
になっている。たとえば特開平８−２３６６９４号公報
には、半導体素子を小型の基板に実装したものにバンプ
を形成し、これを多段に積んで一つのパッケージとして
配線基板に実装する技術が記載されている。このような
技術においては、低コスト化の要求からプリント配線基
板が実装基板として用いられている。2. Description of the Related Art Conventionally, semiconductor elements have been surface-mounted on a wiring board in the form of a package such as TSOP, QFP, or TAB. However, as electronic devices have become smaller and lighter, a smaller mounting area has been required. ing. In response to such demands, a technique of connecting a semiconductor element to a wiring board as a chip-size package by bump connection has been used. For example, Japanese Patent Application Laid-Open No. Hei 8-236694 discloses a technique in which bumps are formed on a semiconductor element mounted on a small-sized board, and the bumps are stacked in multiple stages and mounted on a wiring board as one package. In such a technique, a printed wiring board is used as a mounting board due to a demand for cost reduction.
【０００３】[0003]
【発明が解決しようとする課題】実装基板として用いら
れているプリント配線基板は、Ｓｉ素子やＧａＡｓ素子
と比較して大きな熱膨張係数をもつため、使用環境の温
度変化、又は通電時の半導体素子の発熱による温度変化
により半導体素子と配線基板との間に応力が生じ、高密
度実装を可能にするバンプ接続により実装した半導体素
子では、接続部分、すなわちバンプ部分に亀裂が生じる
など、熱膨張差に起因する接続不良の発生が問題とな
る。半導体素子をセラミックス基板に接続し、セラミッ
クス基板をプリント配線基板に実装する形態をとった場
合においても、半導体素子とセラミックス基板の接続部
分、セラミックス基板とプリント配線基板との接続部分
のそれぞれで、同様の接続不良発生が問題となる。A printed wiring board used as a mounting board has a larger coefficient of thermal expansion than a Si element or a GaAs element. A temperature change due to heat generated by the semiconductor causes stress between the semiconductor element and the wiring board, and a semiconductor element mounted by bump connection that enables high-density mounting has a difference in thermal expansion, such as a crack in a connection portion, that is, a bump portion. This causes a problem of poor connection caused by the above. Even in the case where the semiconductor element is connected to the ceramic substrate and the ceramic substrate is mounted on the printed wiring board, the same applies to the connection between the semiconductor element and the ceramic substrate and the connection between the ceramic substrate and the printed wiring board. Is a problem in connection failure.
【０００４】本発明は、以上の問題を解決し、半導体素
子の高密度実装を可能にするとともに、接続信頼性低下
を改善するセラミック・パッケージを提供することを目
的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a ceramic package which solves the above problems, enables high-density mounting of a semiconductor element, and improves a decrease in connection reliability.
【０００５】[0005]
【課題を解決するための手段】本発明のセラミック・パ
ッケージは、半導体素子を高密度に配線基板に実装する
ことを可能にするとともに、熱膨張係数の異なる配線基
板に実装する際、この熱膨張係数差に起因する接続信頼
性低下を改善する半導体素子実装パッケージである。SUMMARY OF THE INVENTION The ceramic package of the present invention enables a semiconductor element to be mounted on a wiring board at a high density. This is a semiconductor element mounting package that improves a decrease in connection reliability caused by a coefficient difference.
【０００６】具体的には、半導体素子がセラミックス基
板に実装され、さらに前記セラミックス基板が、前記半
導体素子と異なる熱膨張係数を有する配線基板に実装さ
れた構造よりなるセラミック・パッケージにおいて、セ
ラミックス基板は配線基板へバンプ接続によって実装さ
れており、バンプは前記セラミックス基板における半導
体素子実装領域の外周部分に形成されており、少なくと
も半導体素子実装領域の外周部分の前記セラミックス基
板の厚みは０．１ｍｍ以上０．５ｍｍ以下であり、か
つ、セラミックス基板の熱膨張係数Ｖｓが半導体素子の
熱膨張係数Ｖｃと配線基板の熱膨張係数Ｖｂの中間であ
ることを特徴とするセラミック・パッケージである。Specifically, in a ceramic package having a structure in which a semiconductor element is mounted on a ceramic substrate and the ceramic substrate is mounted on a wiring substrate having a different thermal expansion coefficient from that of the semiconductor element, The bumps are mounted on the wiring substrate by bump connection, and the bumps are formed on an outer peripheral portion of the semiconductor element mounting region on the ceramic substrate. At least an outer peripheral portion of the semiconductor element mounting region has a thickness of 0.1 mm or more and 0 mm. 0.5 mm or less, and wherein the thermal expansion coefficient Vs of the ceramic substrate is intermediate between the thermal expansion coefficient Vc of the semiconductor element and the thermal expansion coefficient Vb of the wiring substrate.
【０００７】図１及び図２において、セラミック・パッ
ケージ１には厚さ０．５ｍｍ以下のセラミックス基板２
の上に半導体素子３が接続され、バンプ４が半導体素子
の外周部分に形成されている。これらセラミック・パッ
ケージは、図３の様にバンプ４を介して配線基板７に実
装される。1 and 2, a ceramic package 1 has a ceramic substrate 2 having a thickness of 0.5 mm or less.
The semiconductor element 3 is connected to the semiconductor device, and the bump 4 is formed on the outer peripheral portion of the semiconductor element. These ceramic packages are mounted on the wiring board 7 via the bumps 4 as shown in FIG.
【０００８】セラミック・パッケージ１は、配線基板７
へバンプ接続できることから、実装面積を従来のＴＳＯ
ＰやＱＦＰと比較して小さくできる。また、バンプ４を
半導体素子実装面外に形成し、セラミックス基板２の厚
さを０．５ｍｍ以下とし、かつ、セラミックス基板の熱
膨張係数を半導体素子３と配線基板７の熱膨張係数の中
間値にすることにより、半導体素子３と配線基板７との
熱膨張係数差に起因する接続信頼性の低下を改善するこ
とが可能になる。The ceramic package 1 includes a wiring board 7
The mounting area can be reduced to the conventional TSO
It can be smaller than P or QFP. Further, the bumps 4 are formed outside the semiconductor element mounting surface, the thickness of the ceramic substrate 2 is set to 0.5 mm or less, and the coefficient of thermal expansion of the ceramic substrate is an intermediate value between the coefficient of thermal expansion of the semiconductor element 3 and the coefficient of thermal expansion of the wiring board 7. By doing so, it is possible to improve a decrease in connection reliability caused by a difference in thermal expansion coefficient between the semiconductor element 3 and the wiring board 7.
【０００９】[0009]
【発明の実施の形態】本発明を具体的に表した全体構成
を説明する。BEST MODE FOR CARRYING OUT THE INVENTION An overall configuration specifically illustrating the present invention will be described.
【００１０】図１は本発明によるセラミック・パッケー
ジの一形態である。厚さが０．１ｍｍ以上、０．５ｍｍ
以下のセラミックス基板２に半導体素子３が微小バンプ
６及び封止樹脂５によって固定されている。セラミック
ス基板２で半導体素子３を固定している領域の外周部分
にバンプ４を形成しており、図３の様にバンプ４を介し
て配線基板７にセラミック・パッケージ１を実装してい
る。半導体素子３は微小バンプ６、セラミックス基板２
の配線１０、バンプ４を介して配線基板７に実装され
る。FIG. 1 shows an embodiment of a ceramic package according to the present invention. Thickness is 0.1mm or more, 0.5mm
The semiconductor element 3 is fixed to the following ceramic substrate 2 by the minute bumps 6 and the sealing resin 5. A bump 4 is formed on the outer peripheral portion of a region where the semiconductor element 3 is fixed on the ceramic substrate 2, and the ceramic package 1 is mounted on a wiring board 7 via the bump 4 as shown in FIG. The semiconductor element 3 includes the minute bumps 6 and the ceramic substrate 2
Is mounted on the wiring board 7 via the wiring 10 and the bump 4.
【００１１】セラミックス基板２の基材には、材料特性
として熱膨張係数が半導体素子３と配線基板７の熱膨張
係数の中間値をもつものが使用できる。つまり、シリコ
ン素子の熱膨張係数をＶｃ、プリント配線基板の熱膨張
係数をＶｂとしたとき、Ｖｂ＝１６ｐｐｍ／℃のプリン
ト配線基板に実装する場合には、セラミックス基板の熱
膨張係数Ｖｓは４ｐｐｍ／℃以上、１０ｐｐｍ／℃以下
のものが好ましく、この範囲にある場合信頼性が著しく
改善される。As the base material of the ceramic substrate 2, a material having a thermal expansion coefficient having an intermediate value between the semiconductor element 3 and the wiring substrate 7 as a material property can be used. That is, assuming that the thermal expansion coefficient of the silicon element is Vc and the thermal expansion coefficient of the printed wiring board is Vb, when mounted on a printed wiring board of Vb = 16 ppm / ° C., the thermal expansion coefficient Vs of the ceramic substrate is 4 ppm / C. or more and 10 ppm / .degree. C. or less are preferable, and when it is in this range, the reliability is remarkably improved.
【００１２】また、基材の強度はセラミック・パッケー
ジの強度に大きく影響することから、抗折強度は１００
ＭＰａ以上の材料が望ましい。１００ＭＰａ以下の抗折
強度では、半導体素子３と配線基板７との熱膨張差に起
因する応力が発生した際にセラミックス基板２部分で破
壊が起こることから望ましくない。特に、２００ＭＰａ
以上３００ＭＰａ以下の範囲にある材料であれば、十分
な信頼性が得られる。Since the strength of the base material greatly affects the strength of the ceramic package, the transverse rupture strength is 100%.
A material of MPa or higher is desirable. A flexural strength of 100 MPa or less is not desirable because breakage occurs in the ceramic substrate 2 when a stress is generated due to a difference in thermal expansion between the semiconductor element 3 and the wiring board 7. In particular, 200MPa
If the material is in the range of not less than 300 MPa, sufficient reliability can be obtained.
【００１３】材料としては、アルミナ、窒化アルミニウ
ム、ムライト、コーディエライトまたはそれらとホウケ
イ酸ガラスとの複合体等が使用できるが、前述の特性を
満たす材料であれば、これらの材料に限定されるもので
はない。As the material, alumina, aluminum nitride, mullite, cordierite or a composite thereof with borosilicate glass can be used. However, as long as the material satisfies the above-mentioned characteristics, it is limited to these materials. Not something.
【００１４】セラミックス基板２のバンプ４を形成する
外周部の厚さは０．５ｍｍ以下、０．１ｍｍ以上である
ことが望ましい。これは０．５ｍｍ以上の厚さのセラミ
ックス基板２を使用した場合接続信頼性が著しく低下
し、一方セラミックス基板２の厚さを０．１ｍｍ以下と
した場合には、パッケージの強度が著しく低下するため
である。ただし、半導体素子を実装する部分に関しては
この厚さである必要はなく、セラミックス基板２の材料
として窒化アルミニウムといった熱伝導性の良いものを
使用した場合、半導体素子実装領域のセラミックス基板
２の厚さを外周部と比べて厚くすることで、信頼性を損
ねることなく放熱性を向上させることができる。The thickness of the outer peripheral portion of the ceramic substrate 2 on which the bumps 4 are formed is desirably 0.5 mm or less and 0.1 mm or more. This is because when the ceramic substrate 2 having a thickness of 0.5 mm or more is used, the connection reliability is significantly reduced. On the other hand, when the thickness of the ceramic substrate 2 is 0.1 mm or less, the strength of the package is significantly reduced. That's why. However, the thickness of the portion on which the semiconductor element is to be mounted does not need to be this thickness. When a material having good thermal conductivity such as aluminum nitride is used as the material of the ceramic substrate 2, the thickness of the ceramic substrate 2 in the semiconductor element mounting area is reduced. By increasing the thickness in comparison with the outer peripheral portion, the heat radiation can be improved without impairing the reliability.
【００１５】図３の様な実装形態の半導体装置を稼働さ
せた場合、通電時に半導体素子３自身が発熱し非通電時
に冷却されることにより、乃至は周辺環境からの熱の出
入りにより、又は使用する環境の温度変化により、セラ
ミック・パッケージ１は昇降温を繰り返すことになる。
半導体素子３と配線基板７の熱膨張係数が同じの場合に
は昇降温時に熱膨張によるひずみは発生しないが、汎用
的に使用されるプリント配線基板は半導体素子に比べ熱
膨張係数が大きく、熱膨張差に起因する応力が半導体素
子３と配線基板７との間に発生し、前述の昇降温を繰り
返すことによりバンプ４乃至は微小バンプ６に破断が発
生し、接続不良を起こすことになる。When the semiconductor device having the mounting form shown in FIG. 3 is operated, the semiconductor element 3 itself generates heat when energized and is cooled when not energized, or enters or exits heat from the surrounding environment, or is used. Due to the temperature change of the environment, the temperature of the ceramic package 1 repeatedly rises and falls.
If the semiconductor element 3 and the wiring board 7 have the same coefficient of thermal expansion, no distortion due to thermal expansion occurs when the temperature rises and falls, but the printed wiring board used for general purposes has a larger coefficient of thermal expansion than the semiconductor element, A stress due to the difference in expansion is generated between the semiconductor element 3 and the wiring board 7, and the above-described temperature increase and decrease are repeated, so that the bumps 4 or the minute bumps 6 are broken, thereby causing poor connection.
【００１６】熱膨張係数が半導体素子３と配線基板７の
中間であるセラミックスを用い、外周部の厚さを０．１
ｍｍ以上０．５ｍｍ以下のセラミックス基板２で図１に
示すような、半導体素子３の固定領域の外周部分にバン
プ４を備えたセラミック・パッケージ１を、図３のよう
に配線基板７に実装した場合、前述の昇降温によってバ
ンプ４乃至微小バンプ６が破断に至るまでの時間が長
く、乃至は破断に至るまでの昇降温の繰り返し回数が多
くなる。A ceramic having a coefficient of thermal expansion between the semiconductor element 3 and the wiring board 7 is used, and the thickness of the outer peripheral portion is set to 0.1.
As shown in FIG. 1, a ceramic package 1 having a bump 4 on an outer peripheral portion of a fixed region of a semiconductor element 3 was mounted on a wiring board 7 as shown in FIG. In this case, the time required for the bumps 4 to the minute bumps 6 to be broken by the above-mentioned temperature rise / fall is long, or the number of times of the temperature rise / fall until the fracture is broken increases.
【００１７】[0017]
【実施例】（実施例１）以下、本発明を実施例によりさ
らに説明するが、本発明はこれらに限定されるものでは
ない。EXAMPLES (Example 1) Hereinafter, the present invention will be further described with reference to examples, but the present invention is not limited thereto.
【００１８】図１のセラミック・パッケージ１におい
て、半導体素子３をおよそ１９ｍｍ×９ｍｍのシリコン
素子とし、セラミックス基板２を抗折強度２５０ＭＰ
ａ、熱膨張係数５ｐｐｍ／℃のガラスセラミックスで、
基板サイズおよそ２３ｍｍ×１４ｍｍ、厚さ０．４５ｍ
ｍ及び０．９ｍｍとして作製し、熱膨張係数が１６ｐｐ
ｍ／℃のプリント配線基板に実装したものを、−４０℃
に３０分保持後１２５℃に３０分保持することを１サイ
クルとする温度サイクル環境に設置し、故障に至るまで
のサイクル数を計測したところ、図５のように厚さ０．
９ｍｍのセラミック・パッケージが５００サイクルで故
障が発生するのに対し、厚さ０．４５ｍｍのセラミック
・パッケージは１０００サイクルで故障が発生した。In the ceramic package 1 shown in FIG. 1, the semiconductor element 3 is a silicon element of about 19 mm × 9 mm, and the ceramic substrate 2 has a bending strength of 250 MPa.
a, a glass ceramic with a coefficient of thermal expansion of 5 ppm / ° C,
Substrate size about 23mm x 14mm, thickness 0.45m
m and 0.9 mm, and has a thermal expansion coefficient of 16 pp
-40 ° C mounted on m / ° C printed wiring board
The temperature was set in a temperature cycle environment in which one cycle of holding at 30 ° C. and then holding at 125 ° C. for 30 minutes was measured, and the number of cycles up to failure was measured. As shown in FIG.
The 9 mm ceramic package failed in 500 cycles, while the 0.45 mm thick ceramic package failed in 1000 cycles.
【００１９】（実施例２）図２を参照にすると、バンプ
４は半導体素子３の外周の四辺に設けられており各辺の
応力によるひずみが互いに干渉しないように、切りかき
部１１が設けられている。バンプ４を形成できる領域面
積が増えることから、バンプ数を増加させることが出
来、Ｉ／Ｏピン数の多い半導体素子のパッケージとして
使用することが出来る。また、図４のように、半導体素
子３はセラミックス基板２にろう材８により固定され、
ワイヤーボンディング９によって接続させる構造として
も同様の効果が期待できる。(Embodiment 2) Referring to FIG. 2, the bumps 4 are provided on the four sides on the outer periphery of the semiconductor element 3, and the cutout portions 11 are provided so that the strains due to the stress on each side do not interfere with each other. ing. Since the area of the region where the bumps 4 can be formed increases, the number of bumps can be increased, and the semiconductor device can be used as a package of a semiconductor device having a large number of I / O pins. Further, as shown in FIG. 4, the semiconductor element 3 is fixed to the ceramic substrate 2 by a brazing material 8,
The same effect can be expected even when the structure is connected by the wire bonding 9.
【００２０】[0020]
【発明の効果】以上述べたように、本発明のセラミック
ス・パッケージは、昇降温サイクルによる破断に至るま
での時間を長くする、乃至は昇降温サイクル数を多くす
ることにより、製品寿命を長くする効果を有し、半導体
素子の高密度実装を可能にするとともに、接続信頼性の
低下を改善するセラミック・パッケージを提供できる。As described above, the ceramic package of the present invention prolongs the product life by increasing the time until breakage by the temperature rise / fall cycle or increasing the number of temperature rise / fall cycles. It is possible to provide a ceramic package which has an effect, enables high-density mounting of a semiconductor element, and improves deterioration of connection reliability.
【図１】本発明のセラミック・パッケージの一形態の概
略図である。FIG. 1 is a schematic view of one embodiment of the ceramic package of the present invention.
【図２】本発明のセラミック・パッケージの一形態の概
略図である。FIG. 2 is a schematic view of one embodiment of the ceramic package of the present invention.
【図３】本発明の実装形態を示す概略図である。FIG. 3 is a schematic diagram illustrating an implementation of the present invention.
【図４】本発明のセラミック・パッケージの一形態の概
略図である。FIG. 4 is a schematic view of one embodiment of the ceramic package of the present invention.
【図５】信頼性改善を示すグラフである。FIG. 5 is a graph showing an improvement in reliability.
１ セラミック・パッケージ ２ セラミックス基板 ３ 半導体素子 ４ バンプ ５ 封止樹脂 ６ 微小バンプ ７ 配線基板 ８ ろう材 ９ ワイヤーボンディング １０ 配線 １１ 切りかき部 DESCRIPTION OF SYMBOLS 1 Ceramic package 2 Ceramic substrate 3 Semiconductor element 4 Bump 5 Sealing resin 6 Micro bump 7 Wiring board 8 Brazing material 9 Wire bonding 10 Wiring 11 Cut-out part
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/13 H01L 23/12 H05K 1/18 Continuation of the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 23/13 H01L 23/12 H05K 1/18
Claims (6)
れ、さらに前記セラミックス基板が、前記半導体素子と
異なる熱膨張係数を有する配線基板に実装された構造よ
りなるセラミック・パッケージにおいて、 前記セラミックス基板は前記配線基板へバンプ接続によ
って実装されており、 前記バンプは前記セラミックス基板における半導体素子
実装領域の外周部分に形成されており、 少なくとも前記半導体素子実装領域の外周部分の前記セ
ラミックス基板の厚みは０．１ｍｍ以上０．５ｍｍ以下
であり、 かつ、前記セラミックス基板の熱膨張係数Ｖｓが前記半
導体素子の熱膨張係数Ｖｃと前記配線基板の熱膨張係数
Ｖｂの中間であることを特徴とするセラミック・パッケ
ージ。1. A ceramic package having a structure in which a semiconductor element is mounted on a ceramic substrate and the ceramic substrate is mounted on a wiring substrate having a different thermal expansion coefficient from the semiconductor element. The bumps are mounted on the substrate by bump connection, and the bumps are formed on an outer peripheral portion of the semiconductor element mounting area on the ceramic substrate, and a thickness of the ceramic substrate at least on an outer peripheral part of the semiconductor element mounting area is 0.1 mm or more. A ceramic package having a thermal expansion coefficient of 0.5 mm or less and a thermal expansion coefficient Vs of the ceramic substrate being intermediate between a thermal expansion coefficient Vc of the semiconductor element and a thermal expansion coefficient Vb of the wiring substrate.
ＭＰａ以上であることを特徴とする請求項１記載のセラ
ミック・パッケージ。2. The flexural strength of the ceramic substrate is 100.
2. The ceramic package according to claim 1, wherein the pressure is at least MPa.
を有し、かつバンプが四辺に形成されていることを特徴
とする請求項１または２記載のセラミック・パッケー
ジ。3. The ceramic package according to claim 1, wherein the ceramic substrate has cutouts on four sides and bumps are formed on the four sides.
セラミックス基板に搭載されていることを特徴とする請
求項１〜３のいずれかに記載のセラミック・パッケー
ジ。4. The ceramic package according to claim 1, wherein said semiconductor element is mounted on said ceramic substrate by fine bumps.
れていることを特徴とする請求項４記載のセラミック・
パッケージ。5. The ceramic chip according to claim 4, wherein said minute bump portion is sealed with a resin.
package.
アルミニウム、ムライト、コーディエライト、ホウケイ
酸ガラスのいずれか、もしくはこれらから選ばれた複数
の材料よりなる複合体よりなることを特徴とする請求項
１〜５のいずれかに記載のセラミック・パッケージ。6. The ceramic substrate according to claim 1, wherein the ceramic substrate is made of any one of alumina, aluminum nitride, mullite, cordierite, and borosilicate glass, or a composite of a plurality of materials selected from these. The ceramic package according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9926198A JP3031330B2 (en) | 1998-04-10 | 1998-04-10 | Ceramic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9926198A JP3031330B2 (en) | 1998-04-10 | 1998-04-10 | Ceramic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11297892A JPH11297892A (en) | 1999-10-29 |
| JP3031330B2 true JP3031330B2 (en) | 2000-04-10 |
Family
ID=14242777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9926198A Expired - Fee Related JP3031330B2 (en) | 1998-04-10 | 1998-04-10 | Ceramic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3031330B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7279787B1 (en) | 2001-12-31 | 2007-10-09 | Richard S. Norman | Microelectronic complex having clustered conductive members |
-
1998
- 1998-04-10 JP JP9926198A patent/JP3031330B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11297892A (en) | 1999-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2974552B2 (en) | Semiconductor device | |
| JP2671922B2 (en) | Semiconductor package | |
| JPH07221218A (en) | Semiconductor device | |
| WO1991003413A1 (en) | Package for an integrated circuit structure | |
| KR960012647B1 (en) | Semiconductor device and manufacture method | |
| JPH08507656A (en) | Device and method for reducing thermal cycling in a semiconductor package | |
| JPH1079405A (en) | Semiconductor device and electronic component mounting the same | |
| US6097085A (en) | Electronic device and semiconductor package | |
| JP2591499B2 (en) | Semiconductor device | |
| US6828676B2 (en) | Semiconductor device manufacturing method, semiconductor device, and semiconductor device unit | |
| JP2000031343A (en) | Semiconductor device | |
| JPH11284097A (en) | Semiconductor device | |
| EP0504669A1 (en) | Semiconductor device comprising a substrate | |
| JP3031330B2 (en) | Ceramic package | |
| US6784536B1 (en) | Symmetric stack up structure for organic BGA chip carriers | |
| JPH08264566A (en) | Package for mounting semiconductor element | |
| JPH07111278A (en) | Resin-sealed package and electronic circuit device | |
| JPH06196614A (en) | Lead frame | |
| JPH0529484A (en) | Ic chip mounting structure | |
| JP2531125B2 (en) | IC chip carrier module | |
| JPH08213498A (en) | Package made of ceramic | |
| JPH06204396A (en) | Semiconductor device | |
| JPH06291217A (en) | Heat dissipation type lead frame | |
| EP0646963A1 (en) | Multi-chip module and manufacturing method thereof | |
| JPH0697347A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20000111 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080210 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090210 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100210 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100210 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110210 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110210 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120210 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120210 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130210 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130210 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140210 Year of fee payment: 14 |
|
| LAPS | Cancellation because of no payment of annual fees |