JP3020523B2 - Figure exposure apparatus and method - Google Patents
Figure exposure apparatus and methodInfo
- Publication number
- JP3020523B2 JP3020523B2 JP1292332A JP29233289A JP3020523B2 JP 3020523 B2 JP3020523 B2 JP 3020523B2 JP 1292332 A JP1292332 A JP 1292332A JP 29233289 A JP29233289 A JP 29233289A JP 3020523 B2 JP3020523 B2 JP 3020523B2
- Authority
- JP
- Japan
- Prior art keywords
- exposure
- resist
- substrate
- wafer
- baking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
本発明はULSI製造などにおけるリソグラフィ技術に係
り、特に化学増幅系レジストを用いた制御性・安定性の
高いリソグラフィープロセスを実現する基板処理装置お
よび基板処理方法に関する。The present invention relates to a lithography technique in ULSI manufacturing and the like, and more particularly to a substrate processing apparatus and a substrate processing method for realizing a highly controllable and stable lithography process using a chemically amplified resist.
ULSIの高集積・高密度化は３年に４倍の勢いで進めら
れており、既に４メガビットdRAMの量産化および16メガ
ビットdRANの試作がなされている。これに伴って微細加
工に要求される寸法は0.8μｍから0.5μｍ、さらに0.5
μｍ以下へと益々微細化している。 リソグラフィ技術にはこうした素子微細化を牽引する
役割りがある。リソグラフィー技術では光・Ｘ線・電子
線等のエネルギー線を用いる。すなわちリソグラフィー
はこれらエネルギー線を感光性材料であるレジスト材料
に選択的に照射することによりレジスト内に潜像を形成
し、この後現像工程によりこれら潜像を実像とすること
によって下地材料を加工するレジストマスクを形成する
のが通常である。 従ってこれに使用されるレジスト材料には、 高解像性、 高感度、 高加工耐性、 の性能が要求される。ところが今までの一般のレジスト
材料にはこれら３要素を同時に高いレベルで満足するも
のがなく、要素に応じてレジスト材料を選択せざるをえ
ず、いずれかを犠牲にしていた。しかしながら最近，例
えばジャーナル オブ バキューム サイエンス アン
ド テクノロジー（J.Vac.Sci.Technol.）B6（１）,Jan
/Feb'88pp319−322,や、同誌同号pp379−383に示される
ような触媒の増感反応を利用した化学増幅系レジストが
考案された。 これはエネルギー線の照射によって触媒となる中間物
質が生成され、その後の加熱処理でレジスト反応を効率
的に促進するという、新しい機構を有するレジスト材料
である。この結果、従来レジストの高解像度・高加工耐
性は保ったまま、高い感度を実現することができる。こ
れはリソグラフィーにとって理想的なレジスト材料であ
る。また将来的にもこうした化学増幅系レジストはレジ
スト材料の主流としての位置付けがなされている。High integration and high density of ULSI have been advanced four times in three years, and mass production of 4 Mbit dRAM and trial production of 16 Mbit dRAN have already been made. Along with this, the dimensions required for micromachining are from 0.8 μm to 0.5 μm,
The size has been further reduced to μm or less. Lithography technology plays a role in driving such device miniaturization. In lithography technology, energy rays such as light, X-rays, and electron beams are used. In other words, lithography forms latent images in the resist by selectively irradiating these energy rays to a resist material, which is a photosensitive material, and then processes the underlying material by converting these latent images into real images in a developing step. Usually, a resist mask is formed. Therefore, the resist materials used for them are required to have high resolution, high sensitivity, and high processing resistance. However, there has been no conventional general resist material that satisfies these three factors at a high level at the same time, and has to select a resist material according to the components, sacrificing any of them. However, recently, for example, Journal of Vacuum Science and Technology (J.Vac.Sci.Technol.) B6 (1), Jan
/ Feb'88pp319-322, and a chemically amplified resist utilizing the sensitization reaction of a catalyst as shown in the same publication, pp379-383, have been devised. This is a resist material having a new mechanism in which an intermediate substance serving as a catalyst is generated by irradiation with energy rays, and the resist reaction is efficiently promoted by a subsequent heat treatment. As a result, high sensitivity can be realized while maintaining the high resolution and high processing resistance of the conventional resist. This is an ideal resist material for lithography. In the future, such chemically amplified resists will be positioned as mainstream resist materials.
ところが上記化学増幅系レジスト材料をULSI等の製造
工程に用いたところ大量枚数のウェハ間で図形寸法の変
動（細り）が生じ、安定で制御性の高いリソグラフィー
プロセスで実現できないことが判明した。以下第２図
（ａ）により上記現像を詳細に説明する。 一般にｎ枚のウェハを格納したカセット２のウェハ＃
１が図形露光部15に搬送される。次にウェハ＃１上に塗
布されたレジストに所定の図形が露光処理される。この
後ウエハ＃１は再びカセット２に搬送・格納される。次
にウェハ＃２が選択され上記ウェハ＃１と同様に一連の
処理がなされる。これを繰返しウェフ＃ｎまでの全ての
処理が完了することにより１バッチ単位の露光処理が終
了する。この後これらウェハ＃１〜＃ｎは第２図（ｂ）
に示す様に露光後ベーク・現像処理を経てレジストパタ
ーンが形成される。ところがこのシーケンスにおいてウ
ェハ＃１とウェハ＃ｎとの間で大幅なパターン寸法変化
が生じた。 第３図は各ウェハに露光した微細パターンの寸法設計
値からのズレ量を示したものである。図示したようにウ
ェハ間でパターン寸法に大きな違いがあることを見い出
した。このことは露光後からベーク処理までの時間がウ
ェハ＃１〜＃ｎで必然的に異なることに起因しており、
露光によってレジスト内に発生した触媒に経時変化が生
じるものと考えられる。化学増幅系レジストは感度・解
像度などの点で極めて高い性能を同時に実現できる理想
的なレジストであるが、上記現像により安定性・再現性
を問われるULSI製造工程には適用できないという問題が
生じた。 本発明は上記現象を踏まえ、上記化学増幅系レジスト
材料の不安定性を取り除き、安定性・再現性の高いULSI
製造工程を実現することを目的とする。However, when the above-mentioned chemically amplified resist material was used in the manufacturing process of ULSI or the like, it was found that a variation in figure size (thinning) occurred between a large number of wafers, and it was not possible to realize a stable and highly controllable lithography process. Hereinafter, the development will be described in detail with reference to FIG. Generally, wafer # of cassette 2 containing n wafers
1 is conveyed to the graphic exposure unit 15. Next, a predetermined figure is exposed on the resist applied on wafer # 1. Thereafter, wafer # 1 is transported and stored in cassette 2 again. Next, wafer # 2 is selected, and a series of processing is performed in the same manner as wafer # 1. This process is repeated until all processes up to the wafer #n are completed, thereby completing the exposure process in batches. Thereafter, these wafers # 1 to #n are combined as shown in FIG.
As shown in (1), a resist pattern is formed through baking and development after exposure. However, in this sequence, a significant pattern dimension change occurred between wafer # 1 and wafer #n. FIG. 3 shows the deviation from the dimension design value of the fine pattern exposed on each wafer. As shown in the figure, it has been found that there is a large difference in pattern dimensions between wafers. This is due to the fact that the time from the exposure to the baking process is inevitably different for wafers # 1 to #n.
It is considered that the catalyst generated in the resist by the exposure changes with time. Chemically amplified resist is an ideal resist that can simultaneously achieve extremely high performance in terms of sensitivity and resolution, but the above-mentioned development has caused a problem that it cannot be applied to ULSI manufacturing processes where stability and reproducibility are required. . The present invention, based on the above phenomenon, removes the instability of the chemically amplified resist material and provides a highly stable and reproducible ULSI
The purpose is to realize a manufacturing process.
上記目的を露光装置内あるいはその周辺にベーク装置
を配し上記レジスト材料の露光後からベーク処理までを
各試料毎に連続処理しこの間の経時変化を露光試料毎に
全て一定時間にすることにより達成される。The above object is achieved by arranging a baking device in or around the exposure apparatus, performing continuous processing from exposure of the resist material to baking for each sample, and changing the aging during this time to a fixed time for each exposure sample. Is done.
第１図（ａ）に示すように露光装置１の内部、あるい
は同図（ｂ）に示すようにその周辺にベーク装置４を設
けることにより露光後の各ウェハはベークまでの時間を
全て同一とすることができる。すなわち、第１図（ｃ）
に示すように露光とベーク処理とをウェハ毎に一貫して
処理することによりレジスト内の触媒の経時変化をウェ
ハ毎に一定にすればウェハ間のパターン寸法変動を解消
し安定性・再現性の高い化学増幅系レジスト利用のプロ
セスを実現できる。さらに露光後ベークを行なうまでの
経過時間を短くでき感度・解像度の高いパターニングが
可能となり、上記レジストの高い性能を引き出せること
にもなる。 なお、感放射線材料膜を塗布する基板はウエハ、マス
ク若しくはレチクルとすることができる。By providing a baking device 4 inside the exposure apparatus 1 as shown in FIG. 1 (a) or around it as shown in FIG. 1 (b), each exposed wafer has the same time until baking. can do. That is, FIG. 1 (c)
The exposure and bake process are performed consistently for each wafer as shown in the table, so that the aging of the catalyst in the resist is kept constant for each wafer, eliminating pattern dimensional variations between wafers and improving stability and reproducibility. A process using a highly chemically amplified resist can be realized. Furthermore, the elapsed time until the post-exposure bake is performed can be shortened, patterning with high sensitivity and resolution can be performed, and the high performance of the resist can be brought out. The substrate on which the radiation-sensitive material film is applied can be a wafer, a mask, or a reticle.
以下、本発明を実施例を用いて詳細に説明する。 〈実施例１〉 実施例１は電子線露光装置の露光室と交換室との間に
ホットプレートベーク機能を設けた例である。 第４図に該電子線露光装置の概要を示す。該電子線露
光装置は加速電圧30kVの可変成形ビーム型露光装置であ
る。露光試料は４インチSi基板上にネガ型化学増幅系レ
ジスト材料SAL601−ER7（シップレイ・マイクロエレク
トロニクス社）を0.5μｍ膜厚で塗膜形成した。露光予
定の１バッチ10枚全ての試料は第４図に示す試料待機室
に設置され、１枚ずつ交換室に搬送される。 該交換室を〜１μTorr以下の露光室と同程度の高真空
状態にした後、露光ステージへ搬送・固定し、照射量８
μC/cm2で所定の微細パターンを露光し、その潜像を形
成した。露光済みの該１枚目の試料は次にベーク装置に
搬送され110℃で２分間ベーク処理を行なった。この後
該試料を待機室の所定の場所に格納した。２枚目以降１
枚目と同様の手順で処理を行ない、露光予定の10枚全て
の該試料の処理を終了させた。次いで、現像液MF312
（シップレイ・マイクロエレクトロニクス社）にて現像
することによりパターン形成した。このレジストパター
ンの寸法の評価を走査型電子顕微鏡S6000（日立）を用
いて行なったところウェハ間寸法バラツキで0.02μm/10
枚の良好な値を得ることができた。 〈実施例２〉 実施例２は電子線露光装置の露光室と試料待機部との
間にベルト加熱式ベーク機能を設けた場合である。該ベ
ーク装置温度を110℃としベルト送り速度を0.15cm/sec
としたベーク処理により実施例１と同様の結果を得た。 〈実施例３〉 実施例３は波長248nmのKrFエキシマレーザ光による光
学式露光装置の露光部と試料待機部との間に赤外線加熱
ベーク機能を設けた。該ベーク装置を用いて10分間ベー
ク処理を行なったところ、この場合も実施例１と同様の
レジスト特性の経時変化抑制の改善効果を認めた。Hereinafter, the present invention will be described in detail with reference to examples. Embodiment 1 Embodiment 1 is an example in which a hot plate bake function is provided between an exposure chamber and an exchange chamber of an electron beam exposure apparatus. FIG. 4 shows an outline of the electron beam exposure apparatus. The electron beam exposure apparatus is a variable shaped beam type exposure apparatus with an acceleration voltage of 30 kV. As the exposure sample, a negative chemically amplified resist material SAL601-ER7 (Shipley Microelectronics) was formed on a 4-inch Si substrate to a thickness of 0.5 μm. All samples of 10 batches to be exposed are set in the sample waiting room shown in FIG. 4, and are transferred one by one to the exchange room. After the exchange chamber is brought into the same high vacuum state as the exposure chamber of 1 μTorr or less, it is transported and fixed to the exposure stage, and the irradiation amount is 8 μm.
A predetermined fine pattern was exposed at μC / cm 2 to form a latent image. The exposed first sample was then transported to a baking apparatus and baked at 110 ° C. for 2 minutes. Thereafter, the sample was stored in a predetermined place in the waiting room. 2nd and subsequent 1
The processing was performed in the same procedure as that of the sample, and the processing of all the samples to be exposed was completed. Next, the developer MF312
(Shipley Microelectronics) to develop a pattern. Evaluation of the dimensions of this resist pattern was performed using a scanning electron microscope S6000 (Hitachi).
A good number of sheets could be obtained. Example 2 Example 2 is a case where a belt heating bake function is provided between an exposure chamber of an electron beam exposure apparatus and a sample standby unit. The baking device temperature was 110 ° C. and the belt feed speed was 0.15 cm / sec.
As a result, the same result as in Example 1 was obtained. <Example 3> In Example 3, an infrared heating bake function was provided between an exposure unit of an optical exposure apparatus using a KrF excimer laser beam having a wavelength of 248 nm and a sample standby unit. When a baking treatment was performed for 10 minutes using the baking apparatus, the same effect of suppressing the temporal change of the resist characteristics as in Example 1 was observed in this case.
本発明によれば、高感度・高解像度・高ドライエッチ
ング耐性を有する化学増幅系レジスト材料固有の触媒の
経時変化現象に起因するウェハ間パターン寸法変動を回
避することができる。このため今後益々高集積化するUL
SIの半導体素子や超微細デバイスの製造を強力に推進す
るものとなる。ADVANTAGE OF THE INVENTION According to this invention, the pattern dimension variation between wafers resulting from the time-dependent change phenomenon of the catalyst peculiar to the chemically amplified resist material having high sensitivity, high resolution, and high dry etching resistance can be avoided. For this reason, UL will be increasingly integrated in the future
It will strongly promote the production of SI semiconductor elements and ultra-fine devices.
第１図（ａ）は本発明の実施例の露光装置の概略側断面
図、第１図（ｂ）は露光周辺部にベーク機能を設けた実
施例を示す概略側断面図、第１図（ｃ）は本発明を用い
た場合のレジストプロセスフローを説明する図、第２図
（ａ）は露光部と試料待機部からなる従来の露光装置の
概略側断面図、第２図（ｂ）は従来の露光装置を用いた
場合のレジストプロセスフローを示す図、第３図は従来
例において各ウェハに露光した微細パターンの寸法設計
値からのズレ量を示す図、第４図は露光室と試料交換室
との間にホットプレートベーク機能を設けた電子線露光
装置の概略側断面図である。 符号の説明 ２……カセット、３……試料（ウェハ）、４……ベーク
装置、５……ステージ、６……光源、７……電子線露光
部、８……試料待機部、９……ホットプレート、10……
バルブ、11……電子銃、15……図形露光部FIG. 1 (a) is a schematic side sectional view of an exposure apparatus according to an embodiment of the present invention, and FIG. 1 (b) is a schematic side sectional view showing an embodiment in which a bake function is provided in an exposure peripheral portion. FIG. 2C is a view for explaining a resist process flow when the present invention is used, FIG. 2A is a schematic side sectional view of a conventional exposure apparatus including an exposure section and a sample standby section, and FIG. FIG. 3 is a view showing a resist process flow when a conventional exposure apparatus is used, FIG. 3 is a view showing a deviation amount from a dimension design value of a fine pattern exposed on each wafer in a conventional example, and FIG. 4 is an exposure chamber and a sample; FIG. 2 is a schematic side sectional view of an electron beam exposure apparatus provided with a hot plate bake function between the exchange chamber and the hot plate bake function. DESCRIPTION OF SYMBOLS 2... Cassette 3... Sample (wafer) 4... Baking device 5... Stage 6. Light source 7 electron beam exposure unit 8 sample standby unit 9. Hot plate, 10 ……
Valve, 11 ... Electron gun, 15 ... Picture exposure unit
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡崎 信次 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 平２−82026（ＪＰ，Ａ) 特開 昭61−210628（ＪＰ，Ａ) 特開 昭63−31119（ＪＰ，Ａ) Ｊ．Ｖａｃ．Ｓｃｉ．Ｔｅｃｈｎｏ ｌ．Ｂ６（１），Ｊａｎ／Ｆｅｂ （1988），ｐｐ．319−322 Ｊ．Ｖａｃ．Ｓｃｉ．Ｔｅｃｈｎｏ ｌ．Ｂ６（１），Ｊａｎ／Ｆｅｂ （1988），ｐｐ．379−383 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/027 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shinji Okazaki 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. (56) References JP-A-2-82026 (JP, A) JP-A Sho 61-210628 (JP, A) JP-A-63-31119 (JP, A) Vac. Sci. Techno l. B6 (1), Jan / Feb (1988), pp. 319-322 Vac. Sci. Techno l. B6 (1), Jan / Feb (1988), pp. 379-383 (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/027
Claims (4)
装置を用いて、化学増幅系レジスト膜が形成された複数
の基板を基板毎に処理する基板処理方法であって、 前記露光部にて、エネルギー線を用いて、所望のパター
ンを前記基板上の化学増幅系レジスト膜に転写する露光
工程と、 前記基板を、引き続き前記ベーク処理部にて、現像前ベ
ークするベーク工程とを有し、 前記基板毎の、前記露光工程終了から前記ベーク工程開
始までの時間を、一定時間とすることを特徴とする基板
処理方法。1. A substrate processing method for processing a plurality of substrates on which a chemically amplified resist film is formed for each substrate using a substrate processing apparatus having an exposure unit and a bake processing unit, An exposure step of transferring a desired pattern to a chemically amplified resist film on the substrate using energy rays, and a baking step of baking the substrate before development in the bake processing unit. A time period from the end of the exposure step to the start of the bake step for each of the substrates, wherein the time is a fixed time.
徴とする請求項１記載の基板処理方法。2. The substrate processing method according to claim 1, wherein said energy beam is an electron beam.
とする請求項１記載の基板処理方法。3. The substrate processing method according to claim 1, wherein said energy rays are X-rays.
する請求項１記載の基板処理方法。4. The method according to claim 1, wherein the energy beam is light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1292332A JP3020523B2 (en) | 1989-11-13 | 1989-11-13 | Figure exposure apparatus and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1292332A JP3020523B2 (en) | 1989-11-13 | 1989-11-13 | Figure exposure apparatus and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03154324A JPH03154324A (en) | 1991-07-02 |
| JP3020523B2 true JP3020523B2 (en) | 2000-03-15 |
Family
ID=17780422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1292332A Expired - Lifetime JP3020523B2 (en) | 1989-11-13 | 1989-11-13 | Figure exposure apparatus and method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3020523B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2682437B2 (en) * | 1994-04-22 | 1997-11-26 | 日本電気株式会社 | Exposure method and apparatus |
| JPH10284360A (en) | 1997-04-02 | 1998-10-23 | Hitachi Ltd | Substrate temperature control equipment and method |
| US7679714B2 (en) * | 2006-10-12 | 2010-03-16 | Asml Netherlands B.V. | Lithographic apparatus, combination of lithographic apparatus and processing module, and device manufacturing method |
| JP5196775B2 (en) * | 2006-12-07 | 2013-05-15 | キヤノン株式会社 | Exposure apparatus and device manufacturing method |
| US8636458B2 (en) | 2007-06-06 | 2014-01-28 | Asml Netherlands B.V. | Integrated post-exposure bake track |
| US9891541B2 (en) | 2012-05-17 | 2018-02-13 | Asml Netherlands B.V. | Thermal conditioning unit, lithographic apparatus and device manufacturing method |
| JP6200238B2 (en) | 2013-08-20 | 2017-09-20 | 矢崎総業株式会社 | Wire harness |
-
1989
- 1989-11-13 JP JP1292332A patent/JP3020523B2/en not_active Expired - Lifetime
Non-Patent Citations (2)
| Title |
|---|
| Ｊ．Ｖａｃ．Ｓｃｉ．Ｔｅｃｈｎｏｌ．Ｂ６（１），Ｊａｎ／Ｆｅｂ（１９８８），ｐｐ．３１９−３２２ |
| Ｊ．Ｖａｃ．Ｓｃｉ．Ｔｅｃｈｎｏｌ．Ｂ６（１），Ｊａｎ／Ｆｅｂ（１９８８），ｐｐ．３７９−３８３ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03154324A (en) | 1991-07-02 |
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