JP3013632B2 - Manufacturing method of dielectric isolation substrate - Google Patents
Manufacturing method of dielectric isolation substrateInfo
- Publication number
- JP3013632B2 JP3013632B2 JP4282410A JP28241092A JP3013632B2 JP 3013632 B2 JP3013632 B2 JP 3013632B2 JP 4282410 A JP4282410 A JP 4282410A JP 28241092 A JP28241092 A JP 28241092A JP 3013632 B2 JP3013632 B2 JP 3013632B2
- Authority
- JP
- Japan
- Prior art keywords
- mask material
- voltage element
- substrate
- groove
- crystal silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、誘電体分離型の半導体
集積回路装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dielectric isolation type semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】誘電体絶縁分離基板内に高耐圧素子と低
耐圧素子を合わせて形成する場合、高耐圧素子を合わせ
て形成する場合、高耐圧素子の耐圧性を満足するため、
基板は高比抵抗で絶縁分離された単結晶シリコン島の島
の深さは、一般的に５０μｍ以上の深さが必要である。2. Description of the Related Art When a high breakdown voltage element and a low breakdown voltage element are formed together in a dielectric insulating isolation substrate, and when a high breakdown voltage element is formed together, the breakdown voltage of the high breakdown voltage element is satisfied.
In general, the depth of a single crystal silicon island in which a substrate is insulated and separated with a high specific resistance needs to be 50 μm or more.
【０００３】一方、低耐圧素子に要求される単結晶シリ
コン島の深さは２０μｍ程度で十分であるが、一般的な
製造工程の場合、低耐圧素子部も高耐圧素子部と同様の
深さとなり島の肩部に高濃度不純物拡散領域を設けても
コレクター直列抵抗が非常に大きい欠点があった。On the other hand, the depth of a single crystal silicon island required for a low-breakdown-voltage element is about 20 μm, but in a general manufacturing process, the low-breakdown-voltage element section has the same depth as the high-breakdown-voltage element section. However, even if a high-concentration impurity diffusion region is provided on the shoulder of the island, there is a disadvantage that the collector series resistance is very large.
【０００４】従来これに対応し高耐圧素子部の単結晶シ
リコン層のみを厚く低耐圧素子部の単結晶シリコン島を
薄く形成する技術として図３，図４に示す製造方法があ
る。Conventionally, there is a manufacturing method shown in FIGS. 3 and 4 as a technique for forming only a single crystal silicon layer in a high breakdown voltage element portion and a thin single crystal silicon island in a low breakdown voltage element portion.
【０００５】従来法では（１００）面を表面とする単結
晶シリコン基板１に図３（ａ）のようにマスク材２とし
ての熱酸化膜などをフォトリソグラフィ技術により所定
の領域を形成し、図２（ｂ）のようにエッチングにより
所望の深さｄ3 を有する逆台形溝３を最初に形成する。In the conventional method, a predetermined region is formed on a single crystal silicon substrate 1 having a (100) plane as a surface by a photolithography technique using a thermal oxide film or the like as a mask material 2 as shown in FIG. As shown in FIG. 2B, an inverted trapezoidal groove 3 having a desired depth d3 is first formed by etching.
【０００６】一般にこのエッチングは水酸化カリウム
（ＫＯＨ）水溶液などのアルカリ性水溶液による異方性
エッチが用いられる。Generally, anisotropic etching using an alkaline aqueous solution such as a potassium hydroxide (KOH) aqueous solution is used for this etching.
【０００７】次に上記単結晶シリコン基板の表面の所定
の位置に高耐圧素子部を形成するための所望の深さｄ1
の深い第１Ｖ字溝４をさらに低耐圧素子部となる逆台形
溝３の表面の所定の位置に所望の深さｄ2 の浅い第２Ｖ
字溝５をフォトリソグラフィ技術と異方性エッチング技
術とにより同時形成する。異方性エッチング後の断面は
図３（ｃ）のようで第１Ｖ字溝と第２Ｖ字溝の先端はほ
ぼ同一平面上にあるように形成されることが望ましい。Next, a desired depth d1 for forming a high breakdown voltage element portion at a predetermined position on the surface of the single crystal silicon substrate.
A first V-shaped groove 4 having a large depth is further formed at a predetermined position on the surface of the inverted trapezoidal groove 3 serving as a low withstand voltage element portion by a second V-shaped groove having a desired depth d2.
The groove 5 is formed simultaneously by photolithography and anisotropic etching. The cross section after anisotropic etching is as shown in FIG. 3 (c), and it is desirable that the tips of the first V-shaped groove and the second V-shaped groove are formed so as to be substantially on the same plane.
【０００８】次に図３（ｄ）のように高濃度不純物領域
６と、絶縁膜７を形成し、図４（ｅ）のように支持体と
しての多結晶シリコン層８を厚く積み、さらに研磨など
により第１Ｖ字溝４，第２Ｖ字溝５の先端部まで単結晶
を除去することにより、図４（ｆ）のように高耐圧素子
部となる深い単結晶シリコン島９と低耐圧素子部用の浅
い単結晶シリコン島１０を形成している。Next, as shown in FIG. 3D, a high-concentration impurity region 6 and an insulating film 7 are formed, and as shown in FIG. 4E, a polycrystalline silicon layer 8 as a support is thickly stacked and further polished. By removing the single crystal up to the end portions of the first V-shaped groove 4 and the second V-shaped groove 5 by a method such as that shown in FIG. The single crystal silicon island 10 shallow is formed.
【０００９】[0009]
【発明が解決しようする課題】しかしながら、上記した
従来の誘電体分離基板の製造工程において、低耐圧素子
部となる部分にＫＯＨ等のウェットによる異方性エッチ
ングにて段差約３０μｍの逆台形溝３を予め形成し（図
５（ａ））、次でホトリソ後、低耐圧素子部（島深さ２
０μｍ）、高耐圧素子部（島深さ５０μｍ）の第１・第
２Ｖ字溝４，５を同時に形成し（図５（ｂ），
（ｃ））、次で分離絶縁膜１５，多結晶シリコン層８を
生成後、単結晶シリコン側を研磨し、島深さの異なる単
結晶シリコン島９，１０が形成される（図５（ｄ））
が、低・高耐圧素子部境界Ｃ部ではシリコン島の崩れを
防ぐため、レジスト１１による分離余裕を広くする必要
が生じ、集積度の向上を妨げる原因となっており、これ
を避けるため、低・高耐圧各領域をチップ内で２分割し
た限定されたレイアウトになっている。However, in the above-described conventional manufacturing process of the dielectric isolation substrate, the inverted trapezoidal groove 3 having a step of about 30 .mu.m is wetted by anisotropic etching with KOH or the like in a portion to be a low breakdown voltage element portion. Is formed in advance (FIG. 5 (a)), and after photolithography, a low breakdown voltage element portion (island depth 2) is formed.
0 μm) and the first and second V-shaped grooves 4 and 5 of the high breakdown voltage element portion (island depth 50 μm) are simultaneously formed (FIG. 5B,
(C)) Next, after forming the isolation insulating film 15 and the polycrystalline silicon layer 8, the single crystal silicon side is polished to form single crystal silicon islands 9 and 10 having different island depths (FIG. 5 (d)). ))
However, in order to prevent the silicon island from collapsing at the low / high withstand voltage element boundary C, it is necessary to increase the separation margin by the resist 11, which hinders the improvement of the integration degree. -A limited layout in which each high withstand voltage region is divided into two in the chip.
【００１０】本発明の目的は、以上述べた誘電体分離基
板のチップ縮小化の妨げになっていた問題点を除去し、
分離精度の優れた誘電体分離基板の製造方法を提供する
ものである。[0010] An object of the present invention is to eliminate the above-mentioned problem that has hindered the miniaturization of the dielectric isolation substrate chip.
An object of the present invention is to provide a method for manufacturing a dielectric separation substrate having excellent separation accuracy.
【００１１】[0011]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る誘電体分離基板の製造方法は、逆台形
溝形成工程と、マスク材形成工程と、マスク材除去工程
と、垂直溝形成工程と、埋設工程と、支持体層形成工程
と、基板除去工程とを有し、半導体基板の表面の深い単
結晶シリコン島領域に高耐圧素子を形成し、浅い単結晶
シリコン島領域に低耐圧素子を形成する誘電体分離基板
の製造方法であって、逆台形溝形成工程は、単結晶シリ
コン基板の表面側に絶縁膜からなる第１のマスク材で異
方性エッチングにより高耐圧素子を分離するＶ字溝及び
低耐圧素子を配置する逆台形溝を形成するものであり、
マスク材形成工程は、前記第１のマスク材を除去後、絶
縁膜からなる第２のマスク材を形成するものであり、マ
スク材除去工程は、前記Ｖ字溝の先端領域及び前記逆台
形溝の底面部位領域に前記第２のマスク材の一部分を除
去するものであり、垂直溝形成工程は、前記第２のマス
ク材で異方性エッチングにより垂直溝を形成するもので
あり、埋設工程は、前記第２のマスク材を除去後、前記
垂直溝を分離絶縁膜で埋めるものであり、支持体層形成
工程は、前記絶縁膜上に多結晶シリコンの支持体層を形
成するものであり、基板除去工程は、前記単結晶シリコ
ン基板の裏面側を前記垂直溝の先端が露見するまで除去
するものである。In order to achieve the above object, a method of manufacturing a dielectric isolation substrate according to the present invention comprises an inverted trapezoidal groove forming step, a mask material forming step, a mask material removing step, and a vertical groove. Forming a high withstand voltage element in a deep single crystal silicon island region on the surface of the semiconductor substrate, and forming a low breakdown voltage element in a shallow single crystal silicon island region. A method of manufacturing a dielectric isolation substrate for forming a high-voltage element, wherein the reverse trapezoidal groove forming step includes forming a high-voltage element by anisotropic etching with a first mask material made of an insulating film on a surface side of a single-crystal silicon substrate. Forming a V-shaped groove for separation and an inverted trapezoidal groove for arranging the low withstand voltage element;
In the mask material forming step, after the first mask material is removed, a second mask material made of an insulating film is formed. The mask material removing step includes a step of forming a tip region of the V-shaped groove and the reverse trapezoidal groove. Removing a part of the second mask material in the bottom region region of the substrate. The vertical groove forming step includes forming a vertical groove by anisotropic etching with the second mask material. Removing the second mask material, filling the vertical groove with an isolation insulating film, and forming a support layer in the support layer forming a polycrystalline silicon support layer on the insulating film. In the substrate removing step, the back surface of the single crystal silicon substrate is removed until the tip of the vertical groove is exposed.
【００１２】[0012]
【作用】単結晶シリコン基板１２の表面に第１のマスク
材としてアルカリ水溶液による異方性エッチングにより
高耐圧素子を分離するＶ字溝１５及び低耐圧素子を配置
する逆台形溝１６を形成し、さらに第２のマスク材とし
て反応性イオンエッチングによる異方性エッチングによ
りＶ字溝の先端領域２０及び逆台形溝底面部領域２１に
垂直溝２３を形成する。このため、低・高耐圧素子部境
界の分離余裕を広くする必要がなく、隣合う素子分離領
域間の寸法を従来の２０〜５０μｍから５μｍ以下への
設定ができるので、単結晶シリコン島領域の縮小が可能
となり大幅なチップ縮小化を図ることができる。A V-shaped groove 15 for isolating a high-voltage element and an inverted trapezoidal groove 16 for disposing a low-voltage element are formed on the surface of a single-crystal silicon substrate 12 as a first mask material by anisotropic etching with an aqueous alkali solution. Further, vertical grooves 23 are formed in the tip region 20 of the V-shaped groove and the bottom region 21 of the inverted trapezoidal groove by anisotropic etching using reactive ion etching as a second mask material. For this reason, it is not necessary to widen the isolation margin at the boundary between the low and high withstand voltage element portions, and the dimension between the adjacent element isolation regions can be set from 20 to 50 μm to 5 μm or less from the conventional size. The size can be reduced, and the chip can be significantly reduced.
【００１３】[0013]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は、本発明の実施例を示す
誘電体分離基板の製造工程断面図である。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a process of manufacturing a dielectric isolation substrate according to an embodiment of the present invention.
【００１４】まず、図１（ａ）に示すように例えばＮ型
（１００）結晶方位面を有する単結晶シリコン基板１２
の主表面側を酸化し、通常のホトリソ・エッチングによ
り熱酸化膜パターン１１を形成する。次に図１（ｂ）に
示すように熱酸化膜パターン１３にマスクとして単結晶
シリコン基板１２の主表面のシリコン露出部１４を例え
ば、ＫＯＨ，ＮａＯＨ，ヒドラジン等のアルカリ異方性
エッチングにて異方性エッチングを行なって高耐圧素子
を分離するＶ字溝１５及び低耐圧素子を分離する逆台形
溝１６を形成する。First, as shown in FIG. 1A, for example, a single-crystal silicon substrate 12 having an N-type (100) crystal orientation plane
Is oxidized, and a thermal oxide film pattern 11 is formed by ordinary photolithographic etching. Next, as shown in FIG. 1 (b), the exposed silicon portion 14 on the main surface of the single crystal silicon substrate 12 is used as a mask for the thermal oxide film pattern 13 by, for example, an alkali anisotropic etching of KOH, NaOH, hydrazine or the like. Anisotropic etching is performed to form a V-shaped groove 15 for separating a high breakdown voltage element and an inverted trapezoidal groove 16 for separating a low breakdown voltage element.
【００１５】次に図１（ｃ）に示すようにパターン形成
した熱酸化膜パターン１３をすべて除去し、単結晶シリ
コン基板１２の主表面側にマスク材として再度熱酸化膜
１７を形成する。次に図１（ｄ）に示すようにレジスト
１８を形成し、マスク１９を合わせて露光する。さらに
現像し、高耐圧素子形成領域を分離する所望のＶ字溝１
５の先端領域２０と低耐圧素子形成領域を分離する所望
の逆台形溝１６の底面部２１両端（低耐圧素子の分離境
界）と内部領域のレジスト１８を約５μｍ程度除去す
る。Next, as shown in FIG. 1C, the patterned thermal oxide film pattern 13 is entirely removed, and a thermal oxide film 17 is formed again as a mask material on the main surface side of the single crystal silicon substrate 12. Next, a resist 18 is formed as shown in FIG. Further developing, a desired V-shaped groove 1 for separating the high breakdown voltage element formation region
5 is removed by about 5 μm in both ends of the bottom portion 21 (separation boundary of the low breakdown voltage element) of the desired inverted trapezoidal groove 16 for separating the low breakdown voltage element formation region from the tip region 20 of the fifth breakdown region.
【００１６】次いで図２（ｅ）に示すように熱酸化膜２
２をマスクとして反応性イオンエッチング等のドライ式
による異方性エッチングを行ない、例えば２０μｍの深
さの垂直溝２３を形成する。次に図２（ｆ）に示すよう
に、単結晶シリコン基板１２に形成した垂直溝２３を例
えばＴＥＯＳ（テトラエチルオルソシケイト）ＣＶＤＳ
ｉＯ2 で埋め込む。その後、単結晶シリコン基板１２の
Ｖ字溝１５と逆台形溝１６を形成した主表面側に支持体
層として多結晶シリコン層２４を形成する。Next, as shown in FIG.
Anisotropic etching such as reactive ion etching or the like is performed by using 2 as a mask to form a vertical groove 23 having a depth of, for example, 20 μm. Next, as shown in FIG. 2 (f), a vertical groove 23 formed in the single crystal silicon substrate 12 is formed, for example, by TEOS (tetraethylorthosilicate) CVDS.
filled with iO 2. Thereafter, a polycrystalline silicon layer 24 is formed as a support layer on the main surface side of the single crystal silicon substrate 12 where the V-shaped groove 15 and the inverted trapezoidal groove 16 have been formed.
【００１７】しかる後、単結晶シリコン基板１２の主表
面に平行となるように多結晶シリコン層２４を点線ａ−
ａ′で示した位置まで除去し、さらに単結晶シリコン基
板１２の反対側の主表面を垂直溝２３の先端２５が露見
する点線ｂ−ｂ′で示した位置まで研磨除去及び仕上げ
研磨することによって図２（ｇ）に示すように、分離絶
縁膜２６で囲まれた高耐圧素子の単結晶シリコン島２７
と低耐圧素子の単結晶シリコン島２８を有する誘電体分
離基板を得る。Thereafter, the polycrystalline silicon layer 24 is dashed so as to be parallel to the main surface of the single crystal silicon substrate 12.
a ', and the main surface on the opposite side of the single-crystal silicon substrate 12 is further polished to the position shown by a dotted line bb' exposed by the tip 25 of the vertical groove 23 and finish-polished. As shown in FIG. 2G, a single crystal silicon island 27 of a high breakdown voltage element surrounded by an isolation insulating film 26 is formed.
And a dielectric isolation substrate having a single crystal silicon island 28 of a low breakdown voltage element.
【００１８】[0018]
【発明の効果】以上説明したように本発明によれば、単
結晶シリコン基板１に第１のマスク材としてアルカリ水
溶液による異方性エッチングにより高耐圧素子を分離す
るＶ字溝低耐圧素子を配置する逆台形溝を形成し、さら
に第２のマスク材として反応性イオンエッチングによる
異方性エッチングによりＶ字溝の先端領域及び逆台形溝
底面部領域に垂直溝を形成することで低・高耐圧素子部
境界の分離余裕を広くする必要がなく、隣合う素子分離
領域間の寸法を従来の２０〜５０μｍから５μｍ以下へ
の設定ができ、単結晶シリコン島領域の縮小化が可能と
なり、大幅なチップの縮小化を図ることができる。As described above, according to the present invention, a V-shaped groove low-breakdown-voltage element for separating a high-breakdown-voltage element by anisotropic etching with an alkaline aqueous solution is disposed on a single-crystal silicon substrate 1 as a first mask material. Forming a vertical groove in the tip region of the V-shaped groove and the bottom region of the reverse trapezoidal groove by anisotropic etching by reactive ion etching as a second mask material, thereby forming a low / high withstand voltage. There is no need to widen the isolation margin at the element boundary, the size between adjacent element isolation regions can be set from 20 to 50 μm to 5 μm or less, and the single crystal silicon island region can be reduced. Chips can be reduced in size.
【００１９】更に、低・高耐圧素子領域をチップ内で２
分割して、低・高耐圧素子を混載した自由度の高いレイ
アウトを行うことができる。Further, a low / high withstand voltage element region is formed within the chip by two.
By dividing the layout, a layout having a high degree of freedom in which low and high withstand voltage elements are mixed can be performed.
【図１】本発明の実施例を示す誘電体分離基板の製造工
程断面図である。FIG. 1 is a cross-sectional view illustrating a process of manufacturing a dielectric isolation substrate according to an embodiment of the present invention.
【図２】本発明の実施例を示す誘電体分離基板の製造工
程断面図である。FIG. 2 is a cross-sectional view illustrating a process of manufacturing a dielectric isolation substrate according to an embodiment of the present invention.
【図３】従来の誘電体分離基板の製造工程断面図であ
る。FIG. 3 is a cross-sectional view showing a manufacturing process of a conventional dielectric isolation substrate.
【図４】従来の誘電体分離基板の製造工程断面図であ
る。FIG. 4 is a cross-sectional view illustrating a manufacturing process of a conventional dielectric isolation substrate.
【図５】従来の誘電体分離基板の欠点を説明する製造工
程断面図である。FIG. 5 is a cross-sectional view showing a manufacturing process for explaining a defect of a conventional dielectric isolation substrate.
１２ 単結晶シリコン基板 １３ 熱酸化膜パターン １４ シリコン露出部 １５ Ｖ字溝 １６ 逆台形溝 １７，２３ 熱酸化膜 １８ レジスト １９ マスク ２０ Ｖ字溝の先端領域 ２１ 逆台形溝の底面部 ２３ 垂直溝 ２４ 多結晶シリコン層 ２５ 垂直溝の先端 ２６ 分離絶縁膜 ２７ 高耐圧素子部シリコン島 ２８ 低耐圧素子部シリコン島 REFERENCE SIGNS LIST 12 single crystal silicon substrate 13 thermal oxide film pattern 14 silicon exposed portion 15 V-shaped groove 16 inverted trapezoidal groove 17, 23 thermal oxide film 18 resist 19 mask 20 tip region of V-shaped groove 21 bottom portion of inverted trapezoidal groove 23 vertical groove 24 Polycrystalline silicon layer 25 End of vertical groove 26 Isolation insulating film 27 High breakdown voltage element part silicon island 28 Low breakdown voltage element part silicon island
Claims (1)
と、マスク材除去工程と、垂直溝形成工程と、埋設工程
と、支持体層形成工程と、基板除去工程とを有し、半導
体基板の表面の深い単結晶シリコン島領域に高耐圧素子
を形成し、浅い単結晶シリコン島領域に低耐圧素子を形
成する誘電体分離基板の製造方法であって、 逆台形溝形成工程は、単結晶シリコン基板の表面側に絶
縁膜からなる第１のマスク材で異方性エッチングにより
高耐圧素子を分離するＶ字溝及び低耐圧素子を配置する
逆台形溝を形成するものであり、 マスク材形成工程は、前記第１のマスク材を除去後、絶
縁膜からなる第２のマスク材を形成するものであり、 マスク材除去工程は、前記Ｖ字溝の先端領域及び前記逆
台形溝の底面部位領域に前記第２のマスク材の一部分を
除去するものであり、 垂直溝形成工程は、前記第２のマスク材で異方性エッチ
ングにより垂直溝を形成するものであり、 埋設工程は、前記第２のマスク材を除去後、前記垂直溝
を分離絶縁膜で埋めるものであり、 支持体層形成工程は、前記絶縁膜上に多結晶シリコンの
支持体層を形成するものであり、 基板除去工程は、前記単結晶シリコン基板の裏面側を前
記垂直溝の先端が露見するまで除去するものであること
を特徴とする誘電体分離基板の製造方法。1. A semiconductor device comprising an inverted trapezoidal groove forming step, a mask material forming step, a mask material removing step, a vertical groove forming step, a burying step, a support layer forming step, and a substrate removing step. A method for manufacturing a dielectric isolation substrate in which a high withstand voltage element is formed in a deep single crystal silicon island region on a surface of a substrate and a low withstand voltage element is formed in a shallow single crystal silicon island region. Forming a V-shaped groove for isolating a high breakdown voltage element and an inverted trapezoidal groove for disposing a low breakdown voltage element by anisotropic etching with a first mask material made of an insulating film on the surface side of the crystalline silicon substrate; In the forming step, after the first mask material is removed, a second mask material made of an insulating film is formed. In the mask material removing step, the tip region of the V-shaped groove and the bottom surface of the inverted trapezoidal groove are formed. A part of the second mask material in the region of the region In the vertical groove forming step, a vertical groove is formed by anisotropic etching with the second mask material, and the embedding step includes removing the second mask material and then removing the vertical groove. The groove is filled with an isolation insulating film. The supporting layer forming step is for forming a supporting layer of polycrystalline silicon on the insulating film. The substrate removing step is a back side of the single crystal silicon substrate. Is removed until the end of the vertical groove is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4282410A JP3013632B2 (en) | 1992-09-28 | 1992-09-28 | Manufacturing method of dielectric isolation substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4282410A JP3013632B2 (en) | 1992-09-28 | 1992-09-28 | Manufacturing method of dielectric isolation substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06112307A JPH06112307A (en) | 1994-04-22 |
| JP3013632B2 true JP3013632B2 (en) | 2000-02-28 |
Family
ID=17652053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4282410A Expired - Lifetime JP3013632B2 (en) | 1992-09-28 | 1992-09-28 | Manufacturing method of dielectric isolation substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3013632B2 (en) |
-
1992
- 1992-09-28 JP JP4282410A patent/JP3013632B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06112307A (en) | 1994-04-22 |
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