JP3008900B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3008900B2 JP3008900B2 JP9210636A JP21063697A JP3008900B2 JP 3008900 B2 JP3008900 B2 JP 3008900B2 JP 9210636 A JP9210636 A JP 9210636A JP 21063697 A JP21063697 A JP 21063697A JP 3008900 B2 JP3008900 B2 JP 3008900B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- heat
- power
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000020169 heat generation Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 37
- 238000009792 diffusion process Methods 0.000 description 23
- 239000000758 substrate Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 5
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Measuring Temperature Or Quantity Of Heat (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体装置に係り、
特に温度検出機能を有する半導体装置に関するものであ
る。
【０００２】
【従来の技術】能動機能をもつ半導体素子の動作時の異
常な接合温度上昇による破壊をさける為に、従来では同
一半導体基板内に能動機能をもつ半導体素子と、例えば
感熱サイリスタ等の感熱素子を形成し、感熱素子により
半導体基板の温度を検出し、その検出信号により半導体
素子を制御して熱破壊しないように保護している。
【０００３】
【発明が解決しようとする課題】しかしながら、この従
来の温度検出機能では、半導体基板内における半導体素
子と感熱素子との配置位置関係については特に考慮され
ておらず、半導体素子として複数のＭＯＳ型の単位セル
の集合からなるパワー素子が形成される場合、感熱素子
の位置によっては半導体素子を熱破壊から保護するのに
は不充分となる等の問題がある。
【０００４】そこで本発明は上記の点に鑑みて創案され
たもので、半導体素子を熱破壊から確実に保護すること
のできる半導体装置を提供する事を目的とする。
【０００５】
【課題を解決するための手段】上記目的を達成する為に
本発明の半導体装置は、その導通状態の際に電流が流れ
ることで高熱を発する半導体パワー素子が形成された半
導体チップにおいて、該半導体チップの前記半導体パワ
ー素子のレイアウトされる領域の内側の領域の表面に絶
縁膜を介して、前記半導体パワー素子の発熱状況を検出
する感熱素子部を配置することを特徴とする。
【０００６】
【作用及び発明の効果】本発明は前記の構成により、半
導体基板の温度が異常に上昇した時、すなわち半導体パ
ワー素子の発熱温度が異常に高くなった時には、この温
度上昇を感熱素子部で検出することができる。この際、
感熱素子の集積化に起因する寄生動作をなくすことがで
き、さらに感熱素子部は半導体パワー素子がレイアウト
される領域の内側の領域，すなわち半導体パワー素子に
囲まれて放熱性が低く、半導体チップの中でも比較的温
度のあがりやすい領域に配置されているので、該領域の
温度を感熱素子部にて検出して半導体パワー素子の導通
制御を行うようにすれば半導体パワー素子を確実に熱破
壊から保護することのできるようになる。
【０００７】
【実施例】以下、本発明を図に示す実施例により詳述す
る。図１及び図２は自己過熱保護機能を有する縦形パワ
ーＭＯＳトランジスタ（以下、パワーＭＯＳという）に
応用した例であって、図１にその半導体チップの模式的
平面図を示す。また図２に図１中のα−α断面図を示
す。半導体基板Ａの全体の大部分に能動素子であるパワ
ーＭＯＳ１３が複数個並列接続してマルチソース構造と
なりパワー領域Ｍを形成している。半導体基板Ａの中央
部、言い換えれば最も放熱しにくい部分で、温度が高く
成り易い部分に感熱素子としての多結晶シリコンダイオ
ード１５を複数個直列接続して形成し、その周辺に制御
部としての横形ＭＯＳトランジスタ１４、多結晶シリコ
ン抵抗１６、定電圧ツェナダイオード１７を形成し、全
体として制御領域Ｃを形成する。また、半導体基板Ａ上
には外部から電圧（Ｖin）を印加する為のボンディング
パッド部Ｂを形成する。これらパワー領域Ｍ及び制御領
域Ｃの各素子及びボンディングバッド部Ｂは電気的に互
いに接続される。
【０００８】次に図２において、その構成を詳しく説明
する。１はＮ+ 形のシリコン基板、２はＮ- 形のシリコ
ンエピタキシャル層、３及び３ａは深く拡散したＰ形拡
散層、４はＰ形拡散層、５，５ａ，５ｂ及び５ｃはＮ+
形拡散層、１１はＰ+ 形拡散層であり、Ｐ形拡散層３と
３ａ、Ｎ+ 形拡散層５，５ａ，５ｂ及び５ｃはそれぞれ
同時に同じ拡散行程で形成される。パワーＭＯＳ１３の
ＭＯＳ構造は、シリコンピタキシャル層２とシリコン基
板１とドレイン電極１２から成るドレインＤと、ゲート
酸化膜６を介して形成される多結晶シリコン層７から成
るゲートＧと、その表面に層間絶縁膜８を介しパワーＭ
ＯＳ１３表面全体を覆うアルミニウム電極９から成るソ
ースＳとから構成され、その動作はゲートＧに電圧を印
加すると図中ｃｈの部分にＮ形のチャネルが形成されソ
ースＳとドレインＤ間に電流が流れる。尚、拡散層４と
拡散層３が一部重なって、しかも拡散層３が深く拡散し
ているのは過電圧保護の為であり、所定のブレークダウ
ン電圧に設定する為である。次に横形ＭＯＳトランジス
タ１４のＭＯＳ構造は拡散層５ａ及び５ｂ上のアルミニ
ウム電極９ａ及び９ｂから成るそれぞれソースＳ１及び
ドレインＤ１と、ゲート酸化膜６ａを介して形成される
多結晶シリコン層７ａから成るゲートＧ１とから構成さ
れ、その動作はゲートＧ１に電圧がかかると図中ｃｈ１
の部分にＮ形のチャネルが形成されソースＳ１とドレイ
ンＤ１間に電流が流れる。定電圧ツェナダイオード１７
は拡散層５ｃと拡散層１１とから形成され、その表面に
それぞれアルミニウム電極９ｃ及び９ｄを形成する。次
に拡散層３ａ表面上の一部を熱酸化して絶縁膜（ＳｉＯ
2 膜等）１０を形成する。そして絶縁膜１０上に多結晶
シリコン抵抗１６と、感熱素子としての多結晶シリコン
ダイオード１５を形成する。多結晶シリコン抵抗１６
は、多結晶シリコン層７ｃと層間絶縁膜８とアルミニウ
ム電極９ｇ及び９ｈから形成される。また、多結晶シリ
コンダイオード１５は多結晶シリコン層７ｂを選択的拡
散しＰＮ接合をつくり、その上に層間絶縁膜８を一部介
しアルミニウム電極９ｅ及び９ｆを形成する。以上述べ
た実施例の構成でゲート酸化膜６と６ａ、多結晶シリコ
ン層７，７ａ，７ｂ，７ｃ，アルミニウム電極９，９
ａ，９ｂ，９ｃ，９ｄ，９ｅ，９ｇ，９ｈはそれぞれ同
じ工程で造る事が出来る。また前記の各素子は、図３に
示す等価回路図にあるように互いに配線される。
【０００９】尚、各々の素子は例えば図１１の上面図に
示すように配置される。すなわち、制御領域Ｃには横形
ＭＯＳトランジスタ１４、多結晶シリコンダイオード１
５、抵抗１６Ｃ，定電圧ツェナーダイオード１７が配置
しており、パワー領域の表面を覆うアルミニウム電極９
とその各々は接続路Ｃ１を経由して電気接続される。図
中、２０は図３中における２０と同じ点であり、アルミ
ニウム電極９の外部接続端子を表わす。ここで、定電圧
ツェナダイオード１７の陽極に電気接続する外部接続端
子２０は接地電位に固定されている。従って、図２に示
されるように、定電圧ツェナダイオード１７の拡散層１
１に電気接続するＰ形拡散層３ａも接地電位に固定され
る。又、ボンディングパッド部Ｂに印加される電圧の一
部はその横に配置する抵抗１６ｂを介してパワーＭＯＳ
１３のゲート電極Ｇ１あるいは横型ＭＯＳトランジスタ
１４のドレインＤ１に加わり、他は同じく横に配置する
抵抗１６ａ等を介して横形ＭＯＳトランジスタ１４のゲ
ートＧ１に加わる。
【００１０】次に、図３の等価回路図を用いて全体の動
作を説明する。図において符号は図１及び図２と共通で
ある。但し、１６ａ，１６ｂ，１６ｃは多結晶シリコン
抵抗、ＲL は外部の負荷抵抗、ＶDDは外部電源である。
シリコン基板温度が通常温度の時、すなわちパワーＭＯ
Ｓ１３の接合温度が通常温度の時には印加された電圧Ｖ
inによりパワーＭＯＳ１３はオン状態となっているが、
シリコン基板温度が異常に高い時、すなわちパワーＭＯ
Ｓ１３の接合温度が異常に上昇した時には感熱素子であ
る多結晶シリコンダイオード１５の順方向電圧は一定の
負の温度係数を持つ為に低下し、抵抗１６ｃの端子間電
圧（すなわち、横形ＭＯＳトランジスタ１４のゲートＧ
１−ソースＳ１間電圧）が上昇する。一定の電圧以上に
なると横形ＭＯＳトランジスタ１４がオン状態となる。
抵抗１６ｂ抵抗値を横形ＭＯＳトランジスタ１４のオン
抵抗値より十分に大きくしておけば、図４の２２の電位
Ｖ 22及び２３の電位Ｖ23の接合温度による変化を表すグ
ラフに示すように接合温度１３０℃近辺（保護動作温
度）でＶ22はほぼ０Ｖまで急激に下がるのでパワーＭＯ
Ｓ１３は強制的にオフ状態となり、接合温度上昇による
素子の破壊をさける事が出来る。
【００１１】上記の実施例の構成によれば、絶縁膜１０
を形成する事により、個別素子のトリミングが可能な、
しかも寄生動作がない半導体装置を提供する事ができ、
またパワーＭＯＳ１３の接合温度の異常な上昇が、感熱
素子を温度の高く成り易い中央部の制御領域Ｃに配置す
るのでより正確に検出でき、また、製造工程が同時に同
じ工程で行えるので簡単となり、コストダウンにもつな
がり、さらに絶縁膜上の多結晶シリコン抵抗１６ｃの抵
抗値及び、多結晶シリコンダイオード１５の直列接続数
により保護動作温度を任意に設定出来る。多結晶シリコ
ン抵抗１６ｃの抵抗値を個別にトリミング出来る為、製
造後に保護動作温度を精密に制御出来る等という優れた
効果がある。
【００１２】又、シリコンエピタキシャル層２はパワー
ＭＯＳ１３のドレインの一部を構成しているのでパワー
ＭＯＳ１３の動作状態に応じてその電位が変化し、その
上に形成されている多結晶シリコンダイオード１５の温
度検出精度を悪化させるように作用する可能性がある
が、本実施例によると、シリコンエピタキシャル層２内
にＰ形拡散層３ａを形成し、その上に絶縁膜１０を介し
て多結晶シリコンダイオード１５を形成しているのでこ
のような不具合をなくすことができる。この点について
詳述すると、仮に、Ｐ形拡散層３ａがない構造を想定す
ると、シリコンエピタキシャル層２の電位に応じて絶縁
膜（ＳｉＯ2 膜等）１０が分極し、多結晶シリコンダイ
オード１５の絶縁膜１０側表面に電荷が誘起されてしま
う。本実施例の場合には、例えばシリコンエピタキシャ
ル層２が高電位になると、多結晶シリコンダイオード１
５のＰＮ接合部における不純物濃度が変化してしまい、
その順方向電圧における温度特性が変化して温度検出の
精度が悪化してしまう。極端な場合、多結晶シリコンダ
イオード１５のＰ形領域下部に反転層が形成されてしま
いＭＯＳトランジスタのような寄生動作をしてしまうの
で、もはや温度検出が不可能になる。
【００１３】本実施例によると、多結晶シリコンダイオ
ード１５下にＰ形拡散層３ａを形成しているので、Ｐ形
拡散層３ａとシリコンエピタキシャル層２との間にＰＮ
接合が形成され、パワーＭＯＳ１３のドレイン電位から
電気的に分離することができるので、多結晶シリコンダ
イオード１５はドレイン電位の影響を受けることがな
く、上述のような寄生動作をなくすことができ、より精
度が高い温度検出を行うことができるという効果があ
る。
【００１４】尚、本発明は上記の実施例に限定されず、
以下の如く種々変形可能である。
（１）制御領域Ｃの素子は全て絶縁膜１０上に形成して
もよく、図５の第２の実施例に示す様に横形ＭＯＳトラ
ンジスタ１４ａを絶縁膜１０上に形成し、定電圧ツェナ
ダイオード１７だけを拡散層３ａ内に形成してもよい。
また逆に、横形ＭＯＳトランジスタ１４ａを拡散層３ａ
内に、定電圧ツェナダイオード１７を絶縁膜１０上に形
成してもよい。この他に多結晶シリコン抵抗１６を拡散
層３ａ内に形成してもよい。
【００１５】（２）図６の第３の実施例としての図１に
おけるα−α断面図、及びその等価回路図である図７に
示すように、絶縁膜１０上にＰ形チャネルＭＯＳトラン
ジスタ２４（２４ａ，２４ｂ，２４ｃ）、及びＮ形チャ
ネルＭＯＳトラジスタ２５（２５ａ，２５ｂ）を形成
し、相補形ＭＯＳトランジスタ（Ｃ−ＭＯＳ）を構成し
て２２の電位Ｖ22を増幅して２６の電位Ｖ26としてもよ
い。又、絶縁膜１０上にＰ形チャネルＭＯＳトランジス
タ２４（２４ａ、２４ｂ，２４ｃ）を形成し、Ｎ形チャ
ネルＭＯＳトランジスタ２５（２５ａ，２５ｂ）を拡散
層３ａ内に形成したＣ−ＭＯＳ構成でも良い。
【００１６】本例によるとＣ−ＭＯＳが多段に接続され
るので、その入出力特性は、各々の段の入出力特性の積
となり、図８のＶ23及びＶ26と接合温度の関係のグラフ
に示すように、２６の電位Ｖ26を急峻に下げる事がで
き、従って、パワーＭＯＳ１３を接合温度上昇に対し急
峻にオフ状態にする事ができる。尚、Ｃ−ＭＯＳの接続
段数は限定される事なく、その数が多い程、入出力特性
は急峻となる。また、図６、図７において同一構成要素
の符号は、それぞれ図２、図３のものと同じものを使用
している。
【００１７】（３）制御領域Ｃあるいは感温素子として
の多結晶シリコンダイオード１５の配置は、上記実施例
の如く半導体基板Ａの中央部だけに限定される事なく、
例えば半導体装置の模式的平面図を表わす図９（ａ）乃
至（ｅ）に示すように、複数箇所に対称に配置してもよ
い。尚、本発明者らの実験結果によると、図１０の負荷
ショートさせパワーＭＯＳ１３を強制的に発熱させた場
合の配置箇所数と不良率との関係図に示すように、自己
過熱保護機能がない（０箇所）場合には不良率は１００
％となり、１箇所、すなわち半導体基板Ａの中央部だけ
に多結晶シリコンダイオード１５を配置した場合には不
良率は大幅に低減し、５箇所以上配置すると不良率は０
％となる。負荷ショートの様な短時間に大きな電力を消
費し発熱するような場合を想定した場合には、半導体基
板Ａ内の温度分布が不均一になり易いため、１箇所の配
置では保護機能が不十分であるので、本例の如く、複数
箇所配置するのが有効である。
【００１８】（４）上記実施例はパワーＭＯＳ１３及び
横形ＭＯＳトランジスタ１４をＮ型のチャネルで示した
が、本発明はそれに限らずＰ形のチャネルでもよい。こ
の場合には上記実施例において符号３ａに相当する拡散
層はＮ形導電形となり、そこで、絶縁層１０上にＮ形チ
ャンネルＭＯＳトランジスタ２５（２５ａ，２５ｂ）を
形成し、Ｐ形チャンネルＭＯＳトランジスタ２４（２４
ａ，２４ｂ，２４ｃ）をその拡散層３ａ内に形成しても
よい。通常、多結晶半導体内におけるＭＯＳトランジス
タのチャネルモビリティは単結晶半導体内におけるもの
と比較して小さくなるが、上記のように形成する事によ
り、Ｎ形チャネルＭＯＳトランジスタはＰ形チャネルＭ
ＯＳトランジスタに比較してキャリアが電子であるため
にチャネルモビリティの高いものが作り易く、Ｃ−ＭＯ
Ｓ構成としたときモビリティのバランスがとり易くな
る。
【００１９】（５）能動機能をもつ半導体素子はパワー
ＭＯＳ１３に限定されず、バイポーラトランジスタ、パ
ワーＩＣ等であってもよい。また、感熱素子も多結晶シ
リコンダイオード１５に限らずサーミスタ等でもよい。
さらに制御部の構成は実施例に示す構成に限定されない
事はもちろんである。
（６）実施例は抵抗体として多結晶シリコン抵抗１６を
用いたが、それに限らず窒化タンタル等の抵抗体であっ
てもよい。DETAILED DESCRIPTION OF THE INVENTION
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a semiconductor device having a temperature detecting function.
You.
[0002]
2. Description of the Related Art Differences in the operation of semiconductor devices having active functions
Conventionally, to avoid destruction due to the
A semiconductor element having an active function in one semiconductor substrate, for example,
Form a heat-sensitive element such as a heat-sensitive thyristor, and
The temperature of the semiconductor substrate is detected and the semiconductor
The element is controlled to protect it from thermal destruction.
[0003]
[0005] However, this
With the conventional temperature detection function, the semiconductor element inside the semiconductor substrate
Special consideration is given to the positional relationship between the element and the thermal element.
Not a plurality of MOS type unit cells as semiconductor elements
When a power element consisting of a set of
To protect the semiconductor device from thermal destruction
Is insufficient.
The present invention has been made in view of the above points.
To ensure that semiconductor elements are protected from thermal damage.
It is an object of the present invention to provide a semiconductor device which can be used.
[0005]
In order to achieve the above object,
In the semiconductor device of the present invention, a current flows during the conduction state.
The semiconductor power device that emits high heat by forming
A semiconductor chip, wherein the semiconductor power of the semiconductor chip is
-Area inside the element layout areaAbove the surface
Through the rimDetects the heat generation status of the semiconductor power element
A heat sensitive element portion is provided.
[0006]
According to the present invention, there is provided a semiconductor device comprising:
When the temperature of the printed circuit board rises abnormally,
When the heating temperature of the power element becomes abnormally high,
The temperature rise can be detected by the heat-sensitive element section. On this occasion,
The parasitic operation caused by the integration of the thermal element can be eliminated.
And furtherThermal power element is a semiconductor power elementIs the layout
Area inside the area to beIn other words, for semiconductor power devices
Enclosed and has low heat dissipation, and is relatively warm even among semiconductor chips.
It is located in the area where the temperature rises easily.
Conduction of semiconductor power element by detecting temperature in thermal element
The control ensures that the semiconductor power element is destroyed by heat.
You will be able to protect it from breaking.
[0007]
BRIEF DESCRIPTION OF THE DRAWINGS FIG.
You. FIGS. 1 and 2 show a vertical power unit having a self-overheating protection function.
-MOS transistors (hereinafter referred to as power MOS)
FIG. 1 is a schematic diagram of the semiconductor chip.
FIG. FIG. 2 is a sectional view taken along the line α-α in FIG.
You. Power that is an active element is provided on most of the entire semiconductor substrate A.
-Multiple MOS 13 connected in parallel to form a multi-source structure
Thus, a power region M is formed. The center of the semiconductor substrate A
Part, in other words, the part where heat is hardly dissipated,
Polycrystalline silicon diode as thermal element in easy-to-make part
A plurality of cards 15 are connected in series and controlled around
MOS transistor 14 as part, polycrystalline silicon
Resistors 16 and a constant voltage zener diode 17 are formed.
The control region C is formed as a body. Also, on the semiconductor substrate A
Voltage from outside (VinBonding to apply)
A pad section B is formed. These power region M and control region
Each element in the region C and the bonding pad portion B are electrically connected to each other.
Connected.
Next, referring to FIG. 2, the configuration will be described in detail.
I do. 1 is N+Shaped silicon substrate, 2 is N-Shaped silico
The epitaxial layers 3, 3a are deeply diffused P-type extensions.
Spreading layer, 4 is P-type diffusion layer, 5, 5a, 5b and 5c are N+
Type diffusion layer, 11 is P+P-type diffusion layer 3
3a, N+The diffusion layers 5, 5a, 5b and 5c are respectively
At the same time, they are formed in the same diffusion process. Power MOS13
The MOS structure is composed of a silicon epitaxial layer 2 and a silicon substrate.
A drain D comprising a plate 1 and a drain electrode 12;
A polycrystalline silicon layer 7 formed via an oxide film 6
Gate G and power M on its surface via an interlayer insulating film 8
A source comprising an aluminum electrode 9 covering the entire surface of the OS 13
The operation is performed by applying a voltage to the gate G.
As a result, an N-type channel is formed
A current flows between the source S and the drain D. The diffusion layer 4 and
The diffusion layer 3 partially overlaps, and the diffusion layer 3 diffuses deeply.
This is for over-voltage protection, and
This is to set the power supply voltage. Next, horizontal MOS transistor
The MOS structure of the resistor 14 is formed of aluminum on the diffusion layers 5a and 5b.
Sources S1 and
Formed via drain D1 and gate oxide film 6a
And a gate G1 made of a polycrystalline silicon layer 7a.
The operation is performed when a voltage is applied to the gate G1.
An N-type channel is formed in the portion
A current flows between the terminals D1. Constant voltage zener diode 17
Is formed of the diffusion layer 5c and the diffusion layer 11 and has a surface
Aluminum electrodes 9c and 9d are formed respectively. Next
A part of the surface of the diffusion layer 3a is thermally oxidized to form an insulating film (SiO 2).
Two10) is formed. And polycrystalline on the insulating film 10.
Silicon resistor 16 and polycrystalline silicon as thermal element
The diode 15 is formed. Polycrystalline silicon resistor 16
Is a polycrystalline silicon layer 7c, an interlayer insulating film 8 and aluminum
It is formed from the memory electrodes 9g and 9h. In addition, polycrystalline silicon
The diode 15 selectively expands the polysilicon layer 7b.
To form a PN junction, on which an interlayer insulating film 8 is partially interposed.
Then, aluminum electrodes 9e and 9f are formed. Stated above
Gate oxide films 6 and 6a, polycrystalline silicon
Layers 7, 7a, 7b, 7c, aluminum electrodes 9, 9
a, 9b, 9c, 9d, 9e, 9g, 9h are the same
It can be made in the same process. Each of the above elements is shown in FIG.
They are wired together as shown in the equivalent circuit diagram.
Each element is shown in the top view of FIG.
It is arranged as shown. That is, the control area C has a horizontal shape.
MOS transistor 14, polycrystalline silicon diode 1
5, resistor 16C and constant voltage zener diode 17 are arranged
And an aluminum electrode 9 covering the surface of the power region.
And each of them is electrically connected via a connection path C1. Figure
Medium 20 is the same as 20 in FIG.
The external connection terminal of the nickel electrode 9 is shown. Where the constant voltage
External connection terminal electrically connected to the anode of Zener diode 17
The child 20 is fixed to the ground potential. Therefore, as shown in FIG.
The diffusion layer 1 of the constant voltage zener diode 17
The P-type diffusion layer 3a electrically connected to 1 is also fixed to the ground potential.
You. Also, one of the voltages applied to the bonding pad B
The part is connected to a power MOS via a resistor 16b disposed beside the part.
13 gate electrodes G1 or lateral MOS transistors
In addition to the 14 drains D1, the others are also arranged horizontally
The gate of the lateral MOS transistor 14 is connected via the resistor 16a and the like.
Join G1.
Next, referring to the equivalent circuit diagram of FIG.
Explain the work. In the drawings, reference numerals are common to those in FIGS. 1 and 2.
is there. However, 16a, 16b and 16c are polycrystalline silicon
Resistance, RLIs the external load resistance, VDDIs an external power supply.
When the silicon substrate temperature is normal, that is, when the power MO
When the junction temperature in S13 is the normal temperature, the applied voltage V
inThe power MOS 13 is turned on,
When the silicon substrate temperature is abnormally high,
When the junction temperature in S13 rises abnormally,
The forward voltage of the polycrystalline silicon diode 15 is constant.
Because of having a negative temperature coefficient, the voltage drops between terminals of the resistor 16c.
(Ie, the gate G of the lateral MOS transistor 14).
1-source S1). Above a certain voltage
Then, the lateral MOS transistor 14 is turned on.
The resistance of the resistor 16b is turned on to turn on the lateral MOS transistor 14.
If it is sufficiently larger than the resistance value, the potential of 22 in FIG.
V twenty twoAnd 23 potential Vtwenty threeThe change in the junction temperature
As shown in the rough, the junction temperature is around 130 ° C (protection operation temperature
V)twenty twoDrops sharply to almost 0V, so the power MO
S13 is forcibly turned off, causing the junction temperature to rise.
Element destruction can be avoided.
According to the structure of the above embodiment, the insulating film 10
By forming, individual elements can be trimmed,
And parasiticmotionSemiconductor device without
In addition, an abnormal rise in the junction temperature of the power MOS
The element is arranged in the central control region C where the temperature tends to be high.
This allows for more accurate detection, and the
It can be done in the same process, which makes it simple and leads to cost reduction.
And the resistance of the polysilicon resistor 16c on the insulating film.
Resistance value and number of polycrystalline silicon diodes 15 connected in series
, The protection operation temperature can be set arbitrarily. Polycrystalline silico
Since the resistance of the resistor 16c can be individually trimmed,
Excellent protection operation temperature can be precisely controlled after fabrication
effective.
The silicon epitaxial layer 2 has a power
Since it forms part of the drain of MOS13, the power
The potential changes according to the operation state of the MOS 13,
Temperature of the polycrystalline silicon diode 15 formed thereon
May act to degrade the degree of detection accuracy
However, according to the present embodiment, in the silicon epitaxial layer 2
A P-type diffusion layer 3a is formed on the
To form the polycrystalline silicon diode 15
Can be eliminated. in this regard
More specifically, a structure without the P-type diffusion layer 3a is assumed.
Then, it is insulated according to the potential of the silicon epitaxial layer 2.
Film (SiOTwoFilm, etc.) 10 is polarized and polycrystalline silicon die
Charges are induced on the surface of the diode 15 on the insulating film 10 side.
U. In the case of the present embodiment, for example, a silicon epitaxy
When the metal layer 2 has a high potential, the polysilicon diode 1
5, the impurity concentration at the PN junction changes.
The temperature characteristics at the forward voltage change and the temperature
Accuracy deteriorates. In extreme cases, polycrystalline silicon
An inversion layer is formed under the P-type region of the ion 15
It will behave like a parasitic MOS transistor
Thus, temperature detection is no longer possible.
According to this embodiment, the polycrystalline silicon
Since the P-type diffusion layer 3a is formed under the
PN between the diffusion layer 3a and the silicon epitaxial layer 2
A junction is formed, and the power MOS 13
Since it can be electrically separated, polycrystalline silicon
The ion 15 is not affected by the drain potential.
In addition, the parasitic operation described above can be eliminated,
The effect is that high temperature detection can be performed.
You.
The present invention is not limited to the above embodiment,
Various modifications are possible as follows.
(1) All elements in the control region C are formed on the insulating film 10
Alternatively, as shown in the second embodiment of FIG.
A transistor 14a is formed on the insulating film 10 and a constant voltage zener is formed.
Only the diode 17 may be formed in the diffusion layer 3a.
Conversely, the lateral MOS transistor 14a is connected to the diffusion layer 3a.
Inside, a constant voltage zener diode 17 is formed on the insulating film 10.
May be implemented. In addition, diffused polycrystalline silicon resistor 16
It may be formed in the layer 3a.
(2) FIG. 1 shows a third embodiment of FIG.
FIG. 7 which is an α-α sectional view and an equivalent circuit diagram thereof
As shown in FIG.
Register 24 (24a, 24b, 24c) and N-type cha
Forming MOS transistors 25 (25a, 25b)
To form a complementary MOS transistor (C-MOS)
22 potentials Vtwenty twoTo a potential V of 2626As well
No. Also, a P-type channel MOS transistor is formed on the insulating film 10.
And form an N-type channel 24 (24a, 24b, 24c).
Diffusion of MOS transistor 25 (25a, 25b)
A C-MOS configuration formed in the layer 3a may be used.
According to this embodiment, C-MOSs are connected in multiple stages.
Therefore, the input / output characteristics are the product of the input / output characteristics of each stage.
And V in FIG.twenty threeAnd V26Graph of relationship between temperature and junction temperature
As shown in FIG.26Can be lowered sharply.
Therefore, the power MOS 13 suddenly responds to the rise in the junction temperature.
It can be turned off steeply. In addition, connection of C-MOS
The number of stages is not limited.
Becomes steep. 6 and 7, the same components are used.
Use the same reference numerals as those in FIGS. 2 and 3, respectively.
are doing.
(3) As a control area C or a temperature sensing element
The arrangement of the polycrystalline silicon diode 15 in the above embodiment is
Without being limited to only the central part of the semiconductor substrate A as in
For example, FIG. 9A shows a schematic plan view of a semiconductor device.
As shown in FIG.
No. According to the experimental results of the present inventors, the load of FIG.
When the power MOS 13 is forcibly heated by short-circuit
As shown in the diagram of the relationship between the number of
Failure rate is 100 when there is no overheat protection function (0 places)
%, That is, only at one location, that is, only at the center of the semiconductor substrate A.
When the polycrystalline silicon diode 15 is arranged in
The pass rate is greatly reduced, and the defective rate is 0 when 5 or more locations are arranged.
%. Turn off large power in a short time such as load short
If it is assumed that heat will be consumed,
Since the temperature distribution in the plate A tends to be non-uniform,
Device does not provide sufficient protection,
It is effective to place them in places.
(4) The above embodiment uses the power MOS 13 and
The lateral MOS transistor 14 is shown by an N-type channel.
However, the present invention is not limited to this, and may be a P-type channel. This
In the above case, the diffusion corresponding to the code 3a in the above embodiment is performed.
The layers are of the N-type conductivity type, where the N-type
Channel MOS transistor 25 (25a, 25b)
And a P-type channel MOS transistor 24 (24
a, 24b, 24c) in the diffusion layer 3a.
Good. MOS transistors in polycrystalline semiconductors
Channel mobility within a single-crystal semiconductor
Although it is smaller than that of
And the N-channel MOS transistor is a P-channel M
Carriers are electrons compared to OS transistors
With high channel mobility, and C-MO
Mobility is easy to balance when S configuration
You.
(5) The semiconductor element having an active function is a power
It is not limited to the MOS 13 but may be a bipolar transistor,
It may be a power IC or the like. Also, the thermal element is made of polycrystalline silicon.
The thermistor may be used instead of the recon diode 15.
Further, the configuration of the control unit is not limited to the configuration shown in the embodiment.
Of course things are.
(6) The embodiment uses a polycrystalline silicon resistor 16 as a resistor.
However, a resistor such as tantalum nitride may be used.
You may.
【図面の簡単な説明】
【図１】本発明の一実施例を示す半導体装置の模式的平
面図である。
【図２】図１中のα−α断面図である。
【図３】図１及び図２の等価回路図である。
【図４】Ｖ22及びＶ23と接合温度の関係を示すグラフで
ある。
【図５】第２の実施例を示す断面図である。
【図６】第３の実施例としての図１中のα−α断面図で
ある。
【図７】図６の等価回路図である。
【図８】図６の実施例のＶ23及びＶ26と接合温度の関係
を示すグラフである。
【図９】多結晶シリコンダイオードを複数箇所配置した
半導体装置の模式的平面図である。
【図１０】配置箇所数と不良率との関係図である。
【図１１】図１における実施例の具体的な配置を示す上
面図である。
【符号の説明】
１０ 絶縁膜（ＳｉＯ2 膜）
１３ 縦形パワーＭＯＳトランジスタ
１５ 感熱素子である多結晶シリコンダイオードBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view of a semiconductor device showing one embodiment of the present invention. FIG. 2 is a sectional view taken along line α-α in FIG. FIG. 3 is an equivalent circuit diagram of FIGS. 1 and 2; 4 is a graph showing the relationship between the junction temperature and the V 22 and V 23. FIG. 5 is a sectional view showing a second embodiment. FIG. 6 is a sectional view taken along the line α-α in FIG. 1 as a third embodiment. FIG. 7 is an equivalent circuit diagram of FIG. 6; 8 is a graph showing the relationship between V 23 and V 26 of the embodiment junction temperature of FIG. FIG. 9 is a schematic plan view of a semiconductor device in which a plurality of polycrystalline silicon diodes are arranged. FIG. 10 is a diagram showing the relationship between the number of locations and the defect rate. FIG. 11 is a top view showing a specific arrangement of the embodiment in FIG. 1; [Description of Signs] 10 Insulating film (SiO 2 film) 13 Vertical power MOS transistor 15 Polycrystalline silicon diode which is a thermal element
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 27/04 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/78 H01L 27/04
Claims (1)
する半導体パワー素子が形成された半導体チップにおい
て、 前記半導体チップの前記半導体パワー素子のレイアウト
される領域の内側の領域の表面に絶縁膜を介して配置さ
れ、前記半導体パワー素子の発熱状況を検出する感熱素
子部を有する事を特徴とする半導体装置。 （２）前記半導体パワー素子は並列接続された複数のＭ
ＯＳトランジスタ構造から構成されるものであり、前記
感熱素子部の配置される前記領域は、前記半導体チップ
において、前記複数のＭＯＳトランジスタ構造の配置領
域の内側に位置している特許請求の範囲第１項記載の半
導体装置。 （３）前記感熱素子部は、前記半導体チップのほぼ中央
部に配置されている特許請求の範囲第１項又は第２項記
載の半導体装置。 （４）前記感熱素子部は、前記半導体チップの表面に前
記絶縁膜を介して配置された多結晶シリコンに形成され
たダイオードである特許請求の範囲第１項乃至第３項の
いずれかに記載の半導体装置。 （５）前記感熱素子部は、前記多結晶シリコンダイオー
ドの順方向電圧の負の温度係数を利用するものである特
許請求の範囲第４項記載の半導体装置。 （６）前記感熱素子部は、前記多結晶シリコンダイオー
ドを複数個直列接続したものである特許請求の範囲第４
項又は第５項記載の半導体装置。 （７）前記感熱素子部は前記半導体チップの複数箇所に
配置されている特許請求の範囲第１項乃至第６項のいず
れかに記載の半導体装置。 （８）前記感熱素子部は、５箇所以上配置されている特
許請求の範囲第７項記載の半導体装置。(57) Claims: (1) In a semiconductor chip on which a semiconductor power element that generates high heat when a current flows in the conductive state is formed, a region of the semiconductor chip on which the semiconductor power element is laid out A semiconductor device disposed on a surface of a region inside the semiconductor device via an insulating film and detecting a heat generation state of the semiconductor power element. (2) The semiconductor power element includes a plurality of M connected in parallel.
2. The semiconductor device according to claim 1, wherein the region in which the thermosensitive element portion is disposed is located inside a region where the plurality of MOS transistor structures are disposed in the semiconductor chip. 13. The semiconductor device according to claim 1. (3) The semiconductor device according to claim 1 or 2, wherein the heat-sensitive element section is disposed substantially at a center of the semiconductor chip. ( 4 ) The heat-sensitive element portion is provided in front of the surface of the semiconductor chip.
The semiconductor device according to any one of the serial first term claims is a diode formed in polysilicon disposed over the insulating film to the third term. ( 5 ) The semiconductor device according to claim 4 , wherein the thermal element uses a negative temperature coefficient of a forward voltage of the polycrystalline silicon diode. (6) the thermosensitive element portion, the polycrystalline range of silicon diodes claims in which the plurality of series-connected fourth
Item 6. The semiconductor device according to item 5 or 5 . ( 7 ) The semiconductor device according to any one of claims 1 to 6, wherein the heat-sensitive element portions are arranged at a plurality of locations on the semiconductor chip. ( 9 ) The semiconductor device according to claim 7 , wherein the thermosensitive element section is arranged at five or more locations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9210636A JP3008900B2 (en) | 1985-11-29 | 1997-08-05 | Semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60-270141 | 1985-11-29 | ||
| JP27014185 | 1985-11-29 | ||
| JP9210636A JP3008900B2 (en) | 1985-11-29 | 1997-08-05 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61250208A Division JPH0693485B2 (en) | 1985-11-29 | 1986-10-21 | Semiconductor device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31203398A Division JP3204226B2 (en) | 1985-11-29 | 1998-11-02 | Semiconductor device |
| JP31203498A Division JP3204227B2 (en) | 1985-11-29 | 1998-11-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10116987A JPH10116987A (en) | 1998-05-06 |
| JP3008900B2 true JP3008900B2 (en) | 2000-02-14 |
Family
ID=26518173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9210636A Expired - Lifetime JP3008900B2 (en) | 1985-11-29 | 1997-08-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3008900B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002009284A (en) * | 2000-06-19 | 2002-01-11 | Mitsubishi Electric Corp | Semiconductor element and device for electric power |
| JP4620889B2 (en) * | 2001-03-22 | 2011-01-26 | 三菱電機株式会社 | Power semiconductor device |
| JP4696395B2 (en) * | 2001-05-21 | 2011-06-08 | パナソニック株式会社 | Brushless motor drive device |
| JP4677756B2 (en) * | 2004-10-13 | 2011-04-27 | 富士電機システムズ株式会社 | Power module |
| US7554173B2 (en) | 2004-12-22 | 2009-06-30 | Mitsubishi Electric Corporation | Semiconductor device |
| JP2011096699A (en) * | 2009-10-27 | 2011-05-12 | Mitsubishi Electric Corp | Semiconductor device, and method of manufacturing the same |
| DE112013007376T5 (en) | 2013-08-28 | 2016-05-19 | Mitsubishi Electric Corporation | Semiconductor device |
| CN114883323B (en) * | 2018-06-19 | 2023-06-20 | 新唐科技日本株式会社 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
-
1997
- 1997-08-05 JP JP9210636A patent/JP3008900B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10116987A (en) | 1998-05-06 |
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