JP2986875B2 - Integrated solar cell - Google Patents
Integrated solar cellInfo
- Publication number
- JP2986875B2 JP2986875B2 JP2235892A JP23589290A JP2986875B2 JP 2986875 B2 JP2986875 B2 JP 2986875B2 JP 2235892 A JP2235892 A JP 2235892A JP 23589290 A JP23589290 A JP 23589290A JP 2986875 B2 JP2986875 B2 JP 2986875B2
- Authority
- JP
- Japan
- Prior art keywords
- solar cell
- layer
- upper electrode
- integrated
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010410 layer Substances 0.000 claims description 142
- 239000004065 semiconductor Substances 0.000 claims description 46
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 8
- 229920003002 synthetic resin Polymers 0.000 claims description 4
- 239000000057 synthetic resin Substances 0.000 claims description 4
- 229910010272 inorganic material Inorganic materials 0.000 claims description 3
- 239000011147 inorganic material Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 41
- 238000000034 method Methods 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000010408 film Substances 0.000 description 8
- -1 polyethylene terephthalate Polymers 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000005038 ethylene vinyl acetate Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229920002620 polyvinyl fluoride Polymers 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910004613 CdTe Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- DQXBYHZEEUGOBF-UHFFFAOYSA-N but-3-enoic acid;ethene Chemical compound C=C.OC(=O)CC=C DQXBYHZEEUGOBF-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 2
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920005668 polycarbonate resin Polymers 0.000 description 1
- 239000004431 polycarbonate resin Substances 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 239000012255 powdered metal Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
- H01L31/0465—PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/543—Solar cells from Group II-VI materials
Landscapes
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Engineering & Computer Science (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は集積化太陽電池に係わり、特に一体基板上に
直列接続して、集積化された薄膜太陽電池に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated solar cell, and more particularly, to an integrated thin-film solar cell connected in series on an integrated substrate.
［従来の技術及び発明が解決しようとする課題］ 太陽電池は、その種類によらず、一般に出力電圧が低
いので、一般の機器の電源として使用する場合、直列に
接続して電圧を上げて使用しなければならない。[Problems to be Solved by the Related Art and the Invention] Since the output voltage of a solar cell is generally low irrespective of its type, when used as a power source for general equipment, it is used by increasing the voltage by connecting in series. Must.
このとき、半導体層として結晶シリコンあるいは多結
晶シリコンを用いる太陽電池では、太陽電池を形成した
半導体ウエハーをリード線によって直列に接続してい
る。しかしながら、リード線によって直列化する場合、
断線の不安があり、また組立工程が複雑で製造コストも
高くなるという問題があった。At this time, in a solar cell using crystalline silicon or polycrystalline silicon as a semiconductor layer, semiconductor wafers on which the solar cell is formed are connected in series by lead wires. However, when serializing with leads,
There was a problem that there was a fear of disconnection, and the assembly process was complicated and the manufacturing cost was high.
これに対し、半導体層としてアモルファスシリコンを
用いる太陽電池では、一体基板上で、リード線を用いず
に直列化接続する方法がとられている。この方法の一例
としては、特公昭58−21827号公報に示されているよう
に、一体基板上にいくつかの部分に分割された太陽電池
を形成し、第16図の平面図に示すように、隣り合った太
陽電池の上部電極1604と下部電極1602を半導体層1603の
形成されていない場所で接続する方法がある。On the other hand, in a solar cell using amorphous silicon as a semiconductor layer, a method of serial connection on an integrated substrate without using a lead wire has been adopted. As an example of this method, as shown in JP-B-58-21827, a solar cell divided into several parts is formed on an integrated substrate, and as shown in the plan view of FIG. There is a method of connecting the upper electrode 1604 and the lower electrode 1602 of the adjacent solar cells at a place where the semiconductor layer 1603 is not formed.
この方法によれば、１枚の基板から、実用的な出力電
圧が得られ、太陽電池モジュールの組立工程が簡単化さ
れて、製造コストが低下し、断線の不安もなくなり、製
造の歩留りも向上した。According to this method, a practical output voltage can be obtained from a single substrate, the assembling process of the solar cell module is simplified, the manufacturing cost is reduced, there is no fear of disconnection, and the manufacturing yield is improved. did.
しかしながら、太陽電池の面積を大きくすると、透明
電極（上部電極）の抵抗値が大きくなり、太陽電池の光
電変動効率が低下するという問題点があった。However, when the area of the solar cell is increased, there is a problem that the resistance value of the transparent electrode (upper electrode) increases, and the photoelectric fluctuation efficiency of the solar cell decreases.
また、特公昭62−5353号公報には、第17図の断面図の
ように、一体基板上で分割された太陽電池の隣接する境
界部分で接続する方法が示されている。この方法によれ
ば、接続部の間の太陽電池の幅を最適化することによっ
て、透明電極（上部電極）の抵抗値を下げ、大面積の太
陽電池においても、光電変換効率の低下が少なくなっ
た。In addition, Japanese Patent Publication No. Sho 62-5353 discloses a method of connecting solar cells divided on an integrated substrate at adjacent boundaries, as shown in the sectional view of FIG. According to this method, by optimizing the width of the solar cell between the connection portions, the resistance value of the transparent electrode (upper electrode) is reduced, and even in a large-area solar cell, the decrease in photoelectric conversion efficiency is reduced. Was.
しかしながら、この方法では、下部電極1702とアモル
ファスシリコン層1703と上部電極1704を、別々にパター
ニングしなければならないため、アモルファスシリコン
層1703の堆積後、つまり上部電極1704の堆積前にパター
ニングが必要であり、半導体層が大気にさらされている
工程が長くなって、太陽電池の特性に悪影響を与えるお
それがある。However, in this method, since the lower electrode 1702, the amorphous silicon layer 1703, and the upper electrode 1704 must be separately patterned, patterning is necessary after the deposition of the amorphous silicon layer 1703, that is, before the deposition of the upper electrode 1704. In addition, a process in which the semiconductor layer is exposed to the air is lengthened, which may adversely affect the characteristics of the solar cell.
また、隣り合った太陽電池の下部電極1702は、アモル
ファスシリコン層1703で絶縁されているが、アモルファ
スシリコン層1703は半導体層であり、またｎ型アモルフ
ァスシリコン層、あるいはｐ型アモルファスシリコン層
のような低抵抗の半導体層を含むため、リーク電流が生
じ、絶縁耐圧も低くなるという問題がある。Further, the lower electrodes 1702 of the adjacent solar cells are insulated by an amorphous silicon layer 1703, but the amorphous silicon layer 1703 is a semiconductor layer, and an n-type amorphous silicon layer or a p-type amorphous silicon layer. Since the semiconductor layer includes a low-resistance semiconductor layer, there is a problem that a leak current is generated and a dielectric strength voltage is reduced.
さらに、上部電極1704に透明電極を用いる場合には、
光透過率の確保のため、透明電極の膜厚を薄くした場合
に、接続部の段差により、断線が生じるという問題があ
った。Further, when a transparent electrode is used for the upper electrode 1704,
When the thickness of the transparent electrode is reduced in order to secure the light transmittance, there is a problem that a disconnection occurs due to a step in the connection portion.
［発明の目的］ 本発明の目的は、上述した従来の技術の課題点を解決
し、一体基板上で、直列化された、信頼性が高く、製造
工程が簡単で、低コストな大面積の集積化太陽電池を提
供することにある。[Object of the Invention] An object of the present invention is to solve the above-mentioned problems of the conventional technology, and to form a serialized, highly reliable, simple manufacturing process and a low cost large area on an integrated substrate. It is to provide an integrated solar cell.
［課題を解決するための手段］ 本発明者は、上述の目的を達成すべく鋭意研究を重ね
たところ完成に至ったものであり、 本発明の集積化太陽電池は、下部電極と、半導体層
と、上部電極とを有する複数の太陽電池を、接続して集
積化される集積化太陽電池において、 前記半導体層と前記上部電極の一部をパターニング除
去することによって、前記下部電極の一部に前記半導体
層及び前記上部電極で覆われていない除去領域が形成さ
れていること、前記除去領域を含む隣接する太陽電池の
対向する端部とこれらの端部の間の領域あるいは全面を
被覆する絶縁層が形成されていること、隣接する太陽電
池の一方の下部電極の前記除去領域上に形成された前記
絶縁層の一部と、他方の上部電極上に形成された前記絶
縁層の一部とを取り除くことによって接続部が形成され
ていること、及び前記隣接する太陽電池のそれぞれに形
成された接続部を前記絶縁層をまたいで接続するように
導電層が形成されていること、を特徴とする。Means for Solving the Problems The inventor of the present invention has made extensive studies to achieve the above object, and has completed the present invention. The integrated solar cell of the present invention has a lower electrode and a semiconductor layer. And an integrated solar cell in which a plurality of solar cells having an upper electrode are connected and integrated, by patterning and removing a part of the semiconductor layer and the upper electrode, thereby forming a part of the lower electrode. A removal region not covered by the semiconductor layer and the upper electrode is formed, and an insulating portion covering an opposite end of an adjacent solar cell including the removal region and a region between these ends or the entire surface. That the layer is formed, a part of the insulating layer formed on the removal region of one lower electrode of the adjacent solar cell, and a part of the insulating layer formed on the other upper electrode. To get rid of The connecting portion is formed me, and the possible adjacent conductive layers so that connection portions formed respectively to connect across the insulating layer of the solar cell is formed, characterized by.
［作用］ 本発明においては、一体基板上で、分割された太陽電
池を直接に接続するにあたり、隣接した太陽電池の下部
電極を従来例の様に半導体層で絶縁するのではなく、絶
縁層で絶縁することにより、リーク電流をなくし、絶縁
耐圧を向上させることができる。[Operation] In the present invention, in directly connecting the divided solar cells on the integrated substrate, the lower electrode of the adjacent solar cell is not insulated by the semiconductor layer as in the conventional example, but by an insulating layer. By insulating, leakage current can be eliminated and dielectric strength can be improved.
また半導体層と上部電極を同時にパターニングできる
構造とすることによって、半導体層のみをパターニング
する工程を省略することができ、半導体層表面が長時間
大気にさらされることを防ぐことができる。Further, by adopting a structure in which the semiconductor layer and the upper electrode can be patterned at the same time, the step of patterning only the semiconductor layer can be omitted, and the semiconductor layer surface can be prevented from being exposed to the air for a long time.
また、隣接した太陽電池の上部電極と下部電極を接続
する導電層を上部電極と独立して設けることによって、
上部電極の膜厚が薄い場合でも、接続部の段差による断
線をなくすことができる。Also, by providing a conductive layer connecting the upper electrode and the lower electrode of the adjacent solar cell independently of the upper electrode,
Even when the thickness of the upper electrode is thin, disconnection due to a step in the connection portion can be eliminated.
本発明者は、上述の知見に基き、以下の構成の集積化
太陽電池によって前述の目的を達成した。The present inventor has achieved the above-mentioned object by an integrated solar cell having the following configuration based on the above findings.
［実施例］ 以下、本発明の好適な実施態様例を第１図、第３図に
基いて説明する。[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 1 and 3.
第３図は本発明の集積化太陽電池の一例の概観図であ
り、301は一体基板上に形成された複数の太陽電池、302
は複数形成された太陽電池301を直列に接続する接続部
分、303,304は引き出し電極である。FIG. 3 is a schematic view of an example of an integrated solar cell according to the present invention, wherein 301 denotes a plurality of solar cells formed on an integrated substrate, 302
Is a connection portion for connecting a plurality of formed solar cells 301 in series, and 303 and 304 are extraction electrodes.
第１図は、本発明の実施例を説明するための断面図で
あり、第３図における接続部分Ａを拡大した断面を示し
たものである。第２図は、本発明の参考例を説明するた
めの断面図であり、第３図における接続部分Ａを拡大し
た断面を示したものである。FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention, and shows an enlarged cross-section of a connection portion A in FIG. FIG. 2 is a cross-sectional view for explaining a reference example of the present invention, and shows an enlarged cross-section of a connection portion A in FIG.
第１図〜第３図に示されるように絶縁基板201あるい
は導電性基板101上に絶縁層102を形成した基板上に形成
された複数の太陽電池301を直列に接続した集積化太陽
電池であって、下部電極103,202と半導体層104,203と上
部電極105,204を有している。そして太陽電池301の端部
あるいは全面が、下部電極の一部109,209及び上部電極
の一部110,210を除いて絶縁層106,205で被覆されてい
る。隣接する太陽電池の一方の下部電極で絶縁層で被覆
されていない部分109,209と他方の上部電極110,210が、
導電層107,206によって絶縁層106,205をまたいで接続さ
れている。第２図に示す参考例に対して第１図に示す本
実施例は絶縁層205が下部電極の一部と上部電極の一部
をともに取り除いて導電層206を形成している。第１図
に示す本実施例においても、第２図に示す参考例と同様
に、導電性基板上に絶縁層を形成した基板を用いてよ
く、絶縁層を全面に覆わず太陽電池の対向する端部とこ
れらの端部間の領域を覆うようにしてもよく、導電層を
一層で構成してもよい。As shown in FIGS. 1 to 3, an integrated solar cell in which a plurality of solar cells 301 formed on an insulating substrate 201 or a substrate obtained by forming an insulating layer 102 on a conductive substrate 101 is connected in series. In addition, it has lower electrodes 103 and 202, semiconductor layers 104 and 203, and upper electrodes 105 and 204. The end or entire surface of the solar cell 301 is covered with insulating layers 106 and 205 except for parts 109 and 209 of the lower electrode and parts 110 and 210 of the upper electrode. Portions 109, 209 and the other upper electrodes 110, 210 of one lower electrode of the adjacent solar cell that are not covered with an insulating layer,
The conductive layers 107 and 206 are connected across the insulating layers 106 and 205. In contrast to the reference example shown in FIG. 2, in the present embodiment shown in FIG. 1, the insulating layer 205 forms the conductive layer 206 by removing both a part of the lower electrode and a part of the upper electrode. In the present embodiment shown in FIG. 1, as in the reference example shown in FIG. 2, a substrate having an insulating layer formed on a conductive substrate may be used. The end portions and the region between these end portions may be covered, and the conductive layer may be composed of a single layer.
本発明の構成により、一体基板上で、太陽電池を直列
接続することによって、リード線を用いて直列接続する
場合よりも、低コストで、リード線の断線等のない信頼
性の高い太陽電池を提供することができる。With the configuration of the present invention, by connecting solar cells in series on an integrated substrate, a more reliable solar cell without disconnection of the lead wire can be provided at a lower cost than in the case of serial connection using lead wires. Can be provided.
また、一体基板上の隣りあった太陽電池の端部あるい
は全部が下部電極と上部電極の一部を除いて絶縁層で被
覆されていることにより、直列化する太陽電池の間のリ
ーク電流がなくなり、絶縁耐圧を大巾に向上させること
ができる。In addition, since the ends or all of the adjacent solar cells on the integrated substrate are covered with the insulating layer except for a part of the lower electrode and the upper electrode, there is no leakage current between the solar cells to be serialized. In addition, the withstand voltage can be greatly improved.
また、半導体層と上部電極を同時にパターニングでき
るので、製造工程が簡単になり、半導体層の形成後、半
導体層を長時間大気にさらすことを無くすことができ
る。Further, since the semiconductor layer and the upper electrode can be patterned at the same time, the manufacturing process can be simplified, and the semiconductor layer can be prevented from being exposed to the air for a long time after the formation of the semiconductor layer.
さらに、上部電極として透明電極を用いる場合でも、
隣り合った太陽電池の下部電極との接続材料は上部電極
そのものではなく、導電層を用いるので、接続部の段差
による断線を無くすことができる。Furthermore, even when a transparent electrode is used as the upper electrode,
Since the conductive material is used for the connection material with the lower electrode of the adjacent solar cell instead of the upper electrode itself, disconnection due to the step of the connection portion can be eliminated.
また、第３図の接続部と接続部の間の太陽電池の幅ｄ
を最適化することにより、光電変換効率を下げずに大面
積化することができる。In addition, the width d of the solar cell between the connection portions in FIG.
By optimizing, the area can be increased without lowering the photoelectric conversion efficiency.
以下本発明の集積化太陽電池の各部の構成を詳述す
る。Hereinafter, the configuration of each part of the integrated solar cell of the present invention will be described in detail.
本発明に於て、使用する基板は、絶縁性基板あるいは
導電性基板に絶縁層を形成した基板である。絶縁性基板
としては、ガラス基板あるいはポリイミド、ポリエチレ
ンテレフタラート等の高分子フィルムを用いることがで
きる。In the present invention, the substrate used is an insulating substrate or a substrate obtained by forming an insulating layer on a conductive substrate. As the insulating substrate, a glass substrate or a polymer film such as polyimide or polyethylene terephthalate can be used.
また、導電性基板としては、ステンレス等の金属基板
を用いることができる。Further, a metal substrate such as stainless steel can be used as the conductive substrate.
また、導電性基板上に形成する絶縁層としては、Si
O2,Si2N4,Al2O3等の無機材料の薄膜を用いるか、あるい
は合成樹脂を塗布してもよい。In addition, as the insulating layer formed on the conductive substrate, Si
A thin film of an inorganic material such as O 2 , Si 2 N 4 and Al 2 O 3 may be used, or a synthetic resin may be applied.
本発明に於て、上部電極及び下部電極はAl,Ag,Cr,Ni,
Au,Pb,Sn,Zn,Mg,Cu,Fe,W等の金属、あるいは、ITO,Sn
O2,ZnO等の透明導電膜が好適に用いられる。In the present invention, the upper electrode and the lower electrode are Al, Ag, Cr, Ni,
Metals such as Au, Pb, Sn, Zn, Mg, Cu, Fe, W, or ITO, Sn
A transparent conductive film such as O 2 or ZnO is preferably used.
本発明に於て、半導体層としては、アモルファスシリ
コン、多結晶シリコン、Cds,CdTe,CuInSe2等の半導体薄
膜が好適に用いられる。In the present invention, as the semiconductor layer, a semiconductor thin film of amorphous silicon, polycrystalline silicon, Cds, CdTe, CuInSe 2 or the like is suitably used.
本発明に於て、太陽電池の電極及び半導体層の端部を
被覆する絶縁層は、第２図のごとく、端部のみを被覆す
る構成であっても良いし、第１図のごとく、全面を被覆
し、下部電極と上部電極の接続部分のみを除去した構成
であっても良い。In the present invention, the insulating layer covering the electrodes of the solar cell and the ends of the semiconductor layers may be configured to cover only the ends as shown in FIG. 2 or the entire surface as shown in FIG. And only the connection portion between the lower electrode and the upper electrode may be removed.
絶縁層としては、SiO2,Si3N4,Al2O3等の無機材料ある
いは、ポリエチレンエポシキ樹脂、ポリアミド樹脂、ポ
リイミド、ポリエステル樹脂、ポリカーボネイト樹脂、
フッ素樹脂等の合成樹脂の中から選択して用いられる。As the insulating layer, an inorganic material such as SiO 2 , Si 3 N 4 , Al 2 O 3 or a polyethylene epoxy resin, a polyamide resin, a polyimide, a polyester resin, a polycarbonate resin,
It is used by selecting from synthetic resins such as fluororesins.
また、上部電極側から光を入射させる太陽電池で、太
陽電池全面を前記絶縁層で被覆する場合、前記の絶縁層
の中で可視光の吸収係数の小さな物質が選択して用いら
れる。In the case where the entire surface of the solar cell is covered with the insulating layer in a solar cell in which light is incident from the upper electrode side, a substance having a small visible light absorption coefficient is selected and used in the insulating layer.
絶縁層の厚さは、薄すぎると絶縁耐圧が低下し、厚す
ぎると隣り合った太陽電池の上部電極と下部電極を接続
する導電層の断線を生じるおそれがある。したがって絶
縁層の厚さは、使用する材料によって好ましい厚さが異
なるが、好ましくは0.2μｍ〜3mm、より好ましくは１μ
ｍ〜1mm、最適には５μｍ〜500μｍであることが望まし
い。If the thickness of the insulating layer is too small, the withstand voltage decreases, and if the thickness is too large, there is a possibility that the conductive layer connecting the upper electrode and the lower electrode of the adjacent solar cells may be disconnected. Therefore, the preferred thickness of the insulating layer varies depending on the material used, but is preferably 0.2 μm to 3 mm, more preferably 1 μm.
m to 1 mm, optimally 5 μm to 500 μm.
隣り合った太陽電池の上部電極と下部電極を接続する
導電層としては、Al,Ag,Cr,Ni,Au,Pb,Sn,Zn,Mg,Cu,Fe,W
等の金属、あるいは、はんだ等の合金、あるいはAgペー
スト等の粉末状金属を用いた導電性樹脂、あるいは以上
の物質を第１図のように２種以上組み合わせて使用する
ことができる。Al, Ag, Cr, Ni, Au, Pb, Sn, Zn, Mg, Cu, Fe, W as the conductive layer connecting the upper and lower electrodes of adjacent solar cells
As shown in FIG. 1, two or more kinds of metals, such as alloys such as solder, conductive resin using powdered metal such as Ag paste, or the above substances can be used.
また、導電層として、金属と導電性樹脂を組み合わせ
て二層構成とすることによって、電極とのコンタクトを
確実にし、更に導電層全体としての抵抗値を低くするこ
とができる。In addition, by forming a two-layer structure by combining a metal and a conductive resin as the conductive layer, contact with an electrode can be ensured and the resistance value of the entire conductive layer can be reduced.
また、本発明の集積化太陽電池には、表面保護材料及
び充てん材料が、太陽電池の構成に応じて適宜用いられ
る。In the integrated solar cell of the present invention, a surface protection material and a filling material are appropriately used according to the configuration of the solar cell.
表面保護材料及び充てん材料の例としては、ガラス、
アクリル樹脂、ポリエチレンテレフタラート、シリコー
ン樹脂、ポリビニルブチラール（PVB）、エチレンビニ
ルアセテート（EVA）等を用いることができる。Examples of surface protection and filling materials include glass,
Acrylic resin, polyethylene terephthalate, silicone resin, polyvinyl butyral (PVB), ethylene vinyl acetate (EVA), or the like can be used.
また、本発明の集積化太陽電子に於て透明電極の上部
または下部に金属あるいは導電性樹脂からなる集積電極
を備えた構成とすることもできる。Further, the integrated solar electron of the present invention may be configured such that an integrated electrode made of metal or conductive resin is provided above or below the transparent electrode.
次に本発明の集積化太陽電池の製造方法について述べ
る。Next, a method for manufacturing the integrated solar cell of the present invention will be described.
本発明の集積化太陽電池は、絶縁基板あるいは導電性
基板に絶縁層を形成した基板上に、下部電極と半導体層
及び上部電極を形成し、下部電極をパターニングして複
数に分割し、下部電極の一部が露出するように半導体層
と上部電極をパターニングし、パターニングした太陽電
池の端部あるいは全面を被覆するように絶縁層を形成
し、隣接する太陽電池の一方の下部電極の一部と他方の
上部電極の一部の絶縁層を取り除き、取り除いた部分を
導電層で接続して、全面に保護膜を形成することによ
り、製造される。The integrated solar cell of the present invention comprises a lower electrode, a semiconductor layer, and an upper electrode formed on an insulating substrate or a substrate on which an insulating layer is formed on a conductive substrate. The semiconductor layer and the upper electrode are patterned so that part of the solar cell is exposed, an insulating layer is formed so as to cover the edge or the entire surface of the patterned solar cell, and a part of one lower electrode of an adjacent solar cell is formed. It is manufactured by removing a part of the insulating layer of the other upper electrode, connecting the removed portion with a conductive layer, and forming a protective film on the entire surface.
ここで各層のパターニングの方法としては、マスク蒸
着、あるいはマスク堆積、あるいはフォトリソグラフィ
ー、あるいはレーザースクライブ等の方法を用いること
ができる。Here, as a method of patterning each layer, a method such as mask evaporation, mask deposition, photolithography, or laser scribe can be used.
また、下部電極のパターニングと、半導体層及び上部
電極のパターニングは、どちらを先に行う工程でも製造
することができる。Further, the patterning of the lower electrode and the patterning of the semiconductor layer and the upper electrode can be manufactured by performing either step first.
また、導電層を第１図の例のように、２種類組み合わ
せて用いる場合には、第１の導電性層206を形成後、連
続して第２の導電性層207を形成する。このとき例えば
第１の導電性層として導電性樹脂としてのAgペーストを
用いることにより、電極とのコンタクトを良好にするこ
とができ、第２の導電性層として金属を用いることによ
って導電性層全体の抵抗を下げることができる。In the case where two types of conductive layers are used in combination as in the example of FIG. 1, after forming the first conductive layer 206, the second conductive layer 207 is formed continuously. At this time, for example, by using an Ag paste as a conductive resin as the first conductive layer, the contact with the electrode can be improved, and by using a metal as the second conductive layer, the entire conductive layer can be formed. Resistance can be reduced.
以下、本発明の集積化太陽電池及びその製造方法を実
施例によって詳細に説明する。Hereinafter, an integrated solar cell and a method of manufacturing the same according to the present invention will be described in detail with reference to examples.
（参考例１） まず、本発明に係わる参考例について説明する。Reference Example 1 First, a reference example according to the present invention will be described.
第２図に示した構成の集積化太陽電池を第４図〜第10
図に示した工程で製造した。The integrated solar cell having the structure shown in FIG.
It was manufactured by the steps shown in the figure.
導電性基板101として、厚さ0.15mm、幅30cm、長さ300
mの帯状基板を用い、連続成膜装置を用いたRoll to Rol
l法によって連続的に各層を形成した。As conductive substrate 101, thickness 0.15 mm, width 30 cm, length 300
Roll to Rol using a continuous film forming device
Each layer was continuously formed by the l method.
まず、第４図のように、導電性基板101上に熱CVD法に
よって絶縁層102としてSiO2を３μｍ堆積し、更にその
上に下部電極103としてAlを5000Å、Crを500Å蒸着し、
ZnOをスパッタ法によって5000Å堆積した。First, as shown in FIG. 4, 3 μm of SiO 2 is deposited as an insulating layer 102 on a conductive substrate 101 by a thermal CVD method, and further, 5000 μm of Al and 500 μm of Cr are deposited thereon as a lower electrode 103.
ZnO was deposited at 5000Å by sputtering.
次に、ｎ型アモルファスシリコンと真性アモルファス
シリコンゲルマンとｐ型微結晶シリコンとｎ型アモルフ
ァスシリコンと真性アモルファスシリコンとｐ型微結晶
シリコンをこの順に合計4000Å、プラズマCVD法によっ
て堆積し、タンデム型の半導体層104を形成し、ITOを70
0Å蒸着して、上部電極105を形成し、第５図に示した構
成の太陽電池を形成した。Then, n-type amorphous silicon, intrinsic amorphous silicon germane, p-type microcrystalline silicon, n-type amorphous silicon, intrinsic amorphous silicon, and p-type microcrystalline silicon were deposited in this order by a total of 4000 に よ っ て by a plasma CVD method to form a tandem semiconductor. Form layer 104 and make ITO 70
The upper electrode 105 was formed by vapor deposition at 0 ° to form a solar cell having the structure shown in FIG.
次に第６図に示すように、601の部分の上部電極105と
半導体104と下部電極103を波長1.06μｍのＱスイッチパ
ネルのYAGレーザーで、出力0.8W、周波数4KHZで直径50
μｍのレーザービームを照射し、速度100mm/secで走査
して除去した。Next, as shown in FIG. 6, the upper electrode 105, the semiconductor 104, and the lower electrode 103 in the portion 601 were irradiated with a Q switch panel YAG laser having a wavelength of 1.06 μm, output 0.8 W, frequency 4 KHZ, and diameter 50
Irradiation with a laser beam of μm was performed and scanning was performed at a speed of 100 mm / sec.
次に第７図に示すように、701の部分の半導体層104及
び上部電極105を、ＱスイッチパルスのYAGレーザーで波
長0.53μｍの第二高調波を使って出力0.3W、周波数4KHZ
で直径100μｍのレーザービームを照射し、速度100mm/s
ecで走査して除去し、下部電極103の一部が露出した構
造にした。Next, as shown in FIG. 7, the semiconductor layer 104 and the upper electrode 105 of the portion 701 are output from a Q switch pulse YAG laser using a second harmonic having a wavelength of 0.53 μm at an output of 0.3 W and a frequency of 4 KHZ.
Irradiates a laser beam with a diameter of 100 μm at a speed of 100 mm / s
The structure was removed by scanning with ec, and a part of the lower electrode 103 was exposed.
次に絶縁層106として、エポキシ樹脂をスクリーン印
刷で、厚さ約30μｍ、幅約150μｍで塗布して、第６
図、第７図の工程で形成した溝を埋め、第８図に示すよ
うな構成にした。Next, as the insulating layer 106, an epoxy resin is applied by screen printing to a thickness of about 30 μm and a width of about 150 μm,
The grooves formed in the steps of FIG. 7 and FIG. 7 are filled to obtain a configuration as shown in FIG.
次に、波長1.06μｍのＱスイッチパルスのYAGレーザ
ーで出力0.3W、周波数4KHZで直径50μｍのレーザービー
ムを照射して、100mm/secで走査して、第９図に示した
ように、901の部分のエポキシ樹脂を除去して、下部電
極103の一部を露出させた。この時エポキシ樹脂はレー
ザー光を吸収させるため、有色のものを使用した。Next, a laser beam having a diameter of 50 μm was radiated at a power of 0.3 W and a frequency of 4 KHZ by a YAG laser of a Q switch pulse having a wavelength of 1.06 μm, and scanning was performed at 100 mm / sec. As shown in FIG. Part of the epoxy resin was removed to expose a part of the lower electrode 103. At this time, a colored epoxy resin was used to absorb laser light.
次に、露出させた下部電極103の一部と隣接する太陽
電池の上部電極105の一部を導電層107で接続した。導電
層107としては、Agペーストを用い、スクリーン印刷
で、厚さ約30μｍ、幅約150μｍを第10図のように塗布
した。Next, a part of the exposed lower electrode 103 and a part of the adjacent upper electrode 105 of the solar cell were connected by the conductive layer 107. As the conductive layer 107, an Ag paste was applied by screen printing to a thickness of about 30 μm and a width of about 150 μm as shown in FIG.
次に、表面と裏面にEVAとポリビニルフロライド（PV
F）を用いて保護膜108を形成して、第２図に図示した接
続部の構成の集積化太陽電池を形成した。Next, EVA and polyvinyl fluoride (PV
F) was used to form a protective film 108, thereby forming an integrated solar cell having the connection portion configuration shown in FIG.
この様にして作製した帯状SUS基板を所望の大きさに
切断することによって、所望の出力電圧、出力電流の太
陽電池を形成することができた。By cutting the strip-shaped SUS substrate thus manufactured into a desired size, a solar cell having a desired output voltage and output current could be formed.
例えば30cm×30cmの基板で25段直列に集積化した集積
化太陽電池を作成し、AM1.5、100mw/cm2のソーラーシミ
ュレータで電流、電圧特性を測定したところ、出力電圧
30Vのとき最大出力10Wであった。For example, an integrated solar cell was fabricated by integrating 25 stages in series on a 30 cm × 30 cm substrate, and the current and voltage characteristics were measured with a solar simulator of AM 1.5 and 100 mw / cm 2.
At 30V, the maximum output was 10W.
（比較例１） 参考例１と同様の下部電極103、半導体層104、上部電
極105をもつ太陽電池を、特公昭62−5353号公報で開示
された方法で、第17図のような構造で直列化したとこ
ろ、上部電極105であるITOの膜厚が700Åと薄いため
に、段差部分で断線をおこし、集積化できなかった。(Comparative Example 1) A solar cell having the same lower electrode 103, semiconductor layer 104, and upper electrode 105 as in Reference Example 1 was obtained by the method disclosed in Japanese Patent Publication No. Sho 62-5353, using the structure shown in FIG. As a result of the serialization, the thickness of the ITO as the upper electrode 105 was as thin as 700 mm, so that disconnection occurred at the stepped portion and integration was not possible.
（参考例２） 参考例１と同様の製造工程で以下の点の異なる集積化
太陽電池を製造した。Reference Example 2 In the same manufacturing process as Reference Example 1, integrated solar cells having the following differences were manufactured.
絶縁層102として、LPCVD法によりSi3N4を3.5μｍ堆積
した。また下部電極103としてAgとＣ電極を積層し、半
導体層104として、ｐ型CdTeとｎ型CdSを積層し、上部電
極105はｎ型CdSが兼用し、上部電極105上にAgの集電電
極を形成した。また、絶縁層106としてシリコーン樹脂
をスクリーン印刷した。As the insulating layer 102, 3.5 μm of Si 3 N 4 was deposited by the LPCVD method. Ag and C electrodes are stacked as the lower electrode 103, p-type CdTe and n-type CdS are stacked as the semiconductor layer 104, the upper electrode 105 is also used as the n-type CdS, and the Ag collecting electrode is formed on the upper electrode 105. Was formed. In addition, a silicone resin was screen-printed as the insulating layer.
また、導電層107としては、Alをマスク蒸着により、
１μｍ堆積した。この様にして30cm×20cmの大きさで、
25段直列に接続した集積化太陽電池を製造したところ、
AM1.5、100mW/cm2で最大出力3.5Wが得られた。Further, as the conductive layer 107, Al is deposited by mask evaporation.
1 μm was deposited. In this way, with a size of 30 cm × 20 cm,
When we manufactured integrated solar cells connected in 25 stages in series,
A maximum output of 3.5 W was obtained at AM 1.5 and 100 mW / cm 2 .
（実施例） 第１図に示した本発明の集積化太陽電池を以下の工程
で製造した。(Example) The integrated solar cell of the present invention shown in FIG. 1 was manufactured by the following steps.
第11図〜第15図は第１図に示した本発明の集積化太陽
電池の製造工程の説明図である。11 to 15 are explanatory views of the manufacturing process of the integrated solar cell of the present invention shown in FIG.
まず絶縁基板201としてガラス基板を用い、下部電極2
02として透明電極であるSnO2をスパッタリングにより20
00Å形成し、フォトリソグラフィーによって第11図のよ
うにパターニングした。First, a glass substrate was used as the insulating substrate 201, and the lower electrode 2
02 is used as the transparent electrode SnO 2 by sputtering.
And formed by photolithography as shown in FIG.
次に半導体層203としてｐ型アモルファスSiC層と真性
アモルファスシリコン層とｎ型アモルファスシリコン層
を合計5000ÅプラズマCVD法により順次堆積し、上部電
極204として、Cr500ÅとAl5000Åを蒸着して第12図の構
造にした。Next, a p-type amorphous SiC layer, an intrinsic amorphous silicon layer, and an n-type amorphous silicon layer are sequentially deposited as a semiconductor layer 203 by a total of 5000 ° plasma CVD method, and Cr500 ° and Al5000 ° are deposited as an upper electrode 204 to form the structure shown in FIG. I made it.
次に透明電極のパターニング部分を中心に、フォトリ
ソグラフィーによって半導体層203と上部電極204をパタ
ーニングして、第13図のように下部電極202の一部が露
出した構造にした。Next, the semiconductor layer 203 and the upper electrode 204 were patterned by photolithography with a focus on the patterning portion of the transparent electrode, thereby obtaining a structure in which a part of the lower electrode 202 was exposed as shown in FIG.
次に絶縁層205としてプラズマCVD法により、アモルフ
ァスSiNを全面に１μｍ堆積し、フォトリソグラフィー
によって、第14図の様に隣接した太陽電池の一方の下部
電極の一部上と他方の上部電極の一部上のアモルファス
SiNを除去した。Next, 1 μm of amorphous SiN is deposited on the entire surface by plasma CVD as an insulating layer 205, and by photolithography, a part of one lower electrode of the adjacent solar cell and one Amorphous on the part
SiN was removed.
次に導電層206としてAgペーストをスクリーン印刷に
より塗布し、導電層207としてクリームハンダをスクリ
ーン印刷により塗布して第15図のごとく隣接した太陽電
池を直列接続した。Next, an Ag paste was applied by screen printing as the conductive layer 206, and cream solder was applied by screen printing as the conductive layer 207, and adjacent solar cells were connected in series as shown in FIG.
次に保護膜208として、EVAとPVFを形成し、第１図の
接続部を特徴とする第３図に示したような集積化太陽電
池を製造した。Next, EVA and PVF were formed as the protective film 208, and an integrated solar cell as shown in FIG. 3 which features the connecting portion of FIG. 1 was manufactured.
これを用いて、30cm×40cmの大きさで、20段直列に接
続した集積化太陽電池を測定したところAM1.5、100mW/c
m2で最大出力6Wであった。Using this, the size of 30cm × 40cm, integrated solar cells connected in series 20 stages, AM1.5, 100mW / c
The maximum output was 6 W at m 2 .
（参考例３） 第２図の接続部の構成で、基板として絶縁基板を用い
た集積化太陽電池を製造した。Reference Example 3 An integrated solar cell having the configuration of the connection portion shown in FIG. 2 and using an insulating substrate as a substrate was manufactured.
絶縁基板として、ポリエチレンテレフタラート（PE
T）を用い、下部電極103として、Alを4000Åと、Crを10
00Å蒸着して、フォトリソグラフィーにより、第11図の
ように下部電極をパターニングした。Polyethylene terephthalate (PE)
T), and as the lower electrode 103, Al was 4000 、 and Cr was 10
The lower electrode was patterned by photolithography as shown in FIG.
次に半導体層104として、プラズマCVD法によりｎ型ア
モルファスシリコン層と真性アモルファスシリコン層と
ｐ型微結晶シリコンとｎ型アモルファスシリコン層と真
性アモルファスシリコン層とｐ型微結晶シリコン層と
を、この順に合計6000Å堆積し、上部電極として透明電
極であるITOを700Å蒸着し、透明電極の上に、集電電極
としてAgペーストをスクリーン印刷によって塗布し、第
12図で集電電極を使用した構成にした。Next, as a semiconductor layer 104, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, a p-type microcrystalline silicon, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type microcrystalline silicon layer are formed in this order by a plasma CVD method. A total of 6000 mm was deposited, 700 mm of ITO, a transparent electrode, was deposited as an upper electrode, and an Ag paste was applied as a current collecting electrode on the transparent electrode by screen printing.
In FIG. 12, a configuration using a collecting electrode was adopted.
次にHClとFeCl2を含むエッチングペーストをスクリー
ン印刷して、下部電極の分離部分を中心にITOをエッチ
ングし、パターニングしたITOをマスクにして、半導体
層であるアモルファスシリコン層をエッチングして、第
13図に示すように下部電極の一部を露出させた。Next, an etching paste containing HCl and FeCl 2 is screen-printed, the ITO is etched around the separated part of the lower electrode, and the amorphous silicon layer as a semiconductor layer is etched using the patterned ITO as a mask.
As shown in FIG. 13, a part of the lower electrode was exposed.
次に絶縁層106として、ポリイミドのフォトレジスト
をディスペンサーによって、第13図の溝の部分に塗布
し、第８図の構成とした。Next, as an insulating layer 106, a photoresist of polyimide was applied to a groove portion in FIG. 13 by a dispenser to obtain a structure in FIG.
次にディスペンサーで遮光物質をレジスト上に部分的
に塗布して、紫外線を照射し、第９図のごとく下部電極
の一部を露出させるようにレジストをアッシングした。Next, a light-shielding substance was partially applied onto the resist with a dispenser, and the resist was ashed so as to expose a part of the lower electrode as shown in FIG. 9 by irradiating ultraviolet rays.
次に導電層107としてAgペーストをディスペンサーで
第10図のごとく塗布して、隣接する太陽電池の一方の下
部電極と他方の上部電極を接続し、保護膜108として、E
VAとPVFをコーティングして、第２図の接続部の構成の
集積化太陽電池を製造した。Next, an Ag paste was applied as a conductive layer 107 with a dispenser as shown in FIG. 10, and one lower electrode and the other upper electrode of the adjacent solar cell were connected.
VA and PVF were coated to produce an integrated solar cell having the connection configuration shown in FIG.
これを用いて、30cm×40cmの大きさで、10段直列に接
続した集積化太陽電池を製造したところAM1.5、100mW/c
m2で最大出力9Wであった。Using this, 30cm × 40cm size, integrated solar cells were connected in 10 stages connected in series, AM1.5, 100mW / c
The maximum output was 9 W at m 2 .
［発明の効果］ 以上、説明したように本発明の集積化太陽電池によっ
て、一体基板上で太陽電池を直列に集積化することによ
って、直列化のためのリード線の断線等の事故がなくな
り、低コストで信頼性の高い集積化太陽電池を提供でき
た。[Effect of the Invention] As described above, by integrating solar cells in series on an integrated substrate by the integrated solar cell of the present invention, accidents such as disconnection of lead wires for serialization are eliminated, A low-cost and highly reliable integrated solar cell could be provided.
また、一体基板上で直列に接続される太陽電池の端部
あるいは全部が、隣接する太陽電池の一方の下部電極と
他方の上部電極の接続部分となる一部を除いて絶縁層で
被覆されていることにより、直列化する太陽電池間のリ
ーク電流が無くなり、特性が向上し、絶縁耐圧が大幅に
向上した。また、半導体層と上部電極を同時にパターニ
ングできる構成を有していることにより、半導体層の形
成後、半導体層が長時間大気にさらされることによる素
子への悪影響が無くなり、また工程も簡単化して低コス
ト化できた。In addition, the ends or all of the solar cells connected in series on the integrated substrate are covered with an insulating layer except for a part that becomes a connection portion between one lower electrode and the other upper electrode of an adjacent solar cell. As a result, the leakage current between the serialized solar cells was eliminated, the characteristics were improved, and the withstand voltage was greatly improved. In addition, since the semiconductor layer and the upper electrode are configured to be patterned at the same time, there is no adverse effect on the device due to the semiconductor layer being exposed to the air for a long time after the formation of the semiconductor layer, and the process is simplified. Cost was reduced.
また、隣接する太陽電池を直列に接続する材料とし
て、上部電極と独立した導電層を用いることによって、
上部電極が薄い場合においても段差によって断線するこ
とが無くなった。Also, by using a conductive layer independent of the upper electrode as a material for connecting adjacent solar cells in series,
Even when the upper electrode is thin, disconnection due to a step is eliminated.
また、特に絶縁層として合成樹脂を、また導電層とし
てAgペースト等の導電性樹脂を用いることによって、製
造工程が簡易になり、低コストで信頼性の高い集積化太
陽電池を提供することができた。Further, in particular, by using a synthetic resin as the insulating layer and a conductive resin such as Ag paste as the conductive layer, the manufacturing process is simplified, and a highly reliable integrated solar cell at low cost can be provided. Was.
また、導電層として、金属と導電性樹脂を組み合わせ
て二層構成とすることにより、電極とのコンタクトを良
好にすることができ、また導電性層全体としての抵抗を
下げることができるという効果が得られる。In addition, by forming a two-layer structure by combining a metal and a conductive resin as the conductive layer, it is possible to improve the contact with the electrode and reduce the resistance of the entire conductive layer. can get.
第１図は、本発明の集積化太陽電池の接続部の実施例を
示す断面図である。 第２図は、本発明の集積化太陽電池の接続部の参考例を
示す断面図である。 第３図は、本発明の集積化太陽電池の接続部の一例の概
観図である。 第４図〜第10図は、第２図の集積化太陽電池の製造工程
の断面図である。 第11図〜第15図は、第１図の集積化太陽電池の製造工程
の断面図である。 第16図は、従来の集積化太陽電池の一例の平面図であ
る。 第17図は、従来の集積化太陽電池の他の一例の断面図で
ある。 101……導電性基板、102……絶縁層、103……下部電
極、104……半導体層、105……上部電極、106……絶縁
層、107……導電層、108……保護膜、109……下部電極
の接続部分、110……上部電極の接続部分、201……絶縁
基板、202……下部電極、203……半導体層、204……上
部電極、205……絶縁層、206……第１の導電層、207…
…第２の導電層、208……保護膜、209……下部電極の接
続部分、210……上部電極の接続部分、301……（分割さ
れた）太陽電池、302……接続部分、303,304……引き出
し電極、601……下部電極と半導体層と上部電極を除去
する部分、701……半導体層と上部電極を除去する部
分、901……絶縁層を除去する部分、1601……絶縁基
板、1602……下部電極、1603……アモルファスシリコン
層、1604……上部電極、1605……引き出し電極、1701…
…絶縁基板、1702……下部電極、1703……アモルファス
シリコン層、1704……上部電極、1705……絶縁膜。FIG. 1 is a sectional view showing an embodiment of a connection portion of the integrated solar cell of the present invention. FIG. 2 is a cross-sectional view showing a reference example of a connection portion of the integrated solar cell of the present invention. FIG. 3 is a schematic view showing an example of a connection portion of the integrated solar cell of the present invention. 4 to 10 are cross-sectional views showing the steps of manufacturing the integrated solar cell shown in FIG. 11 to 15 are cross-sectional views of a manufacturing process of the integrated solar cell of FIG. FIG. 16 is a plan view of an example of a conventional integrated solar cell. FIG. 17 is a sectional view of another example of the conventional integrated solar cell. 101 conductive substrate, 102 insulating layer, 103 lower electrode, 104 semiconductor layer, 105 upper electrode, 106 insulating layer, 107 conductive layer, 108 protective film, 109 ... Connection part of lower electrode, 110 connection part of upper electrode, 201 insulating substrate, 202 lower electrode, 203 semiconductor layer, 204 upper electrode, 205 insulating layer, 206 A first conductive layer, 207 ...
... Second conductive layer, 208 ... Protective film, 209 ... Connection part of lower electrode, 210 ... Connection part of upper electrode, 301 ... (divided) solar cell, 302 ... Connection part, 303,304 ... ... Leader electrode, 601, a portion from which the lower electrode, the semiconductor layer, and the upper electrode are removed; 701, a portion from which the semiconductor layer and the upper electrode are removed; 901, a portion from which the insulating layer is removed; 1601, an insulating substrate; ... lower electrode, 1603 ... amorphous silicon layer, 1604 ... upper electrode, 1605 ... lead-out electrode, 1701 ...
... an insulating substrate, 1702 ... a lower electrode, 1703 ... an amorphous silicon layer, 1704 ... an upper electrode, 1705 ... an insulating film.
Claims (7)
する複数の太陽電池を、接続して集積化される集積化太
陽電池において、 前記半導体層と前記上部電極の一部をパターニング除去
することによって、前記下部電極の一部に前記半導体層
及び前記上部電極で覆われていない除去領域が形成され
ていること、前記除去領域を含む隣接する太陽電池の対
向する端部とこれらの端部の間の領域あるいは全面を被
覆する絶縁層が形成されていること、隣接する太陽電池
の一方の下部電極の前記除去領域上に形成された前記絶
縁層の一部と、他方の上部電極上に形成された前記絶縁
層の一部とを取り除くことによって接続部が形成されて
いること、及び前記隣接する太陽電池のそれぞれに形成
された接続部を前記絶縁層をまたいで接続するように導
電層が形成されていること、を特徴とする集積化太陽電
池。1. An integrated solar cell in which a plurality of solar cells having a lower electrode, a semiconductor layer, and an upper electrode are connected and integrated, and a part of the semiconductor layer and a part of the upper electrode are removed by patterning. By doing so, a removal region not covered by the semiconductor layer and the upper electrode is formed in a part of the lower electrode, and opposing ends of adjacent solar cells including the removal region and these ends That an insulating layer covering the region between the portions or the entire surface is formed, a part of the insulating layer formed on the removed region of one lower electrode of the adjacent solar cell, and on the other upper electrode A connection portion is formed by removing a part of the insulating layer formed on the solar cell, and a connection portion formed on each of the adjacent solar cells is connected so as to connect over the insulating layer. An integrated solar cell, wherein an electric layer is formed.
ように、太陽電池全面に保護層が形成されている請求項
１に記載の集積化太陽電池。2. The integrated solar cell according to claim 1, further comprising a protective layer formed on the entire surface of the solar cell so as to cover the insulating layer and the conductive layer.
に記載の集積化太陽電池。3. The insulating layer according to claim 1, wherein said insulating layer is made of a synthetic resin.
An integrated solar cell according to item 1.
に記載の集積化太陽電池。4. The semiconductor device according to claim 1, wherein said insulating layer is made of an inorganic material.
An integrated solar cell according to item 1.
ら成る請求項１に記載の集積化太陽電池。5. The integrated solar cell according to claim 1, wherein said conductive layer is made of metal or conductive resin.
脂から成る層とを組み合わせた二層構成から成る請求項
１に記載の集積化太陽電池。6. The integrated solar cell according to claim 1, wherein the conductive layer has a two-layer structure in which a layer made of a metal and a layer made of a conductive resin are combined.
るいはアモルファスシリコン合金から成る請求項１に記
載の集積化太陽電池。7. The integrated solar cell according to claim 1, wherein said semiconductor layer is made of amorphous silicon or an amorphous silicon alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2235892A JP2986875B2 (en) | 1990-09-07 | 1990-09-07 | Integrated solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2235892A JP2986875B2 (en) | 1990-09-07 | 1990-09-07 | Integrated solar cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04116986A JPH04116986A (en) | 1992-04-17 |
| JP2986875B2 true JP2986875B2 (en) | 1999-12-06 |
Family
ID=16992790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2235892A Expired - Fee Related JP2986875B2 (en) | 1990-09-07 | 1990-09-07 | Integrated solar cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2986875B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2332178A2 (en) * | 2008-09-01 | 2011-06-15 | LG Electronics Inc. | Thin-film type solar cell and method for manufacturing the same |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000007249A1 (en) * | 1998-07-27 | 2000-02-10 | Citizen Watch Co., Ltd. | Solar cell and method of producing the same, and mask for photolithography for producing solar cell |
| AU772539B2 (en) * | 1999-07-29 | 2004-04-29 | Kaneka Corporation | Method for cleaning photovoltaic module and cleaning apparatus |
| JP4233741B2 (en) * | 2000-09-27 | 2009-03-04 | 三菱重工業株式会社 | Solar cell module and manufacturing method thereof |
| US20070079866A1 (en) * | 2005-10-07 | 2007-04-12 | Applied Materials, Inc. | System and method for making an improved thin film solar cell interconnect |
| KR101011228B1 (en) * | 2008-08-27 | 2011-01-26 | 주식회사 티지솔라 | Solar Cell and Method For Fabricating The Same |
| KR101011222B1 (en) * | 2008-08-26 | 2011-01-26 | 주식회사 티지솔라 | Solar Cell and Method For Fabricating The Same |
| US20100071765A1 (en) * | 2008-09-19 | 2010-03-25 | Peter Cousins | Method for fabricating a solar cell using a direct-pattern pin-hole-free masking layer |
| DE102009020482A1 (en) * | 2009-05-08 | 2010-11-11 | Forschungszentrum Jülich GmbH | Process for the production and series connection of photovoltaic elements to a solar module and solar module |
| WO2010146651A1 (en) * | 2009-06-15 | 2010-12-23 | Wang Haibiao | Production method for photoelectric converter |
| JP5054157B2 (en) | 2010-06-17 | 2012-10-24 | 昭和シェル石油株式会社 | CIS thin film solar cell |
| JP5434827B2 (en) * | 2010-07-12 | 2014-03-05 | 富士電機株式会社 | Solar cell, laminated substrate for solar cell, and manufacturing method thereof |
| KR101114099B1 (en) * | 2010-07-30 | 2012-02-22 | 엘지이노텍 주식회사 | Solar cell apparatus and method of fabricating the same |
| JP5608030B2 (en) * | 2010-09-29 | 2014-10-15 | 昭和シェル石油株式会社 | Method for producing compound thin film solar cell module |
| JP2013149697A (en) * | 2012-01-18 | 2013-08-01 | Fujifilm Corp | Integrated soar cell manufacturing method |
| JP2013183030A (en) * | 2012-03-02 | 2013-09-12 | Panasonic Corp | Solar cell and manufacturing method of the same |
| JP6076302B2 (en) * | 2014-09-22 | 2017-02-08 | 株式会社東芝 | Photoelectric conversion element |
| GB2575792B (en) | 2018-07-20 | 2021-11-03 | Dyson Technology Ltd | Stack for an energy storage device |
-
1990
- 1990-09-07 JP JP2235892A patent/JP2986875B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2332178A2 (en) * | 2008-09-01 | 2011-06-15 | LG Electronics Inc. | Thin-film type solar cell and method for manufacturing the same |
| EP2332178A4 (en) * | 2008-09-01 | 2012-06-06 | Lg Electronics Inc | Thin-film type solar cell and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04116986A (en) | 1992-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5259891A (en) | Integrated type solar battery | |
| JP2986875B2 (en) | Integrated solar cell | |
| US6468828B1 (en) | Method of manufacturing lightweight, high efficiency photovoltaic module | |
| AU2004204637B2 (en) | Transparent thin-film solar cell module and its manufacturing method | |
| EP0971417A2 (en) | Photovoltaic element and production method therefor | |
| US4808242A (en) | Photovoltaic device and a method of manufacturing thereof | |
| JP3815875B2 (en) | Manufacturing method of integrated thin film photoelectric conversion device | |
| WO2008026581A1 (en) | Solar battery module | |
| JP2005277113A (en) | Stacked solar cell module | |
| JP2000150929A (en) | Photovoltaic element and manufacture thereof | |
| EP4128527A1 (en) | Method for making photovoltaic slats for photovoltaic blinds | |
| JP4568531B2 (en) | Integrated solar cell and method of manufacturing integrated solar cell | |
| US4764476A (en) | Method of making photoelectric conversion device | |
| JPH06132552A (en) | Photovoltaic element and manufacture thereof | |
| JPS6357952B2 (en) | ||
| EP4318604A1 (en) | Thin film photovoltaic devices and method of manufacturing them | |
| JPH0571150B2 (en) | ||
| JP2004260013A (en) | Photoelectric converter and its manufacturing method | |
| JPH06268241A (en) | Thin-film solar cell and manufacture thereof | |
| JP2883370B2 (en) | Photovoltaic device | |
| JP2869178B2 (en) | Photovoltaic device | |
| JP2630657B2 (en) | Manufacturing method of integrated multilayer amorphous solar cell | |
| JP4153669B2 (en) | Integrated photovoltaic device and method for manufacturing the same | |
| JP2647892B2 (en) | Optical super power device | |
| JP2744058B2 (en) | Method for manufacturing photovoltaic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |