JP2983096B2 - Manufacturing method of laminated voltage non-linear resistor - Google Patents
Manufacturing method of laminated voltage non-linear resistorInfo
- Publication number
- JP2983096B2 JP2983096B2 JP3311713A JP31171391A JP2983096B2 JP 2983096 B2 JP2983096 B2 JP 2983096B2 JP 3311713 A JP3311713 A JP 3311713A JP 31171391 A JP31171391 A JP 31171391A JP 2983096 B2 JP2983096 B2 JP 2983096B2
- Authority
- JP
- Japan
- Prior art keywords
- laminate
- varistor
- laminated
- sintered body
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Thermistors And Varistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、素体表面の絶縁性化手
段を改良した積層形電圧非直線抵抗器（以下バリスタと
称す）の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated voltage non-linear resistor (hereinafter referred to as a "varistor") having improved means for insulating the surface of a body.
【０００２】[0002]
【従来の技術】一般に、積層形のバリスタは、図５に示
すように、複数の内部電極１１と、例えばＺｎＯを主成
分とした焼結体１２とが積層構造になっており、内部電
極１１の外部取り出し電極部１３以外を前記焼結体１２
で囲まれた構造からなるものであるが、電圧非直線性，
制限電圧比、さらには耐湿性及び耐サ−ジ性などの諸特
性の向上を目的とし、特公平１−４２６１１号公報に開
示された技術がある。2. Description of the Related Art Generally, as shown in FIG. 5, a laminated varistor has a laminated structure of a plurality of internal electrodes 11 and a sintered body 12 containing ZnO as a main component. Of the sintered body 12
It consists of a structure surrounded by
There is a technique disclosed in Japanese Patent Publication No. 1-26111 for the purpose of improving various characteristics such as a limited voltage ratio and furthermore, moisture resistance and surge resistance.
【０００３】この技術は、図６に示すように、複数の内
部電極１１とバリスタ組成物焼結体１４及び絶縁組成物
焼結体１５を積層化してなる構造において、内部電極１
１の表裏いずれか一方が、絶縁組成物焼結体１５に接
し、かつ最外装が絶縁組成物焼結体１５からなり、内部
電極１１が外部取り出し電極１３と接続する部分を除い
てバリスタ組成物焼結体１４及び絶縁組成物焼結体１５
で囲まれた構成を有している。図５及び図６図中１６は
外部電極である。As shown in FIG. 6, this technique employs a structure in which a plurality of internal electrodes 11, a varistor composition sintered body 14, and an insulating composition sintered body 15 are laminated, and the internal electrode 1
1 is in contact with the insulating composition sintered body 15, and the outermost part is made of the insulating composition sintered body 15, and the varistor composition except for the part where the internal electrode 11 is connected to the external extraction electrode 13. Sintered body 14 and insulating composition sintered body 15
It has a configuration surrounded by. In FIGS. 5 and 6, reference numeral 16 denotes an external electrode.
【０００４】このような構成になる積層形バリスタは、
絶縁組成物焼結体１５を構成する結晶粒自体が絶縁化し
ているため、電界は、表面全体に分散し、絶縁組成物焼
結体１５表面での放電劣化はなく、優れた絶縁効果を発
揮できると同時に、耐湿及び耐サ−ジ特性、さらには電
圧非直線性並びに制限電圧比においても優れた特性が得
られる。A laminated varistor having such a structure is
Since the crystal grains constituting the insulating composition sintered body 15 are insulated, the electric field is dispersed over the entire surface, there is no discharge deterioration on the surface of the insulating composition sintered body 15, and an excellent insulating effect is exhibited. At the same time, excellent characteristics are obtained in terms of humidity resistance and surge resistance, as well as voltage non-linearity and limiting voltage ratio.
【０００５】しかしながら、このような構成になる積層
形バリスタを作る手段として、バリスタ組成物焼結体１
４及び絶縁組成物焼結体１５となる生シ−トを個々に作
製しなければならず、これらを間違いなく管理し、かつ
間違いのない積層作業をしなければならず、また、より
優れた耐湿及び絶縁効果を得るためには、バリスタ組成
物焼結体が露出する側面部にガラスコ−ト層又はセラミ
ックコ−ト層を形成する必要があり、作業性を考慮した
ときに、必ずしも最良の技術とは言えなかった。[0005] However, as means for producing a laminated varistor having such a structure, a varistor composition sintered body 1 is used.
4 and the raw sheet to be the insulating composition sintered body 15 must be individually manufactured, these must be managed without fail, and the stacking operation without error must be performed. In order to obtain the moisture resistance and the insulating effect, it is necessary to form a glass coat layer or a ceramic coat layer on the side surface where the varistor composition sintered body is exposed. It wasn't technology.
【０００６】他方、特開平２−１８９９０３号公報に開
示されているように、バリスタ層と内部電極層とを交互
に積層してなる積層体の外表面に酸化アンチモンを拡散
させて絶縁層を形成する技術も提案されている。On the other hand, as disclosed in JP-A-2-189903, an insulating layer is formed by diffusing antimony oxide on the outer surface of a laminate in which varistor layers and internal electrode layers are alternately laminated. A technique to do this has also been proposed.
【０００７】この技術は、焼成炉内にて加熱焼結する際
に、炉内に酸化アンチモン粉末を配設しておき、積層体
の焼成と同時に酸化アンチモンを蒸発拡散させるように
するか、又は、積層体を焼成して焼結体を形成した後、
焼結体と酸化アンチモンとを高温で再熱処理し、酸化ア
ンチモンを蒸発拡散させる方法によって、焼結体表面に
Ｚｎ7 Ｓｂ3 Ｏの化合物の絶縁層を形成するようにする
ものである。According to this technique, when heating and sintering in a firing furnace, antimony oxide powder is provided in the furnace, and the antimony oxide is evaporated and diffused simultaneously with firing of the laminate. After firing the laminate to form a sintered body,
The sintered body and the antimony oxide are heat-treated again at a high temperature to evaporate and diffuse the antimony oxide to form an insulating layer of a Zn 7 Sb 3 O compound on the surface of the sintered body.
【０００８】しかして、上記構成によって積層体の外表
面に形成される絶縁層は、ＺｎＯとＳｂ2 Ｏ3 のスピネ
ル化合物であり、表面部分のＺｎＯを均一に化合物化す
るためには、多量の酸化アンチモンを必要とする。した
がって、酸化アンチモンが素子内部まで拡散し内部のＺ
ｎＯの粒成長を抑制するためバリスタ電圧を任意にコン
トロ−ルすることが困難であった。However, the insulating layer formed on the outer surface of the laminate by the above structure is a spinel compound of ZnO and Sb 2 O 3 . Requires antimony oxide. Therefore, antimony oxide diffuses into the element and Z
It was difficult to arbitrarily control the varistor voltage in order to suppress the grain growth of nO.
【０００９】また、上記構成では、いずれにして酸化ア
ンチモンを蒸発させ、積層体又は焼結体と反応させ絶縁
層を形成するとしても、積層体又は焼結体の炉内への配
置面となる部分への酸化アンチモンの拡散はならず、積
層体又は焼結体の外表面全体に均一に絶縁層を形成する
のが困難であった。Further, in the above structure, even if the antimony oxide is evaporated and reacted with the laminate or the sintered body to form an insulating layer, the surface of the laminate or the sintered body in the furnace is formed. Antimony oxide did not diffuse to the portion, and it was difficult to form an insulating layer uniformly on the entire outer surface of the laminate or sintered body.
【００１０】そのため、積層体又は焼結体の外表面全体
に絶縁層を積層体の外表面全体に満遍なく酸化アンチモ
ンを蒸発拡散する必要があり、そのため積層体又は焼結
体の炉内への配置に工夫が必要であり、作業性に問題が
あった。[0010] Therefore, it is necessary to evaporate and diffuse the antimony oxide over the entire outer surface of the laminated body with an insulating layer over the entire outer surface of the laminated body or sintered body. In addition, there was a problem in workability.
【００１１】[0011]
【発明が解決しようとする課題】以上述べたように、従
来提案されている積層体外表面の絶縁性化手段では作業
性に問題があり、また、外表面を完全に絶縁化するには
問題があり、効率的に所期の目的を達成することは困難
であった。As described above, the conventional means for insulating the outer surface of the laminate has a problem in workability, and there is a problem in completely insulating the outer surface. It was difficult to achieve the intended purpose efficiently.
【００１２】本発明は、上記の点に鑑みて成されたもの
で、作業性良好にして素体表面の絶縁化を行うことによ
って、表面での放電劣化を防止し、耐湿及び耐サ−ジ特
性良好な積層形電圧非直線抵抗器の製造方法を提供する
ことを目的とするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a workability improved to insulate a surface of a body to prevent discharge deterioration on the surface and to prevent moisture and surge resistance. It is an object of the present invention to provide a method for manufacturing a laminated voltage non-linear resistor having good characteristics.
【００１３】[0013]
【課題を解決するための手段】本発明による積層形電圧
非直線抵抗器の製造方法は、内部電極を形成した酸化亜
鉛を主成分としたバリスタ組成物生シ−トを前記内部電
極の端面が両側面に交互に導出するように複数枚積層し
て焼結し、バリスタ素子積層体を形成した後、この積層
体をＣｕ2 Ｏ，Ｌｉ2 Ｏ，Ａｇ2 Ｏ，Ｋ2 Ｏからなる一
価の酸化物微粉末をＡｌ2 Ｏ3 又はＭｇＯの結晶粒子中
に分散した粉体中で包囲して熱処理し、前記積層体の外
表面を絶縁化することを特徴とするものである。According to the present invention, there is provided a method of manufacturing a laminated voltage non-linear resistor, comprising the steps of: forming a raw sheet of a varistor composition containing zinc oxide as a main component and forming an internal electrode; After laminating and sintering a plurality of sheets so as to lead them alternately to both sides to form a varistor element laminate, the laminate is made of a monovalent material made of Cu 2 O, Li 2 O, Ag 2 O, and K 2 O. The oxide fine powder of (1) is surrounded in a powder dispersed in crystal particles of Al 2 O 3 or MgO and heat-treated to insulate the outer surface of the laminate.
【００１４】[0014]
【作用】以上のような構成によれば、積層体を熱処理す
る際に積層体を一価の元素を分散した粉体中で包囲し、
この一価の元素が積層体の内部に拡散され、その部分の
ＺｎＯの結晶が絶縁体化し比抵抗が大きくなるもので、
少量の一価の元素微粉末でよい。また、積層体を粉体中
で包囲して拡散するので、積層体表面が均一に高抵抗化
される。According to the above construction, when the laminate is heat-treated, the laminate is surrounded by a powder in which a monovalent element is dispersed,
This monovalent element is diffused into the inside of the laminate, and the ZnO crystal in that portion becomes an insulator and the specific resistance increases.
A small amount of monovalent elemental fine powder may be used. Further, since the laminate is surrounded and diffused in the powder, the surface of the laminate is uniformly increased in resistance.
【００１５】[0015]
【実施例】以下、本発明の実施例について説明する。Embodiments of the present invention will be described below.
【００１６】すなわち、図２に示すように、焼結後バリ
スタ機能を有する焼結体となる原料として酸化亜鉛を主
成分とし、添加物として酸化ビスマスと、その他に酸化
コバルト，酸化マンガン，酸化ニッケル，酸化クロム，
酸化マグネシウム，酸化鉛，酸化アルミニウム，酸化チ
タン，酸化アンチモン，酸化バリウム，酸化ケイ素，酸
化ホウ素などの中から２種類又は３種類以上加え、ボ−
ルミルで乾燥後６００〜９５０℃で仮焼し、しかる後、
粉砕し有機バインダ−とともに溶媒中に分散させスラリ
−状とする。次に、ドクタ−ブレ−ド法で１０μｍ〜３
ｍｍ程度の均一なバリスタ組成物生シ−ト１を形成す
る。しかして、この生シ−ト１の一方面に金，白金，パ
ラジウム，銀，ロジウム又はこれらのうちの二つ以上の
合金からなる金属ペ−ストを用いて所定の大きさにスク
リ−ン印刷によって内部電極２を形成し、しかる後、図
３に示すようにこの内部電極２が積層間で例えば長さ方
向で若干ずれるようにし、かつ内部電極２同志が接しな
いようにして前記生シ−ト１を複数本積み重ね、さらに
少なくとも前記内部電極２が露出する面に内部電極を形
成しない前記生シ−ト１と同一組成からなる保護シ−ト
３を積み重ね圧着した後、内部電極の外部取り出し電極
との接続部となる内部電極２の端面が両側面に交互に導
出するように、所定の大きさに点線部分を切断し９００
〜１２００℃で０．５〜８時間焼結し、図４に示すよう
に内部電極２の外部電極と接続する部分を除いてバリス
タ組成物焼結体４で囲まれたバリスタ素子積層体５を形
成する。次に、この積層体４をＡｌ2 Ｏ3 又はＭｇ2 Ｏ
の結晶粒子中にＣｕ2 Ｏ，Ｌｉ2 Ｏ，Ａｇ2 Ｏ又はＫ2
Ｏなどの一価の酸化物微粉末を分散した粉体中で包囲し
て５００〜９００℃で１０〜６０分熱処理し、図１に示
すように前記積層体５の外表面を絶縁化６したのち、前
記積層体５の内部電極２を導出させた両側面に銀電極材
を塗布し４５０〜８５０℃で焼き付けて、両側面に内部
電極２と接続した外部電極７を形成し完成品としてなる
ものである。That is, as shown in FIG. 2, zinc oxide is a main component as a raw material for forming a sintered body having a varistor function after sintering, bismuth oxide as an additive, and other components such as cobalt oxide, manganese oxide and nickel oxide. , Chromium oxide,
Add two or more of magnesium oxide, lead oxide, aluminum oxide, titanium oxide, antimony oxide, barium oxide, silicon oxide, boron oxide, etc.
After calcining at 600 to 950 ° C after drying with a mill,
The powder is pulverized and dispersed in a solvent together with an organic binder to form a slurry. Next, 10 μm to 3 μm by doctor blade method.
A uniform varistor composition sheet 1 of about mm is formed. The green sheet 1 is screen-printed to a predetermined size using a metal paste made of gold, platinum, palladium, silver, rhodium or an alloy of two or more of them. Then, as shown in FIG. 3, the internal electrodes 2 are slightly shifted between the laminations, for example, in the length direction, and the raw electrodes 2 are not brought into contact with each other. After a plurality of sheets 1 are stacked and a protective sheet 3 having the same composition as the raw sheet 1 having no internal electrodes formed on at least the surface where the internal electrodes 2 are exposed is pressed and crimped, the internal electrodes are taken out from the outside. The dotted line portion is cut to a predetermined size so that the end faces of the internal electrodes 2 to be connected to the electrodes are alternately led out to both side faces.
The varistor element laminated body 5 surrounded by the varistor composition sintered body 4 except for a portion connected to the external electrode of the internal electrode 2 as shown in FIG. Form. Next, the laminate 4 is made of Al 2 O 3 or Mg 2 O.
Cu 2 O, Li 2 O, Ag 2 O or K 2
The outer surface of the laminate 5 was insulated 6 as shown in FIG. 1 by enclosing in a powder in which a monovalent oxide fine powder such as O was dispersed and heat-treated at 500 to 900 ° C. for 10 to 60 minutes. Thereafter, a silver electrode material is applied to both sides of the laminate 5 from which the internal electrodes 2 are led out, and baked at 450 to 850 ° C. to form external electrodes 7 connected to the internal electrodes 2 on both sides to obtain a finished product. Things.
【００１７】以上のような構成になる積層形電圧非直線
抵抗器の製造方法によれば、積層体４の熱処理によって
この積層体５を包囲している粉体中に分散されている一
価の元素微粉末であるＣｕ，Ｌｉ，Ａｇ又はＫが積層体
５の内部に拡散され、その部分のＺｎＯ結晶が絶縁体化
し比抵抗が大きくなりその部分が均一に高抵抗化され
る。According to the manufacturing method of the laminated voltage non-linear resistor having the above-described structure, the monovalent monodisperse dispersed in the powder surrounding the laminated body 5 by the heat treatment of the laminated body 4 is obtained. Cu, Li, Ag, or K, which is an elemental fine powder, is diffused into the inside of the laminate 5, the ZnO crystal in that portion becomes an insulator, the specific resistance increases, and the portion has a uniform high resistance.
【００１８】また、ＺｎＯ結晶自体の抵抗を大きくする
ものであるため、積層体５を包囲する粉体中に分散させ
る拡散物としてのＣｕ2 Ｏ，Ｌｉ2 Ｏ，Ａｇ2 Ｏ又はＫ
2 Ｏなどの一価の酸化物微粉末の使用は、少量で優れた
積層体５表面の絶縁化６が可能となる。したがって、耐
湿及び耐サ−ジ特性の優れた積層形バリスタが得られ
る。Further, since the resistance of the ZnO crystal itself is increased, Cu 2 O, Li 2 O, Ag 2 O or K 2 as a diffusion material dispersed in the powder surrounding the laminate 5 is used.
Use of a monovalent oxide fine powder such as 2 O makes it possible to provide excellent insulation 6 on the surface of the laminate 5 with a small amount. Therefore, a laminated varistor excellent in moisture resistance and surge resistance can be obtained.
【００１９】また、従来技術として前述した特開平２−
１８９９０３号公報にて開示されている技術に比し作業
性良好にして信頼性の高い積層体表面の絶縁体化が達成
できる。Further, Japanese Patent Application Laid-Open No.
As compared with the technique disclosed in Japanese Patent Application Laid-Open No. 189903, workability can be improved and a highly reliable insulator can be obtained on the surface of the laminate.
【００２０】次に、本発明の効果について実施例によっ
て説明する。ＺｎＯ ９５．５モル％，Ｃｏ2 Ｏ3 １
モル％，ＭｎＯ １モル％，Ｃｒ2 Ｏ3 １モル％，Ｓ
ｂ2 Ｏ3 １モル％，Ｂｉ2 Ｏ3 ０．５モル５％の組
成比からなる原料を用い、内部電極として白金を用い、
また熱処理する際の粉体としてＭｇＯの結晶粒子中にＬ
ｉ2 Ｏ3 を１モル％分散したものを用い、さらに外部電
極として銀電極を用い、前記実施例の説明で述べた手段
により形成した本発明による積層形バリスタと、表面絶
縁化処理を行わず、その他は本発明と同一構成になる従
来例の耐サ−ジ特性（８×２０μｓｅｃ １００Ａ２０
回印加後の△Ｖ１ｍＡ（％）測定）及び耐湿特性を調べ
た結果、表１に示すようになった。Next, the effects of the present invention will be described with reference to examples. 95.5 mol% of ZnO, Co 2 O 3 1
Mol%, MnO 1 mol%, Cr 2 O 3 1 mol%, S
A raw material having a composition ratio of b 2 O 3 1 mol% and Bi 2 O 3 0.5 mol 5% was used, platinum was used as an internal electrode,
In addition, as a powder for heat treatment, L
A layered varistor according to the present invention formed by the means described in the description of the above-described embodiment using a 1% by mole dispersion of i 2 O 3 , further using a silver electrode as an external electrode, and performing no surface insulation treatment Other than that, the surge resistance characteristics of the conventional example having the same configuration as the present invention (8 × 20 μsec 100A20
As a result of examining (ΔV1 mA (%) measurement after repeated application) and humidity resistance, the results are as shown in Table 1.
【００２１】[0021]
【表１】 [Table 1]
【００２２】なお、従来技術の中で述べた特開平２−１
８９９０３号公報に開示された技術によって表面を絶縁
化することを試みたが、多くの積層体の表面全体を均一
に絶縁化するためには作業性に難点があると同時に、所
望の絶縁層形成が困難で実用的でなかった。Incidentally, Japanese Patent Application Laid-Open No. 2-1 described in the prior art.
Attempts have been made to insulate the surface by the technique disclosed in Japanese Patent Application Laid-Open No. 89903, but there are difficulties in workability in order to uniformly insulate the entire surface of many laminates, and at the same time, a desired insulating layer is formed. Was difficult and impractical.
【００２３】表１から明らかなように、本発明のものは
従来例のものと比較して耐サ−ジ特性及び耐湿特性とも
著しく優れている結果を示し、本発明の優位性を実証し
た。As is apparent from Table 1, the present invention exhibited remarkably superior surge and moisture resistance characteristics as compared with the conventional example, demonstrating the superiority of the present invention.
【００２４】[0024]
【発明の効果】本発明によれば、複数の内部電極の外部
取り出し電極と接続する部分を除いて焼結体で囲まれた
バリスタ素子積層体の外表面を絶縁化することが可能
で、耐サ−ジ特性並びに耐湿特性が優れた積層形電圧非
直線抵抗器の製造方法を得ることができる。According to the present invention, it is possible to insulate the outer surface of a varistor element laminated body surrounded by a sintered body except for a portion connected to an external extraction electrode of a plurality of internal electrodes. A method for manufacturing a laminated voltage non-linear resistor excellent in surge characteristics and moisture resistance can be obtained.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の実施例に係る積層形バリスタを示す断
面図である。FIG. 1 is a sectional view showing a laminated varistor according to an embodiment of the present invention.
【図２】本発明の実施例に係る生シ−トに内部電極を形
成した状態を示す斜視図である。FIG. 2 is a perspective view showing a state in which internal electrodes are formed on a raw sheet according to the embodiment of the present invention.
【図３】本発明の実施例に係る生シ−ト積層体を示す断
面図である。FIG. 3 is a cross-sectional view showing a raw sheet laminate according to an embodiment of the present invention.
【図４】本発明の実施例に係るバリスタ素子積層体を示
す断面図である。FIG. 4 is a sectional view showing a varistor element laminate according to an embodiment of the present invention.
【図５】従来例に係る積層形バリスタを示す断面図であ
る。FIG. 5 is a cross-sectional view showing a laminated varistor according to a conventional example.
【図６】従来例に係る積層形バリスタを示す断面図であ
る。FIG. 6 is a sectional view showing a laminated varistor according to a conventional example.
１ バリスタ組成物生シ−ト ２ 内部電極 ４ バリスタ組成物焼結体 ５ バリスタ素子積層体 ６ 絶縁化 ７ 外部電極 REFERENCE SIGNS LIST 1 varistor composition raw sheet 2 internal electrode 4 varistor composition sintered body 5 varistor element laminate 6 insulation 7 external electrode
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01C 7/02 - 7/22 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H01C 7/02-7/22
Claims (1)
したバリスタ組成物生シートを前記内部電極の端面が両
側面に交互に導出するように複数枚積層して焼結し、前
記内部電極の外部電極と接続する部分を除いてバリスタ
組成物焼結体で囲まれたバリスタ素子積層体を形成した
後、この積層体をＣｕ２Ｏ，Ｌｉ２Ｏ，Ａｇ２Ｏ又はＫ
２Ｏなどの一価の酸化物微粉末をＡｌ２Ｏ３又はＭｇＯ
の結晶粒子中に分散した粉体中で包囲して熱処理し、前
記素子積層体の外表面を絶縁化することを特徴とする積
層形電圧非直線抵抗器の製造方法。1. A varistor composition raw sheet mainly composed of zinc oxide having an internal electrode formed thereon is laminated and sintered so that end faces of the internal electrode are alternately led out to both side faces, and sintered. After forming a varistor element laminate surrounded by a varistor composition sintered body except for a portion connected to an external electrode of the above, the laminate is cut into Cu 2 O, Li 2 O, Ag 2 O or K
A monovalent oxide fine powder such as 2 O is mixed with Al 2 O 3 or MgO
A method for manufacturing a laminated voltage non-linear resistor, comprising: surrounding and heat-treating a powder dispersed in crystal particles of (1) to insulate the outer surface of the element laminate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3311713A JP2983096B2 (en) | 1991-10-29 | 1991-10-29 | Manufacturing method of laminated voltage non-linear resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3311713A JP2983096B2 (en) | 1991-10-29 | 1991-10-29 | Manufacturing method of laminated voltage non-linear resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05121211A JPH05121211A (en) | 1993-05-18 |
| JP2983096B2 true JP2983096B2 (en) | 1999-11-29 |
Family
ID=18020577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3311713A Expired - Fee Related JP2983096B2 (en) | 1991-10-29 | 1991-10-29 | Manufacturing method of laminated voltage non-linear resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2983096B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100255906B1 (en) * | 1994-10-19 | 2000-05-01 | 모리시타 요이찌 | Electronic component and method for fabricating the same |
| JP4506066B2 (en) * | 2002-06-11 | 2010-07-21 | 株式会社村田製作所 | Chip-type electronic component and method for manufacturing chip-type electronic component |
| JP4933968B2 (en) * | 2007-07-04 | 2012-05-16 | Ｔｄｋ株式会社 | Ceramic electronic components |
| JP5799672B2 (en) * | 2011-08-29 | 2015-10-28 | Tdk株式会社 | Chip varistor |
| JP5696623B2 (en) * | 2011-08-29 | 2015-04-08 | Tdk株式会社 | Chip varistor |
-
1991
- 1991-10-29 JP JP3311713A patent/JP2983096B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05121211A (en) | 1993-05-18 |
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