JP2981777B2 - Semiconductor substrate manufacturing method - Google Patents
Semiconductor substrate manufacturing methodInfo
- Publication number
- JP2981777B2 JP2981777B2 JP2413846A JP41384690A JP2981777B2 JP 2981777 B2 JP2981777 B2 JP 2981777B2 JP 2413846 A JP2413846 A JP 2413846A JP 41384690 A JP41384690 A JP 41384690A JP 2981777 B2 JP2981777 B2 JP 2981777B2
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial growth
- phase epitaxial
- insulating film
- film
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は単結晶シリコン（Si) 基
台上に絶縁膜を隔てて単結晶シリコン膜を形成する、所
謂SOI(Silicon On Insulator) 技術による半導体基板の
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor substrate by a so-called SOI (Silicon On Insulator) technique for forming a single crystal silicon film on a single crystal silicon (Si) base with an insulating film interposed therebetween.
【０００２】[0002]
【従来の技術】SOI 技術は絶縁膜による素子間分離が容
易で三次元素子への応用が可能であること、CMOSにおけ
るラッチ・アップがないこと、高集積化が容易であるこ
と、接合容量, 配線容量を低減出来て、低消費電力で高
速動作が期待出来る等の優れた特性を備えており、従来
より種々の技術が提案されている。このようなSOI 技術
の一つとして単結晶シリコン基台の一部と接触した状態
で、絶縁膜上に非晶質又は多結晶膜を形成した後、アニ
ール処理によって単結晶シリコン基台の表面をシードと
して前記非晶質、又は多結晶膜を単結晶化して単結晶シ
リコン膜を形成する技術が知られている。2. Description of the Related Art SOI technology is easy to separate elements by an insulating film and can be applied to three-dimensional elements, there is no latch-up in CMOS, high integration is easy, junction capacitance, It has excellent characteristics such as a reduction in wiring capacity, high power consumption and low power consumption, and various techniques have been proposed. As one of such SOI technologies, an amorphous or polycrystalline film is formed on an insulating film while being in contact with a part of the single crystal silicon base, and then the surface of the single crystal silicon base is subjected to annealing treatment. A technique for forming a single crystal silicon film by monocrystallizing the amorphous or polycrystalline film as a seed is known.
【０００３】図３は従来のSIO 技術による半導体基板の
製造過程を示す主要工程図である。先ず図３(a) に示す
如く単結晶シリコン基台１の表面に熱酸化法、或いはCV
D 法等によりSiＯ2 からなる絶縁膜２を形成した後、フ
ォトリソグラフィ技術によって絶縁膜２の一部に単結晶
シリコン基台１の表面が露出する窓孔2aを形成する (図
３(b))。次にこの絶縁膜２の表面、及び窓孔2a内に露出
している単結晶シリコン基台１の表面にわたって非晶質
シリコン膜３を堆積した後（図３(c))、600 ℃程度でア
ニール処理を行い、窓孔2a内に露出している単結晶シリ
コン基台１の表面をシードとして、先ず窓孔2a内で縦方
向固相エピタキシャル成長を行い、引き続いて窓孔2a上
から絶縁膜２上に向けて横方向固相エピタキシャル成長
を行って非晶質シリコン膜３を単結晶化して図３(d) に
示す如き固相エピタキシャル成長層４を形成し、半導体
基板を得る。FIG. 3 is a main process diagram showing a manufacturing process of a semiconductor substrate by the conventional SIO technology. First, as shown in FIG. 3A, the surface of the single crystal silicon base 1 is thermally oxidized or CV
After the insulating film 2 made of SiO 2 is formed by the D method or the like, a window hole 2a through which the surface of the single crystal silicon base 1 is exposed is formed in a part of the insulating film 2 by a photolithography technique (FIG. 3B). ). Next, after depositing an amorphous silicon film 3 over the surface of the insulating film 2 and the surface of the single crystal silicon base 1 exposed in the window 2a (FIG. 3 (c)), Annealing is performed, and using the surface of the single-crystal silicon base 1 exposed in the window 2a as a seed, vertical solid-phase epitaxial growth is first performed in the window 2a, and then the insulating film 2 is formed on the window 2a. A solid phase epitaxial growth layer 4 as shown in FIG. 3D is formed by monocrystallizing the amorphous silicon film 3 by performing lateral solid phase epitaxial growth upward to obtain a semiconductor substrate.
【０００４】[0004]
【発明が解決しようとする課題】ところでこのような従
来方法によって製造された半導体基板における固相エピ
タキシャル成長層４の結晶性が悪く、所望の特性を持つ
半導体素子を得難いという問題があった。図４は単結晶
シリコン基台１、SiＯ2 からなる絶縁膜２、固相エピタ
キシャル成長層４の境界部分を窓孔2aの中心から片側に
ついて示す透過型電子顕微鏡(TEM) 写真（１万倍）を示
す図である（参考写真２参照）。この図４から明らかな
如く、横方向固相エピタキシャル成長させた絶縁膜２上
の固相エピタキシャル成長層４の結晶性は窓孔2a位置か
ら遠く離れるに従って結晶性が悪化していることが解
る。ただ、固相エピタキシャル成長層４と絶縁膜２との
境界部分は、良好な結晶性が得られている。図５は固相
エピタキシャル成長層４と絶縁膜２との境界部分を示す
透過型電子顕微鏡写真（300 万倍) を示す図（参考写真
３参照）であり、これから明らかな如く、固相エピタキ
シャル成長層４と絶縁膜２との境界近傍においては固相
エピタキシャル成長層４の結晶性は良好であることが解
る。本発明はかかる事情に鑑みなされたものであって、
その目的とするところは絶縁膜上に横方向固相エピタキ
シャル成長により形成する単結晶半導体膜の結晶性を改
善し、電気的特性の良好な半導体基板を製造する方法を
提供するにある。However, there is a problem that the crystallinity of the solid phase epitaxial growth layer 4 in the semiconductor substrate manufactured by such a conventional method is poor, and it is difficult to obtain a semiconductor element having desired characteristics. FIG. 4 is a transmission electron microscope (TEM) photograph (magnification: 10,000 times) showing a boundary portion between the single crystal silicon base 1, the insulating film 2 made of SiO 2 and the solid phase epitaxial growth layer 4 on one side from the center of the window 2a. It is a figure shown (refer reference photograph 2). As is clear from FIG. 4, the crystallinity of the solid-phase epitaxial growth layer 4 on the insulating film 2 grown by the lateral solid-phase epitaxial growth deteriorates with increasing distance from the position of the window 2a. However, good crystallinity is obtained at the boundary between the solid-phase epitaxial growth layer 4 and the insulating film 2. FIG. 5 is a transmission electron micrograph (3 million times) showing a boundary portion between the solid-phase epitaxial growth layer 4 and the insulating film 2 (see Reference Photo 3). It can be seen that the crystallinity of the solid phase epitaxial growth layer 4 is good near the boundary between the semiconductor layer and the insulating film 2. The present invention has been made in view of such circumstances,
It is an object of the present invention to provide a method for improving the crystallinity of a single crystal semiconductor film formed by lateral solid phase epitaxial growth on an insulating film and manufacturing a semiconductor substrate having good electric characteristics.
【０００５】[0005]
【課題を解決するための手段】本発明に係る半導体基板
の製造方法は、単結晶半導体基台の表面に絶縁膜を形成
する工程と、絶縁膜の一部を除去して単結晶半導体基台
の表面を露出させる工程と、前記絶縁膜及び露出した単
結晶半導体基台表面に非晶質半導体膜を形成する工程
と、この非晶質半導体膜をアニール処理して固相エピタ
キシャル成長層とする工程とを含む半導体基板の製造方
法において、前記固相エピタキシャル成長層を、これと
絶縁膜との境界近傍を除いてセルフインプランテーショ
ンにより非晶質化させる工程と、非晶質化した半導体膜
をアニール処理し、前記絶縁膜との境界に残した固相エ
ピタキシャル成長層をシードとして縦方向固相エピタキ
シャル成長させて単結晶半導体膜を形成する工程とを含
むことを特徴とする。According to the present invention, there is provided a method of manufacturing a semiconductor substrate, comprising the steps of: forming an insulating film on a surface of a single crystal semiconductor base; Exposing the surface, forming an amorphous semiconductor film on the insulating film and the exposed surface of the single crystal semiconductor base, and annealing the amorphous semiconductor film to form a solid phase epitaxial growth layer A step of amorphizing the solid-phase epitaxial growth layer by self-implantation except for near a boundary between the solid-phase epitaxial growth layer and the insulating film; and annealing the amorphized semiconductor film. Forming a single-crystal semiconductor film by longitudinal solid-phase epitaxial growth using the solid-phase epitaxial growth layer left at the boundary with the insulating film as a seed.
【０００６】[0006]
【作用】本発明方法にあっては固相エピタキシャル成長
により形成した固相エピタキシャル成長層に対して絶縁
膜との境界近傍の良好な結晶領域を除く領域にセルフイ
ンプランテーションを施してこの領域を非晶質化し、再
度のアニール処理にて残された結晶性の良好な領域の固
相エピタキシャル成長層をシードとして、縦方向固相エ
ピタキシャル成長を行わせて、結晶性を改善することが
可能となる。According to the method of the present invention, self-implantation is performed on a region excluding a good crystal region near a boundary with an insulating film with respect to a solid-phase epitaxial growth layer formed by solid-phase epitaxial growth to make this region amorphous. It is possible to improve the crystallinity by performing vertical solid-phase epitaxial growth using the solid-phase epitaxial growth layer in the region having good crystallinity remaining by the second annealing as a seed.
【０００７】[0007]
【実施例】以下本発明をその実施例を示す図面に基づい
て具体的に説明する。図１は本発明方法の主要製造工程
を示す模式的断面図であり、図中１は単結晶シリコン(S
i)基台、２はSiＯ2 膜等の絶縁膜を示している。先ず図
１(a) に示す如く単結晶シリコン基台１上にCVD 法、或
いは熱酸化法によりSiＯ2 膜からなる絶縁膜２を形成
し、次にフォトリソグラフィ技術等を利用して絶縁膜２
に、前記単結晶シリコン基台１の表面が露出する窓孔2a
を形成する（図１(b))。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a schematic sectional view showing main manufacturing steps of the method of the present invention.
i) Base 2, reference numeral 2 denotes an insulating film such as a SiO 2 film. First, as shown in FIG. 1A, an insulating film 2 made of a SiO 2 film is formed on a single crystal silicon base 1 by a CVD method or a thermal oxidation method, and then the insulating film 2 is formed by using a photolithography technique or the like.
A window 2a through which the surface of the single crystal silicon base 1 is exposed.
Is formed (FIG. 1 (b)).
【０００８】次にこの絶縁膜２の表面及び前記窓孔2a内
に露出する単結晶シリコン基台１の表面に、基板温度55
0 ℃でSi2 Ｈ6 ガスを用いて非晶質シリコン膜３を堆積
させる（図１(c))。この状態で600 ℃のＮ2 ガス雰囲気
中でアニール処理を行い、窓孔2aに露出する単結晶シリ
コン基台１の単結晶シリコンをシードとして非晶質シリ
コン膜３を縦方向固相エピタキシャル成長させ、次いで
横方向固相エピタキシャル成長させて固相エピタキシャ
ル成長相４を形成する（図１(d))。Next, the surface of the insulating film 2 and the surface of the single-crystal silicon base 1 exposed in the window 2a are exposed to a substrate temperature of 55 ° C.
At 0 ° C., an amorphous silicon film 3 is deposited using Si 2 H 6 gas (FIG. 1C). In this state, annealing is performed in an N 2 gas atmosphere at 600 ° C., and the amorphous silicon film 3 is vertically solid-phase epitaxially grown using the single crystal silicon of the single crystal silicon base 1 exposed in the window 2a as a seed. Next, solid phase epitaxial growth phase 4 is formed by lateral solid phase epitaxial growth (FIG. 1 (d)).
【０００９】成長させた固相エピタキシャル成長層４は
前述した如く結晶性が不良であるが、絶縁膜２及び窓孔
2a内に露出する単結晶シリコン基台１との境界近傍では
良好な単結晶化がまされている。Although the grown solid phase epitaxial growth layer 4 has poor crystallinity as described above, the insulating film 2 and the window hole
Good single crystallization is performed near the boundary with the single crystal silicon base 1 exposed in 2a.
【００１０】そこで固相エピタキシャル成長層４に、こ
れと単結晶シリコン基台1,絶縁膜２との境界近傍を除い
て表面側からシリコンイオンを打ち込む、所謂セルフイ
ンプランテーションを施す（図１(e))。これによって図
１(e) に示す如く境界近傍には固相エピタキシャル成長
領域4aが残り、他の部分が再び非晶質化せしめられて非
晶質シリコン膜５となる。この非晶質シリコン膜５に再
びアニール処理を行って、固相エピタキシャル成長領域
4aの良好な結晶をシードとして縦方向固相エピタキシャ
ル成長させ、単結晶半導体膜たる固相エピタキシャル成
長層６を得る。Therefore, the solid phase epitaxial growth layer 4 is subjected to so-called self-implantation, in which silicon ions are implanted from the surface side except for the vicinity of the boundary between the single crystal silicon base 1 and the insulating film 2 (FIG. 1 (e)). ). As a result, as shown in FIG. 1 (e), a solid phase epitaxial growth region 4a remains near the boundary, and the other portion is made amorphous again to form the amorphous silicon film 5. The amorphous silicon film 5 is again subjected to an annealing treatment, so that a solid phase epitaxial growth region is formed.
The solid phase epitaxial growth layer 6 which is a single crystal semiconductor film is obtained by performing vertical solid phase epitaxial growth using the good crystal of 4a as a seed.
【００１１】図２は前述した如き本発明方法により製作
した半導体基板における単結晶シリコン基台１、絶縁膜
２及び固相エピタキシャル成長層６の境界近傍の電子顕
微鏡写真(100万倍) を示す図（参考写真１参照）であ
る。図２，図４の対比から明らかなように固相エピタキ
シャル成長層６の結晶性は固相エピタキシャル成長層４
の結晶性と比較して格段に向上していることが解る。な
お上述の実施例は単結晶シリコン基台１上に絶縁膜２を
隔ててシリコンの固相エピタキシャル成長層６を形成す
る場合について説明したが、これに限らずGaAs等他の各
種半導体材料についても適用し得ることは言うまでもな
い。FIG. 2 is an electron micrograph (magnification: 1,000,000) of the vicinity of the boundary between the single crystal silicon base 1, the insulating film 2, and the solid phase epitaxial growth layer 6 in the semiconductor substrate manufactured by the method of the present invention as described above (FIG. 2). Reference Photo 1). 2 and 4, the crystallinity of the solid-phase epitaxial growth layer 6 is
It can be seen that the crystallinity is remarkably improved as compared with the crystallinity. In the above-described embodiment, the case where the solid-phase epitaxial growth layer 6 of silicon is formed on the single-crystal silicon base 1 with the insulating film 2 interposed therebetween, but the present invention is not limited to this, and is applicable to other various semiconductor materials such as GaAs. It goes without saying that it can be done.
【００１２】[0012]
【発明の効果】以上の如く本発明方法にあっては固相エ
ピタキシャル成長層に対し、絶縁膜との境界近傍の領域
を除く領域にセルフインプランテーションを行って非晶
質化した後、再度アニール処理し、絶縁膜との境界近傍
の結晶性の良好な領域をシードとして縦方向固相エピタ
キシャル成長することにより良好な結晶性を有する単結
晶半導体膜が得られ半導体基板の特性が安定する等、本
発明は優れた効果を奏するものである。As described above, according to the method of the present invention, the solid phase epitaxial growth layer is made amorphous by performing self-implantation on a region other than the region near the boundary with the insulating film, and then annealed again. According to the present invention, a single crystal semiconductor film having good crystallinity can be obtained by performing vertical solid phase epitaxial growth using a region having good crystallinity near a boundary with an insulating film as a seed, and characteristics of a semiconductor substrate can be stabilized. Has an excellent effect.
【図１】本発明方法の主要製造工程を示す工程説明図で
ある。FIG. 1 is a process explanatory view showing main manufacturing steps of the method of the present invention.
【図２】本発明方法により製造した半導体基板の顕微鏡
写真を示す図である。FIG. 2 is a diagram showing a micrograph of a semiconductor substrate manufactured by the method of the present invention.
【図３】従来方法の主要製造工程を示す工程説明図であ
る。FIG. 3 is a process explanatory view showing main manufacturing steps of a conventional method.
【図４】従来方法により製造した半導体基板の顕微鏡写
真を示す図である。FIG. 4 is a view showing a microscope photograph of a semiconductor substrate manufactured by a conventional method.
【図５】固相エピタキシャル成長層と絶縁膜との境界近
傍の顕微鏡写真を示す図である。FIG. 5 is a view showing a micrograph of the vicinity of a boundary between a solid phase epitaxial growth layer and an insulating film.
１ 単結晶シリコン基台 ２ 絶縁膜 ３ 非晶質シリコン膜 ４ 固相エピタキシャル成長層 ５ 非晶質シリコン膜 ６ 固相エピタキシャル成長層 DESCRIPTION OF SYMBOLS 1 Single crystal silicon base 2 Insulating film 3 Amorphous silicon film 4 Solid phase epitaxial growth layer 5 Amorphous silicon film 6 Solid phase epitaxial growth layer
Claims (1)
する工程と、絶縁膜の一部を除去して単結晶半導体基台
の表面を露出させる工程と、前記絶縁膜及び露出した単
結晶半導体基台表面に非晶質半導体膜を形成する工程
と、この非晶質半導体膜をアニール処理して固相エピタ
キシャル成長層とする工程とを含む半導体基板の製造方
法において、前記固相エピタキシャル成長層を、これと
絶縁膜との境界近傍を除いてセルフインプランテーショ
ンにより非晶質化させる工程と、非晶質化した半導体膜
をアニール処理し、前記絶縁膜との境界に残した固相エ
ピタキシャル成長層をシードとして縦方向固相エピタキ
シャル成長させて単結晶半導体膜を形成する工程とを含
むことを特徴とする半導体基板の製造方法。A step of forming an insulating film on a surface of the single crystal semiconductor base; a step of exposing a surface of the single crystal semiconductor base by removing a part of the insulating film; A method of manufacturing a semiconductor substrate, comprising: a step of forming an amorphous semiconductor film on a surface of a crystalline semiconductor base; and a step of annealing the amorphous semiconductor film to form a solid phase epitaxial growth layer. Amorphizing by self-implantation except for the vicinity of the boundary between the film and the insulating film; and annealing the amorphous semiconductor film to leave a solid phase epitaxial growth layer remaining at the boundary with the insulating film. Forming a single-crystal semiconductor film by performing vertical solid-phase epitaxial growth using the substrate as a seed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2413846A JP2981777B2 (en) | 1990-12-19 | 1990-12-19 | Semiconductor substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2413846A JP2981777B2 (en) | 1990-12-19 | 1990-12-19 | Semiconductor substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04219922A JPH04219922A (en) | 1992-08-11 |
| JP2981777B2 true JP2981777B2 (en) | 1999-11-22 |
Family
ID=18522403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2413846A Expired - Fee Related JP2981777B2 (en) | 1990-12-19 | 1990-12-19 | Semiconductor substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2981777B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6750091B1 (en) | 1996-03-01 | 2004-06-15 | Micron Technology | Diode formation method |
-
1990
- 1990-12-19 JP JP2413846A patent/JP2981777B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04219922A (en) | 1992-08-11 |
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