JP2972486B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2972486B2
JP2972486B2 JP5138373A JP13837393A JP2972486B2 JP 2972486 B2 JP2972486 B2 JP 2972486B2 JP 5138373 A JP5138373 A JP 5138373A JP 13837393 A JP13837393 A JP 13837393A JP 2972486 B2 JP2972486 B2 JP 2972486B2
Authority
JP
Japan
Prior art keywords
chip
finger
shaped conductor
terminals
conductor member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5138373A
Other languages
Japanese (ja)
Other versions
JPH06349885A (en
Inventor
正彦 井桁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Original Assignee
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI AISHII MAIKON SHISUTEMU KK filed Critical NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority to JP5138373A priority Critical patent/JP2972486B2/en
Publication of JPH06349885A publication Critical patent/JPH06349885A/en
Application granted granted Critical
Publication of JP2972486B2 publication Critical patent/JP2972486B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は大容量半導体ダイナミッ
クＲＡＭ（ＤＲＡＭ）など高集積度半導体装置に関し、
特に半導体装置のパッケージ構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor device such as a large capacity semiconductor dynamic RAM (DRAM).
In particular, it relates to a package structure of a semiconductor device.

【０００２】[0002]

【従来の技術】半導体装置の高集積度化に伴ないチップ
面積も増大し、ＤＲＡＭを例にとると、１ＭビットＤＲ
ＡＭの段階ですでに幅５ｍｍ以上、長さ１０ｍｍ以上に
達している。微細化技術の改良によりチップ面積の増大
を抑える努力が払われているものの、メモリ容量が４Ｍ
ビットへ、４Ｍビットから１６Ｍビットへと増大するに
伴なってチップ面積の増大は避けられない。2. Description of the Related Art As the degree of integration of semiconductor devices increases, the chip area also increases.
At the stage of AM, the width has already reached 5 mm or more and the length has reached 10 mm or more. Efforts have been made to suppress an increase in chip area by improving miniaturization technology, but the memory capacity is 4M
As the number of bits increases from 4 Mbits to 16 Mbits, an increase in chip area is inevitable.

【０００３】チップ面積がそれ程大きくない中程度の集
積度の半導体装置、例えば、２５６ＫビットのＤＲＡＭ
程度の半導体装置では、チップ内部の回路と外部回路と
の間の信号授受のためのチップ表面上の複数のチップ端
子すなわちワイヤボンディングパッドは一般にチップの
外周部（一般にはチップの一対の長辺に沿った周縁部）
に沿って直線状に配置される。チップは、チップ載置部
およびそれをとり囲んで放射状に延びる指状導体部を金
属薄板のプレス加工により予め形成したリードフレーム
の前記載置部にバックボンドされ、前記チップ端子と前
記指状導体部の内側端部とが金細線によりワイヤボンデ
ィング工程を経てそれぞれ接続される。チップ載置部お
よび指状導体部をセラミック基板上のメタライズ層で形
成したセラミック基板パッケージにおいても、上記チッ
プと指状導体部と金細線との位置関係は同様である。A semiconductor device of a medium degree of integration having a not so large chip area, for example, a DRAM of 256 Kbits
In some semiconductor devices, a plurality of chip terminals, ie, wire bonding pads, on the chip surface for signal transmission / reception between a circuit inside the chip and an external circuit are generally connected to an outer peripheral portion of the chip (generally, a pair of long sides of the chip). Along the periphery)
Are arranged in a straight line. The chip is back-bonded to a chip mounting portion and a finger-shaped conductor portion radially extending around the chip mounting portion by pressing a thin metal plate to a mounting portion of the lead frame, and the chip terminal and the finger-shaped conductor are formed. The inside ends of the portions are connected by a gold wire through a wire bonding process. In a ceramic substrate package in which the chip mounting portion and the finger-shaped conductor are formed of a metallized layer on the ceramic substrate, the positional relationship between the chip, the finger-shaped conductor and the gold wire is the same.

【０００４】上述のような構成の半導体装置におけるパ
ッケージでは、指状導体部の各々のチップ側端部すなわ
ち内側端部は上記チップ載置部よりも外側に位置してい
る。したがってパッケージ寸法をそれだけ増大させる。
しかも、指状導体部の金細線ボンディングを受ける上記
内側端部は樹脂材料による気密モールド工程のあと指状
導体部の付け根を構成し、この指状導体部への応力に耐
える必要があるので、チップと同一平面内で外側に向っ
てある程度の幅の応力吸収マージンを要し、このマージ
ンも半導体装置のパッケージの小型化を妨げる。チップ
面積の小さい半導体装置ではこれらに起因するパッケー
ジ寸法の増大はそれほど著しくはないが、高集積化に伴
う端子数の増大およびチップ面積の増大はこのパッケー
ジ寸法を著しく増大させ、半導体装置の小型化の阻害要
因となる。In the package of the semiconductor device having the above-described configuration, each chip-side end of the finger-shaped conductor portion, that is, the inside end is located outside the chip mounting portion. Therefore, the package size is increased accordingly.
Moreover, the above-mentioned inner end portion of the finger-shaped conductor portion which receives the gold wire bonding forms a root of the finger-shaped conductor portion after the hermetic molding step with a resin material, and it is necessary to withstand stress to this finger-shaped conductor portion. A stress absorption margin of a certain width is required toward the outside in the same plane as the chip, and this margin also hinders miniaturization of the semiconductor device package. In a semiconductor device having a small chip area, the increase in the package size due to these is not so significant. However, the increase in the number of terminals and the increase in the chip area due to the high integration greatly increase the package size, and the size of the semiconductor device is reduced. It becomes a hindrance factor.

【０００５】この問題を解決するために米国ＩＢＭ社は
１ＭビットＤＲＡＭについて「エリア・ワイヤ・ボン
ド」と称するＩＣパッケージ（Ａ−ワイヤパッケージ）
構造を１９８８年に開発し発表した（詳細については、
Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆｔｈｅ ３８ｔｈ Ｅｌ
ｅｃｔｒｏｎｉｃ Ｃｏｍｐｏｎｅｎｔ Ｃｏｎｆｅｒ
ｅｎｃｅ，ＸＩＩＩ一４，Ｍａｙ，１９８８．ｐｐ．５
５２−５５７所載のＷｉｌｌｉａｍ Ｃ．Ｗａｒｄ著の
論文“Ｖｏｌｕｍｅ ＰｒｏｄｕｃｔｉｏｎｏｆＵｎｉ
ｑｕｅ Ｐｌａｓｔｉｃ Ｓｕｒｆａｃｅ ｍｏｕｎｔ
Ｍｏｄｕｌｅｓｆｏｒ ｔｈｅ ＩＢＭ ８０−ｎｓ
１−Ｍｂｉｔ ＤＲＡＭ Ｃｈｉｐｂｙ Ａｒｅａ
Ｗｉｒｅ Ｂｏｕｄ Ｔｅｃｈｎｉｑｕｅｓ”参照）。In order to solve this problem, IBM Corporation of the United States has proposed an IC package (A-wire package) called "area wire bond" for a 1 Mbit DRAM.
The structure was developed and announced in 1988 (for details,
Proceedings of the 38th El
electronic Component Confer
ence, XIII-14, May, 1988. pp. 5
See William C. 52-557. Ward's paper "Volume Production of Uni"
que Plastic Surface mount
Modulesfor the IBM 80-ns
1-Mbit DRAM Chipby Area
Wire Bound Technologies ").

【０００６】このＡーワイヤパッケージ（Ａーｗｉｒｅ
ｐａｃｋａｇｅ）はメモリチップ上のチップ端子をチ
ップ長辺沿いの周縁部に配列する代わりに長辺方向チッ
プ中央部と短辺沿いの周縁部のみに配置したことと、こ
のチップ端子配列に対応してリードフレームの上記チッ
プ載置部を除去するとともに上記複数の指状導体部をそ
れら導体部の内側先端部がチップの方形の平面の周縁よ
りも内側に位置するようにチップ表面上に絶縁膜を介し
て配置したこととを特徴とする構成を備える。このＡ−
ワイヤパッケージにおいてはチップ端子と指状導体部の
内側端部との金細線による接続がチップと平行でチップ
そのものより小さい面積の平面内で形成されるので、完
成後のパッケージの寸法は方形のチップとほぼ同等に抑
えられ、チップ周縁部からの指状導体部の付け根のはみ
出し、すなわち上記ワイヤボンディング受け用の内側端
部および応力吸収マージンなどによるはみ出しは伴わな
い。また、チップ端子と指状導体部の内側端部との接続
は方形のチップの表面を覆うポリイミド膜などの絶縁膜
の表面に固定された形で形成されるので指状導体部の外
側端部からの応力の吸収も容易に達成できる。さらにチ
ップ端子と指状導体部の内側端部との距離を短縮できる
ので両者間をそれぞれ接続する金細線の所要量を節減で
きる。The A-wire package (A-wire)
package) is that the chip terminals on the memory chip are arranged only on the peripheral portion along the long side chip center and the short side along the chip instead of being arranged on the peripheral portion along the long side of the chip. The chip mounting portion of the lead frame is removed, and the plurality of finger-shaped conductor portions are coated with an insulating film on the chip surface such that the inner ends of the conductor portions are located inside the periphery of the rectangular plane of the chip. And a configuration characterized in that they are arranged through the intermediary. This A-
In a wire package, the connection between the chip terminals and the inner ends of the finger-shaped conductors by a fine gold wire is formed in a plane parallel to the chip and smaller in area than the chip itself. The protrusion of the root of the finger-shaped conductor portion from the peripheral edge of the chip, that is, the protrusion due to the inner end portion for receiving the wire bonding and the stress absorption margin is not involved. In addition, since the connection between the chip terminal and the inner end of the finger-shaped conductor is formed by being fixed to the surface of an insulating film such as a polyimide film covering the surface of the rectangular chip, the outer end of the finger-shaped conductor is connected. Absorption of stress from the material can be easily achieved. Further, the distance between the chip terminal and the inner end of the finger-shaped conductor can be reduced, so that the required amount of the fine gold wire connecting the two can be reduced.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、上述し
たＡーワイヤパッケージの半導体装置では、リードフレ
ームの指状導体部の上記内側端部のさらに内側にあって
上記チップ上の長辺方向中央部のチップ端子配列の対応
位置に形成された一対のバスバー（ｂｕｓｂａｒ）を備
え、これらバスバーと所定のチップ端子との間の細金線
による接続を通じて電源電圧および接地電位を供給して
いる。したがって、電源電圧源でもなく接地電位源でも
ないアドレス信号源などに接続されるチップ端子と指状
導体部の内側端部との間の細金線による接続は上記バス
バーを跨ぐように形成しなければならない。このバスバ
ーを跨ぐために高いフープ状で引き回される金細線はパ
ッケージ形成のためのモールド工程における樹脂材料の
圧入の段階で変形を生じバスバーと短絡する等の問題を
内包する。また、この金細線はバスバーを跨ぐフープ状
の高さの部分だけパッケージの厚みを増大させる。However, in the above-described semiconductor device of the A-wire package, the semiconductor device is located further inside the inner end of the finger-shaped conductor portion of the lead frame and at the center of the chip in the long side direction. A pair of busbars (busbars) formed at corresponding positions of the chip terminal arrangement are provided, and a power supply voltage and a ground potential are supplied through connection between these busbars and predetermined chip terminals by thin gold wires. Therefore, the connection by the thin gold wire between the chip terminal connected to the address signal source which is neither the power supply voltage source nor the ground potential source and the inner end of the finger-like conductor portion must be formed so as to straddle the bus bar. Must. The gold wire drawn in a high hoop shape so as to straddle the bus bar has a problem that it is deformed at the stage of press-fitting the resin material in a molding process for forming a package and short-circuits with the bus bar. In addition, the gold wire increases the thickness of the package only at a portion having a hoop-like height straddling the bus bar.

【０００８】したがって、この発明の目的は、上述の金
細線・バスバー間短絡を避け半導体装置のパッケージを
さらに薄くするようにチップ端子と指状導体部の内側端
部との間の金細線による接続を単純化した構造をもつ半
導体装置を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a connection between a chip terminal and an inner end of a finger-like conductor portion by a gold wire so as to avoid the above-mentioned short circuit between the gold wire and the bus bar and to make the package of the semiconductor device thinner. To provide a semiconductor device having a simplified structure.

【０００９】[0009]

【課題を解決するための手段】 本発明の半導体装置
は、主表面からの不純物拡散により形成された多数の回
路素子とこれら回路素子と外部回路との間の信号の授受
および動作電圧供給のための接続手段を構成する複数の
チップ端子とを備える長方形の半導体チップと、少なく
ともチップ端子の部分を除き半導体チップの主表面を覆
って形成された絶縁物被膜と、この被膜の上に配置され
半導体チップの長方形の一対の長辺の間の領域から外側
に向って延びる複数の指状導体部材と、チップ端子と指
状導体部材の内側端部とをそれぞれ接続する金属細線
と、指状導体部材および金属細線をそれら指状導体部材
の外側端部を除き外部から覆う樹脂膜とを含む半導体装
置において、チップ端子が半導体チップの一対の長辺の
一方に沿って第1の直線上に配置され、複数の指状導体
部材のうち一対の長辺の縁から複数のチップ端子までの
距離が遠い方側に形成されている指状導体部材の内側端
部が、チップ端子が配列された位置とチップ端子から遠
い方の縁との間であって第２の直線上に配置され、複数
の指状導体部材のうち一対の長辺の縁から複数のチップ
端子までの距離が短い方側に形成されている指状導体部
材の内側端部に鉤部を備え、鉤部を備える指状導体部材
が該チップ端子間を通過するように配置されて鉤部が第
2の直線上に配置され、金属細線は鉤部にて接続されて
いることを特徴とする。SUMMARY OF THE INVENTION A semiconductor device according to the present invention includes a plurality of circuit elements formed by diffusion of impurities from a main surface, for transmitting and receiving signals between these circuit elements and an external circuit, and for supplying an operating voltage. A rectangular semiconductor chip having a plurality of chip terminals constituting the connection means, an insulating film formed over the main surface of the semiconductor chip except for at least the chip terminals, and a semiconductor disposed on the film. a plurality of fingers conductor member from the region between the rectangle of the pair of long sides of the chip extending outwardly, and thin metal wires respectively connecting the inner ends of the chip terminal and the finger-like conductor member, the finger-shaped conductor In a semiconductor device including a member and a resin film that covers the thin metal wire from the outside except for the outer ends of the finger-shaped conductor members, a chip terminal is provided along a first straight line along one of a pair of long sides of the semiconductor chip. The inner ends of the finger-shaped conductor members formed on the far side where the distance from the edge of the pair of long sides to the plurality of chip terminals among the plurality of finger-shaped conductor members are arranged, and the chip terminals are arranged. Between the contact position and the edge farthest from the chip terminal and arranged on the second straight line, and the distance from the edge of the pair of long sides to the plurality of chip terminals of the plurality of finger-like conductor members is shorter. A hook portion is provided at the inner end of the finger-shaped conductor member formed on the side, and the finger-shaped conductor member provided with the hook portion is arranged so as to pass between the chip terminals, and the hook portion is the
2 are arranged on a straight line, and the thin metal wires are connected by hooks.

【００１０】[0010]

【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.

【００１１】図１は本発明の一実施例を示す半導体装置
の部分破断斜視図である。この半導体装置は、図１に示
すように、長方形の半導体チップ１０は長辺の一つに沿
って直線状に配列形成された複数個のチップ端子１１を
備える。これらチップ端子１１の配列部分を除きこのチ
ップ１０の主表面は絶縁シート１２で覆われ、そのシー
ト１２の表面に複数の指状導体部材１３，１３ａが一対
の長辺に垂直な方向に延びるように配置される。これら
指状導体部材１３，１３ａは実際にはリードフレームの
一部として形成されるが単純化して示してある。これら
指状導体部材１３，１３ａの各各の内側端部は上記絶縁
シート１２のチップ端子１１の配列に沿う端部に配置さ
れ、それら内側端部とチップ端子１１との間はワイヤボ
ンダーがなし得る最も低いフープ状態の金属細線１４で
ボンディングしそれぞれ接続される。指状導体部材１
３，１３ａの外部端部はこのＩＣパッケージをプリント
配線基板（図示していない）への表面実装に適応させる
ように設けた下向きおよび外向きの曲げ部を経て端子部
１５に達する。FIG. 1 is a partially cutaway perspective view of a semiconductor device showing one embodiment of the present invention. In this semiconductor device, as shown in FIG. 1, a rectangular semiconductor chip 10 includes a plurality of chip terminals 11 which are linearly arranged along one of the long sides. Except for the arrangement of the chip terminals 11, the main surface of the chip 10 is covered with an insulating sheet 12, and a plurality of finger-like conductor members 13, 13a extend on the surface of the sheet 12 in a direction perpendicular to a pair of long sides. Placed in These finger-shaped conductor members 13 and 13a are actually formed as a part of a lead frame, but are shown in a simplified manner. The inner end of each of the finger-shaped conductor members 13 and 13a is disposed at the end of the insulating sheet 12 along the arrangement of the chip terminals 11, and there is no wire bonder between the inner end and the chip terminal 11. Bonding and connection are made with the lowest obtained metal wire 14 in the hoop state. Finger-shaped conductor member 1
The outer ends of the terminals 3 and 13a reach the terminal 15 through downward and outward bending portions provided to adapt the IC package to surface mounting on a printed wiring board (not shown).

【００１２】上述の金属細線１４のボンディング工程の
のちこの組立体は樹脂材料層１６により気密封止されＩ
Ｃパッケージを形成する。なお、この気密封止に至るま
での工程では指状導体部材１３，１３ａは上述のリード
フレームの一部を形成するタイバー１７により一体化さ
れているが、この工程前にタイバー１７は除去されるの
で図１ではその位置を点線で示してある。After the above-described bonding process of the fine metal wires 14, this assembly is hermetically sealed with a resin material layer 16 and then sealed.
Form a C package. In the process up to the hermetic sealing, the finger-shaped conductor members 13 and 13a are integrated by the tie bar 17 forming a part of the above-described lead frame. However, the tie bar 17 is removed before this process. Therefore, the position is shown by a dotted line in FIG.

【００１３】図２は本発明の第２の実施例を示す半導体
装置の部分破断斜視図である。この半導体装置は、図２
に示すように、チップ端子の一部すなわちチップ端子１
１Ａをチップ１０の長辺の近傍でなく短辺の近傍に備え
る。これに対応して指状導体部材１３の一部すなわち部
材１３ｂの内側端部をそのチップ端子１１Ａの近傍に配
置する。図示を容易にするためにこの変形は１個のチッ
プ端子１１Ａを備える形で示しているが、チップ１０の
内部回路の集積度によるチップ端子１１の数が増大する
場合はそれらチップ端子の間隔を最適値に保つための複
数個のチップ端子１１Ａを設けることができる。導体部
材１３ｂの数も配置も端子１１Ａの数に応じて適当に変
更することができる。FIG. 2 is a partially broken perspective view of a semiconductor device according to a second embodiment of the present invention. This semiconductor device is shown in FIG.
As shown in FIG.
1A is provided not near the long side of the chip 10 but near the short side. Correspondingly, a part of the finger-shaped conductor member 13, that is, the inner end of the member 13b is arranged near the chip terminal 11A. For the sake of simplicity, this modification is shown with a single chip terminal 11A. However, if the number of chip terminals 11 increases due to the degree of integration of the internal circuit of the chip 10, the distance between the chip terminals may be increased. A plurality of chip terminals 11A can be provided to maintain the optimum value. The number and arrangement of the conductor members 13b can be appropriately changed according to the number of the terminals 11A.

【００１４】通常、アドレス信号源などに接続されるチ
ップ端子には隣接して保護回路が設けられているので、
この短辺に沿ってる配置されるチップ端子１１Ａを内部
回路の回路素子に電源電位を与える保護回路の不要なチ
ップ端子に望ましくは限定し、内部回路の回路素子と接
続する内部電源配線にコンタクトを介してチップ端子１
１Ａと接続する。このことにより内部回路に電源電位を
与える配線経路を短かくし電源電位の降下や接地電位の
浮き上りを少なくする。しかも保護回路が不要であるこ
とから、このチップ端子１１Ａの近傍にある内部回路領
域を狭くすることがない。特に内部回路領域を複数もつ
短辺の長いチップにこの変形例を適用するとその効果を
より得られる。Usually, a protection circuit is provided adjacent to a chip terminal connected to an address signal source or the like.
The chip terminals 11A arranged along this short side are desirably limited to chip terminals that do not require a protection circuit for applying a power supply potential to the circuit elements of the internal circuit, and contacts are made to the internal power supply wiring connected to the circuit elements of the internal circuit. Via the chip terminal 1
Connect to 1A. As a result, the wiring path for supplying the power supply potential to the internal circuit is shortened, and the drop of the power supply potential and the rise of the ground potential are reduced. Moreover, since no protection circuit is required, the internal circuit area near the chip terminal 11A is not reduced. In particular, if this modification is applied to a chip having a long short side having a plurality of internal circuit regions, the effect can be obtained more.

【００１５】以上説明した実施例では指状導体部材の内
側端部とチップ端子との金属細線で接続しているが、チ
ップ端子の間隔が広くとれる半導体装置では、チップ端
子にはんだバンプを形成し、指状導体部材の内側端部を
延し直接チップ端子と接続が可能である。In the embodiments described above, the inner ends of the finger-shaped conductor members and the chip terminals are connected by thin metal wires. However, in a semiconductor device in which the space between the chip terminals can be widened, solder bumps are formed on the chip terminals. The inner end of the finger-like conductor member can be extended to directly connect to the chip terminal.

【００１６】[0016]

【発明の効果】以上説明したように本発明は、チップ端
子をチップの一対の長辺の一方に沿って直線状に配置さ
せ、指状導体部材の内側端部を絶縁物被膜上のチップ端
子の配列の内側でその配列と隣接する位置に配置させる
ことによって、指状導体部材とチップ端子との間に従来
のようなチップ面から露出するバスバーが介在すること
がなく両者を接続する金属細線のなすフープを低くさせ
その長さを著しく短縮できる。したがって、この金属細
線がモールド工程などにおける樹脂材料の圧力により他
の導体と短絡したり断線を生じたりする懸念も解消され
る。また、この金属細線の短縮により半導体装置のパッ
ケージの厚さをより小さくするとともに指状導体部の内
側端部の付け根にかかる応力に対しても十分な強度を確
保できる。As described above, according to the present invention, the chip terminals are arranged linearly along one of the pair of long sides of the chip, and the inner ends of the finger-shaped conductor members are disposed on the insulating film. By arranging it at a position adjacent to the array inside the array, the metal thin wire connecting the finger-shaped conductor member and the chip terminal without interposing the bus bar exposed from the chip surface as in the related art. The length of the hoop can be reduced and the length can be significantly reduced. Therefore, the concern that the thin metal wire is short-circuited or disconnected with another conductor due to the pressure of the resin material in the molding step or the like is also solved. In addition, the shortening of the thin metal wires makes it possible to further reduce the thickness of the package of the semiconductor device and to secure sufficient strength against the stress applied to the root of the inner end of the finger-shaped conductor.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例を示す半導体装置の部分破断
斜視図である。FIG. 1 is a partially cutaway perspective view of a semiconductor device according to an embodiment of the present invention.

【図２】本発明の第２の実施例を示す半導体装置の部分
破断斜視図である。FIG. 2 is a partially cutaway perspective view of a semiconductor device according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０ 半導体チップ １１，１１ａ，１１ｂ，１１Ａ チップ端子 １２ 絶縁シート １３，１３ａ，１３ｂ 指状導体部材 １４ 金属細線 １５ 端子部 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11, 11a, 11b, 11A Chip terminal 12 Insulating sheet 13, 13a, 13b Finger-shaped conductor member 14 Fine metal wire 15 Terminal part

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 主表面からの不純物拡散により形成され
た多数の回路素子とこれら回路素子と外部回路との間の
信号の授受および動作電圧供給のための接続手段を構成
する複数のチップ端子とを備える長方形の半導体チップ
と、少なくとも前記チップ端子の部分を除き前記半導体
チップの前記主表面を覆って形成された絶縁物被膜と、
この被膜の上に配置され前記半導体チップの前記長方形
の一対の長辺の間の領域から外側に向って延びる複数の
指状導体部材と、前記チップ端子と前記指状導体部材の
内側端部とをそれぞれ接続する金属細線と、前記指状導
体部材および前記金属細線をそれら指状導体部材の外側
端部を除き外部から覆う樹脂膜とを含む半導体装置にお
いて、前記チップ端子が前記半導体チップの前記一対の
長辺の一方に沿って第1の直線上に配置され、前記複数
の指状導体部材のうち前記一対の長辺の縁から前記複数
のチップ端子までの距離が遠い方側に形成されている指
状導体部材の前記内側端部が、前記チップ端子が配列さ
れた位置と前記チップ端子から遠い方の縁との間であっ
て第２の直線上に配置され、前記複数の指状導体部材の
うち前記一対の長辺の縁から前記複数のチップ端子まで
の距離が短い方側に形成されている指状導体部材の前記
内側端部に鉤部を備え、前記鉤部を備える指状導体部材
が該チップ端子間を通過するように配置されて前記鉤部
が前記第2の直線上に配置され、前記金属細線は前記鉤
部にて接続されていることを特徴とする半導体装置。1. A plurality of circuit elements formed by impurity diffusion from a main surface, and a plurality of chip terminals constituting connection means for transmitting and receiving signals between these circuit elements and an external circuit and supplying an operating voltage. A rectangular semiconductor chip comprising: and an insulator coating formed over the main surface of the semiconductor chip except for at least the chip terminals.
A plurality of fingers conductor member extending outwardly and disposed on the film from the region between the long pair of long sides of the rectangular of the semiconductor chip, the chip terminals and the inner end of the finger-shaped conductor member And a resin film that covers the finger-shaped conductor member and the metal wire from outside except for the outer ends of the finger-shaped conductor members, wherein the chip terminals are formed of the semiconductor chip. disposed on the first straight line along one of the pair of long sides, said plurality
Of the pair of long sides of the finger-shaped conductor member
The inner end of the finger-shaped conductor member formed on the side farthest from the chip terminals is arranged with the chip terminals.
Between the contact point and the edge farthest from the chip terminal.
And the plurality of finger-shaped conductor members are arranged on a second straight line.
From the edge of the pair of long sides to the plurality of chip terminals
The distance of the finger-shaped conductor member formed on the shorter side
Finger-shaped conductor member provided with a hook at the inner end, and provided with the hook
Are arranged so as to pass between the chip terminals, and
Are arranged on the second straight line, and the thin metal wire is
A semiconductor device, wherein the semiconductor device is connected by a unit.
JP5138373A 1993-06-10 1993-06-10 Semiconductor device Expired - Fee Related JP2972486B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5138373A JP2972486B2 (en) 1993-06-10 1993-06-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5138373A JP2972486B2 (en) 1993-06-10 1993-06-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06349885A JPH06349885A (en) 1994-12-22
JP2972486B2 true JP2972486B2 (en) 1999-11-08

Family

ID=15220422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5138373A Expired - Fee Related JP2972486B2 (en) 1993-06-10 1993-06-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2972486B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050245062A1 (en) * 2004-04-29 2005-11-03 Jeff Kingsbury Single row bond pad arrangement

Also Published As

Publication number Publication date
JPH06349885A (en) 1994-12-22

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