JP2972463B2 - Synchronous signal supply device - Google Patents
Synchronous signal supply deviceInfo
- Publication number
- JP2972463B2 JP2972463B2 JP4285647A JP28564792A JP2972463B2 JP 2972463 B2 JP2972463 B2 JP 2972463B2 JP 4285647 A JP4285647 A JP 4285647A JP 28564792 A JP28564792 A JP 28564792A JP 2972463 B2 JP2972463 B2 JP 2972463B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- clocks
- standby
- clock
- outputting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は同期信号供給装置に関
し、特に同期クロックを現用系と予備系の冗長構成で通
信装置に供給する同期信号供給装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal supply device, and more particularly to a synchronous signal supply device for supplying a synchronous clock to a communication device in a redundant configuration of an active system and a standby system.
【０００２】[0002]
【従来の技術】図２は従来の同期信号供給装置の一例の
ブロック図である。冗長構成の現用（０）系と予備
（１）系の第１と第２の同期信号Ａ，ＢをそれぞれＮ
（Ｎは正の整数）倍周し第１と第２の分岐信号Ａ１，Ｂ
１として出力する受信部１１ａ，１１ｂ及び倍周部１２
ａ，１２ｂと、第１又は第２の分岐信号Ａ１又はＢ１を
選択出力する選択部１３ａ，１３ｂと、分岐信号Ａ１又
はＢ１に同期する第１と第２のクロックＣ１，Ｃ２をぞ
れぞれ発振し出力するＰＬＬ１４ａ，１４ｂと、第１と
第２のクロックＣ１，Ｃ２を１／４分周して現用系と予
備系の分配クロックＤ１，Ｄ２として出力する分周器１
６ａ，１６ｂとを有している。2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional synchronous signal supply device. The first and second synchronization signals A and B of the working (0) system and the spare (1) system in the redundant configuration are respectively N
(N is a positive integer) times the first and second branch signals A1 and B
Receivers 11a and 11b and doubler 12 output as 1
a and 12b, selectors 13a and 13b for selectively outputting the first or second branch signal A1 or B1, and first and second clocks C1 and C2 synchronized with the branch signal A1 or B1, respectively. PLLs 14a and 14b which oscillate and output, and a frequency divider 1 which divides the first and second clocks C1 and C2 by １ ／ and outputs the divided clocks as active and standby distributed clocks D1 and D2.
6a and 16b.
【０００３】このように、それぞれ冗長系を持ってお
り、片系が障害となっても、システムとしての動作を保
証する構成がとられていた。[0003] As described above, each system has a redundant system, and even if one system fails, the system is configured to guarantee the operation as a system.
【０００４】[0004]
【発明が解決しようとする課題】この従来の同期信号供
給装置において、冗長方式ではクロック分配のＰＬＬ及
び分周回路が０系と１系でそれぞれ独立に動作している
為、外部からの同期信号の冗長切り換えでは、分配クロ
ックの位相の不整合に起因して装置内に与えるクロック
に雑音やデューティ異常が正じ装置内を通る信号データ
にエラーが生じるという欠点がある。In this conventional synchronous signal supply device, in the redundant system, since the PLL for clock distribution and the frequency divider circuit operate independently in the 0 system and the 1 system, respectively, an external synchronous signal is supplied. In the redundant switching, there is a drawback that noise or abnormal duty is applied to a clock applied to the device due to a phase mismatch of a distributed clock, and an error occurs in signal data passing through the device.
【０００５】[0005]
【課題を解決するための手段】本発明の同期信号供給回
路は、現用系と予備系の第１と第２の同期信号をそれぞ
れＮ（Ｎ＝正の整数）倍周し第１と第２の分岐信号とし
て出力する手段と、前記同期信号の状態に応じて出力中
の同期信号を他系の前記第１又は第２の分岐信号に選択
出力する手段と、前記選択出力に同期する第１と第２の
クロックを発振し出力する手段と、前記第１と第２のク
ロック及び位相制御信号を入力するＡＮＤ回路の出力を
１／Ｎ分周し現用系と予備系の分配クロックとして出力
する手段と、予備側からの情報が入力されたとき予備系
の前記ＡＮＤ回路に入力の前記位相制御信号を停止し予
備系の分配クロックを現用系のクロックの位相に追従さ
せる手段とを有する。A synchronization signal supply circuit of the present invention multiplies the first and second synchronization signals of an active system and a standby system by N (N = positive integer) times the first and second synchronization signals, respectively. Means for outputting as a branch signal, and outputting in accordance with the state of the synchronization signal.
Is selected as the first or second branch signal of another system.
Output means, means for oscillating and outputting first and second clocks synchronized with the selected output, and output of an AND circuit for inputting the first and second clocks and a phase control signal by 1 / N. Means for outputting as a distributed clock for the active system and the standby system; and stopping the phase control signal input to the AND circuit of the standby system when information from the standby system is input.
The distribution clock of the auxiliary system follows the phase of the clock of the active system.
Means .
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例のブロック図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.
【０００７】本実施例は、現用（０）系と予備（１）系
の第１と第２の同期信号Ａ，ＢをそれぞれＮ倍周し第１
と第２の分岐信号Ａ１，Ｂ１として出力する受信部１
ａ，１ｂ及び倍周部２ａ，２ｂと、第１又は第２の分岐
信号Ａ１又はＢ１を選択出力する選択部３ａ，３ｂと、
分岐信号Ａ１又はＢ１に同期する第１と第２のクロック
Ｃ１，Ｃ２をそれぞれ発振し出力するＰＬＬ４ａ，４ｂ
と、第１と第２のクロックＣ１，Ｃ２及び位相制御信号
Ｐ１，Ｐ２を入力するＡＮＤ回路５ａ，５ｂの出力を１
／Ｎ分周し現用系と予備系の分配クロックＤ１，Ｄ２と
して出力する分周器６ａ，６ｂと、予備側からの情報が
入力されたとき予備系のＡＮＤ回路５ｂに入力の位相制
御信号Ｐ２を停止する位相比較器７とを有して構成され
る。In this embodiment, the first and second synchronization signals A and B of the working (0) system and the protection (1) system are each multiplied by N times to obtain the first synchronization signal.
And a receiving unit 1 for outputting as second branch signals A1 and B1
a, 1b and multiplying units 2a, 2b, and selecting units 3a, 3b for selectively outputting the first or second branch signal A1 or B1;
PLLs 4a and 4b that oscillate and output first and second clocks C1 and C2, respectively, synchronized with the branch signal A1 or B1
And the outputs of the AND circuits 5a and 5b receiving the first and second clocks C1 and C2 and the phase control signals P1 and P2 are set to 1
Frequency dividers 6a and 6b which divide the frequency by / N and output them as distributed clocks D1 and D2 for the working system and the standby system, and a phase control signal P2 input to the AND circuit 5b of the standby system when information from the standby side is input. And a phase comparator 7 for stopping the operation.
【０００８】図３は本実施例の動作を説明するためのタ
イミング図である。分配クロックＤ１とＤ２の位相が不
整合で予備側情報が入力されると、位相比較器７は位相
制御信号Ｐ２を出力する。ＡＮＤ回路５ｂは位相制御信
号Ｐ２が入力される毎にＰＬＬ４ｂからの第２のクロッ
クＣ２の出力を停止する。図４は本実施例の位相比較器
の詳細ブロック図である。分配クロックＤ１，Ｄ２が排
他的論理和回路ＥＸＯＲに入力され、その論理和出力は
遅延回路経由でオア回路ＯＲａ，ｂにそれぞれ入力さ
れ、予備側情報が直接に入力されているオア回路ＯＲｂ
の出力とＰＬＬ４ｂからのクロックＣ２とがフリップフ
ロップＦＦに入力される。FIG. 3 is a timing chart for explaining the operation of this embodiment. When the phases of the distribution clocks D1 and D2 are inconsistent and protection side information is input, the phase comparator 7 outputs a phase control signal P2. The AND circuit 5b stops outputting the second clock C2 from the PLL 4b every time the phase control signal P2 is input. FIG. 4 is a detailed block diagram of the phase comparator of the present embodiment. The distribution clocks D1 and D2 are input to an exclusive-OR circuit EXOR, and the output of the OR is input to OR circuits ORa and b via delay circuits, respectively, and an OR circuit ORb to which spare side information is directly input.
And the clock C2 from the PLL 4b are input to the flip-flop FF.
【０００９】このようにすると、分配クロックＤ２にお
いて１系列が予備系となっている場合、分配クロックＤ
１の０系と１系が位相比較器７に入力され、さらに予備
側情報の入力により予備側の分配クロックＤ２を動作側
に追従させる位相制御信号Ｐ２が生成される。この位相
制御信号Ｐ２がＰＬＬ４ｂから分周器６ｂに入力するク
ロックをＡＮＤ回路５ｂで遮断することにより、予備側
の分配クロックＤ２の位相が常に動作側に追従するので
切り換えた分配クロックに、ほとんどみだれは発生せ
ず、装置内を通る信号データにエラーは生じない。In this manner, when one system is the standby system in the distribution clock D2, the distribution clock D2
The 0-system and 1-system 1 are input to the phase comparator 7, and the input of the protection-side information generates a phase control signal P2 for causing the protection-side distribution clock D2 to follow the operation side. The phase control signal P2 cuts off the clock input from the PLL 4b to the frequency divider 6b by the AND circuit 5b, so that the phase of the spare-side distributed clock D2 always follows the operation side, so that the switched distributed clock is almost lost. Does not occur, and no error occurs in the signal data passing through the device.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、現用系と
予備系の第１と第２の同期信号をそれぞれＮ（Ｎ＝正の
整数）倍周し第１と第２の分岐信号として出力する手段
と、前記第１又は第２の分岐信号を選択出力する手段
と、前記選択出力に同期する第１と第２のクロックを発
振し出力する手段と、前記第１と第２のクロック及び移
送制御信号を入力するＡＮＤ回路の出力を１／Ｎ分周し
現用系と予備系の分配クロックとして出力する手段と、
予備側からの情報が入力されたとき予備系の前記ＡＮＤ
回路に入力の前記位相制御信号を停止する手段とを有す
ることにより、切り替えた分配クロックがみだれず、装
置内を通る信号データにエラーは生じないという効果を
有する。As described above, according to the present invention, the first and second synchronizing signals of the working system and the standby system are respectively multiplied by N (N = positive integer) to obtain first and second branch signals. Output means; means for selectively outputting the first or second branch signal; means for oscillating and outputting first and second clocks synchronized with the selected output; and the first and second clocks Means for dividing the output of the AND circuit for inputting the transfer control signal by 1 / N, and outputting the divided clock as the distributed clocks for the active system and the standby system;
When the information from the standby side is input, the AND of the standby system
Providing the circuit with means for stopping the input phase control signal has an effect that the switched distribution clock is not observed and no error occurs in the signal data passing through the device.
【図１】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
【図２】従来の同期信号供給装置の一例のブロック図で
ある。FIG. 2 is a block diagram of an example of a conventional synchronization signal supply device.
【図３】本実施例の動作説明のためのタイミング図であ
る。FIG. 3 is a timing chart for explaining the operation of the present embodiment.
【図４】本実施例の位相比較器の詳細ブロック図であ
る。FIG. 4 is a detailed block diagram of a phase comparator according to the present embodiment.
１ａ，１ｂ 受信部 ２ａ，２ｂ 倍周部 ３ａ，３ｂ 選択部 ４ａ，４ｂ 引込発振器（ＰＬＬ） ５ａ，５ｂ アンド回路 ６ａ，６ｂ 分周器 ７ 位相比較器 1a, 1b Receiving unit 2a, 2b Doubler unit 3a, 3b Selector unit 4a, 4b Drop-in oscillator (PLL) 5a, 5b AND circuit 6a, 6b Divider 7 Phase comparator
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H04L 7/00 H04L 1/22 Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H04L 7/00 H04L 1/22
Claims (1)
をそれぞれＮ（Ｎ＝正の整数）倍周し第１と第２の分岐
信号として出力する手段と、前記同期信号の状態に応じ
て出力中の同期信号を他系の前記第１又は第２の分岐信
号に選択出力する手段と、前記選択出力に同期する第１
と第２のクロックを発振し出力する手段と、前記第１と
第２のクロック及び位相制御信号を入力するＡＮＤ回路
の出力を１／Ｎ分周し現用系と予備系の分配クロックと
して出力する手段と、予備側からの情報が入力されたと
き予備系の前記ＡＮＤ回路に入力の前記位相制御信号を
停止し予備系の分配クロックを現用系のクロックの位相
に追従させる手段とを有することを特徴とする同期信号
供給装置。A means for multiplying the first and second synchronization signals of the working system and the protection system by N (N = positive integer), respectively, and outputting them as first and second branch signals; According to the state
To output the synchronization signal being output to the first or second branch signal of another system.
Means for selectively outputting the selected output, and a first means synchronized with the selected output.
Means for oscillating and outputting the first and second clocks, and the output of the AND circuit for inputting the first and second clocks and the phase control signal, which is divided by 1 / N and output as the distribution clocks for the active and standby systems. Means for transmitting the phase control signal input to the standby AND circuit when information from the standby side is input.
Stop and change the standby system distribution clock to the active system clock phase.
Synchronizing signal supply apparatus characterized by having a means to follow the.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4285647A JP2972463B2 (en) | 1992-10-23 | 1992-10-23 | Synchronous signal supply device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4285647A JP2972463B2 (en) | 1992-10-23 | 1992-10-23 | Synchronous signal supply device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06141027A JPH06141027A (en) | 1994-05-20 |
| JP2972463B2 true JP2972463B2 (en) | 1999-11-08 |
Family
ID=17694245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4285647A Expired - Lifetime JP2972463B2 (en) | 1992-10-23 | 1992-10-23 | Synchronous signal supply device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2972463B2 (en) |
-
1992
- 1992-10-23 JP JP4285647A patent/JP2972463B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06141027A (en) | 1994-05-20 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990803 |