JP2956234B2 - Semiconductor memory device and manufacturing method thereof - Google Patents
Semiconductor memory device and manufacturing method thereofInfo
- Publication number
- JP2956234B2 JP2956234B2 JP3035802A JP3580291A JP2956234B2 JP 2956234 B2 JP2956234 B2 JP 2956234B2 JP 3035802 A JP3035802 A JP 3035802A JP 3580291 A JP3580291 A JP 3580291A JP 2956234 B2 JP2956234 B2 JP 2956234B2
- Authority
- JP
- Japan
- Prior art keywords
- storage node
- film
- conductive layer
- forming
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体メモリ装置に係
り，特にDRAMの記憶素子であるセルキャパシタの構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a structure of a cell capacitor as a storage element of a DRAM.
【０００２】近年，DRAMの大容量化に伴い, １ビットの
記憶素子を構成するセルの面積は年々縮小しているが，
回路の安定動作のためにはセルキャパシタには或る限度
以上の静電容量を確保する必要がある。そのための方法
の一つとしてポリシリコン膜とポリシリコン膜の間に容
量を持たせるスタックトキャパシタセルが用いられてい
る。In recent years, as the capacity of DRAMs has increased, the area of cells constituting a 1-bit storage element has been decreasing year by year.
For a stable operation of the circuit, it is necessary to secure a certain level of capacitance or more in the cell capacitor. As one of the methods therefor, a stacked capacitor cell having a capacitance between polysilicon films is used.
【０００３】本発明は大容量化に対応し，基板表面の段
差を緩和して素子形成を容易にしたスタックトキャパシ
タとして利用できる。[0003] The present invention can be used as a stacked capacitor in which the formation of elements is facilitated by alleviating steps on the surface of a substrate, corresponding to an increase in capacity.
【０００４】[0004]
【従来の技術】図４ (A)〜(C) は従来例によるスタック
トキャパシタの断面図である。図４(A) は通常のスタッ
クトキャパシタを示す。2. Description of the Related Art FIGS. 4A to 4C are sectional views of a conventional stacked capacitor. FIG. 4A shows a conventional stacked capacitor.
【０００５】図において，１はｐ型シリコン(p-Si)基
板，２は分離絶縁膜で二酸化シリコン(SiO2)膜, ３はセ
ルFET のソースドレイン領域，４はセルFET のゲート絶
縁膜，５はセルFET のゲート，６は層間絶縁膜でSiO
2膜, ７はポリシリコン膜からなる記憶ノード，８はキ
ャパシタの誘電体膜，９はポリシリコン膜からなる対向
電極である。In the figure, 1 is a p-type silicon (p-Si) substrate, 2 is a silicon dioxide (SiO 2 ) film as an isolation insulating film, 3 is a source / drain region of a cell FET, 4 is a gate insulating film of a cell FET, 5 is a gate of the cell FET, 6 is an interlayer insulating film,
Reference numeral 2 denotes a storage node formed of a polysilicon film, reference numeral 8 denotes a dielectric film of a capacitor, and reference numeral 9 denotes a counter electrode formed of a polysilicon film.
【０００６】図４(B) は，容量増加のために記憶ノード
７を厚く形成した例である。この場合は，この場合も図
４(A) よりも記憶ノードのパターニングが困難となり
（Ａ部），さらに対向電極等上層膜の段差被覆が困難と
なる（Ａ部）。FIG. 4B shows an example in which the storage node 7 is formed thick to increase the capacitance. In this case, patterning of the storage node is also more difficult than in FIG. 4A (part A), and it is more difficult to cover a step on the upper layer film such as the counter electrode (part A).
【０００７】図４(C) は，２層のポリシリコン膜7A, 7B
を使用し，記憶ノード７の外周を厚く形成して容量を増
やした例で，この場合も図４(A) よりも記憶ノードのパ
ターニングが困難となり（Ａ部），さらに対向電極等上
層膜の段差被覆が困難となる（Ａ部およびＢ部）。FIG. 4C shows two polysilicon films 7A and 7B.
4A, the outer periphery of the storage node 7 is formed thick to increase the capacitance. In this case, too, the patterning of the storage node becomes more difficult than in FIG. Step coverage becomes difficult (parts A and B).
【０００８】[0008]
【発明が解決しようとする課題】スタックトキャパシタ
の容量を増加させるための従来例の構造では，記憶ノー
ドのパターニングが困難であり，また，段差が大きくな
り上層膜の段差被覆が悪化し，製造歩留が低下するとい
う問題が生じた。In the conventional structure for increasing the capacitance of the stacked capacitor, it is difficult to pattern the storage node, and the step is increased, and the step coverage of the upper layer film is deteriorated. There is a problem that the yield is reduced.
【０００９】本発明は記憶ノードのパターニングや上層
膜の段差被覆を悪化させないで，スタックトキャパシタ
の容量を増加させる構造を提供し，DRAMの製造歩留の向
上を目的とする。An object of the present invention is to provide a structure for increasing the capacitance of a stacked capacitor without deteriorating the patterning of a storage node and the step coverage of an upper layer film, and an object of the present invention is to improve the production yield of a DRAM.
【００１０】[0010]
【課題を解決するための手段】上記課題の解決は、基板
上に，導電膜からなる記憶ノードと対向電極とが誘電体
膜を介して積層されたセルキャパシタを有し，該記憶ノ
ードは，第１のエッチング端で規定された第１の記憶ノ
ード用導電層と，該第１の記憶ノード用導電層を覆い，
該第１のエッチング端よりも外方の第２のエッチング端
で規定された第２の記憶ノード用導電層とを有し，該記
憶ノードの中央部の厚さが周辺部より厚い半導体メモリ
装置と， 基板表面に形成されたメモリトランジスタの一
端にコンタクトホールを開口し，第１のポリシリコン層
を形成したのち，選択的にエッチングして該コンタクト
ホールの領域に第１のエッチング端で規定された第１の
記憶ノード用導電層を形成し，第２のポリシリコン層を
形成したのち選択的にエッチングして該第１の記憶用導
電層を覆い，該第１のエッチング端よりも外方の第２の
エッチング端で規定された第２の記憶ノード用導電層を
形成し，次いで，誘電体膜，対向電極を形成することに
よってキャパシタを形成する半導体メモリ装置の製造方
法とにより達成される。Solving the problems SUMMARY OF THE INVENTION may, on a substrate, the storage node formed of a conductive film and the counter electrode has a cell capacitor stacked via the dielectric film, the storage Bruno
The first memory node is defined by the first etched edge.
Covering the first conductive layer for the storage node and the first conductive layer for the storage node;
A second etched end outside the first etched end
In a defined a second storage node conductive layer, one memory transistor thickness of the center portion is formed in the thick semiconductor memory device, the substrate surface than the peripheral portion of the storage node
A contact hole is opened at an end, and a first polysilicon layer is formed.
And then selectively etching the contact
The first region defined by the first etched edge in the region of the hole
Forming a conductive layer for a storage node and forming a second polysilicon layer;
After being formed, it is selectively etched to form the first storage conductor.
A second layer outside the first etched edge
Forming a second storage node conductive layer defined by the etched end;
And then forming a dielectric film and a counter electrode.
Method of manufacturing semiconductor memory device forming capacitor
Achieved by law .
【００１１】[0011]
【作用】本発明によれば，２層のポリシリコン膜を用い
て，記憶ノードの中央部を厚く，周辺部を薄く形成して
いるので，記憶ノードのパターニング（パターンの抜
き）は従来の１層ポリシリコン膜を用いた場合と同程度
に容易となり，また，記憶ノードの段差が段階的に形成
されているため，記憶ノードの上部の層，例えばビット
線やワード線のパターニングも容易となる。According to the present invention, the central part of the storage node is made thicker and the peripheral part thereof is made thinner by using a two-layered polysilicon film. It is as easy as using a multi-layer polysilicon film, and since the steps of the storage node are formed stepwise, patterning of layers above the storage node, for example, bit lines and word lines, is also easy. .
【００１２】上記のように，本発明は，２層構造にして
キャパシタ面積を増加させ，かつセルのパターニングを
従来と同程度に容易にすることができる。As described above, according to the present invention, the capacitor area can be increased by using a two-layer structure, and the patterning of the cell can be made as easy as in the prior art.
【００１３】[0013]
【実施例】図１は本発明の一実施例によるスタックトキ
ャパシタの断面図である。図において，１はp-Si基板，
２は分離絶縁膜でSiO2膜, ３はセルFET のソースドレイ
ン領域，４はセルFET のゲート絶縁膜，５はセルFET の
ゲート，６は層間絶縁膜でSiO2膜, 7C, 7Dはポリシリコ
ン膜からなる記憶ノード，８はキャパシタの誘電体膜，
９はポリシリコン膜からなる対向電極である。1 is a sectional view of a stacked capacitor according to an embodiment of the present invention. In the figure, 1 is a p-Si substrate,
2 is an isolation insulating film, SiO 2 film, 3 is a source / drain region of the cell FET, 4 is a gate insulating film of the cell FET, 5 is a gate of the cell FET, 6 is an SiO 2 film as an interlayer insulating film, and 7C and 7D are poly-silicon. A storage node made of a silicon film, 8 a dielectric film of a capacitor,
Reference numeral 9 denotes a counter electrode made of a polysilicon film.
【００１４】ここで，7Cは第１のポリシリコン膜で記憶
ノードの中央部を構成し，7Dは第２のポリシリコン膜で
第１のポリシリコン膜7Cを覆って被着形成されている。
図のように，記憶ノードは周辺部で薄くなっているの
で，パターニングは従来の１層のものと同様に容易であ
り，記憶ノードの段差が段階的につくため上層膜の段差
被覆が良好となる（Ａ部）。Here, 7C is a first polysilicon film constituting the central portion of the storage node, and 7D is formed of a second polysilicon film covering the first polysilicon film 7C.
As shown in the figure, since the storage node is thinner at the periphery, patterning is as easy as that of the conventional single layer, and the step of the storage node is formed stepwise, so that the step coverage of the upper layer film is good. (Part A).
【００１５】図２ (A)〜(F) は実施例のスタックトキャ
パシタの製造工程の概略を説明する断面図である。図２
(A) において，１はp-Si基板，２は分離絶縁膜でSiO
2膜, ３はセルFET のソースドレイン領域，４はセルFET
のゲート絶縁膜，５はセルFET のゲート，６は層間絶
縁膜でSiO2膜である。FIGS. 2A to 2F are cross-sectional views schematically illustrating a manufacturing process of the stacked capacitor of the embodiment. FIG.
In (A), 1 is a p-Si substrate, 2 is an isolation insulating film and SiO
2 film, 3 is the source / drain region of the cell FET, 4 is the cell FET
Is a gate insulating film, 5 is the gate of the cell FET, and 6 is an interlayer insulating film, which is an SiO 2 film.
【００１６】セルキャパシタの製造工程は通常の工程に
よりセルFET が形成された状態より出発する。まず, 気
相成長(CVD) 法により, 基板上に層間絶縁膜として厚さ
1000ÅのSiO2膜６を成長し，ドライエッチング法によ
り，FET のドレイン領域３上にコンタクトホールを開口
する。The manufacturing process of the cell capacitor starts from a state where the cell FET is formed by a normal process. First, the thickness of the interlayer insulating film was formed on the substrate by vapor deposition (CVD).
A 1000Å SiO 2 film 6 is grown, and a contact hole is opened on the drain region 3 of the FET by dry etching.
【００１７】図２(B) において, CVD 法により，コンタ
クトホールを覆って基板上に厚さ2000Åの第１のポリシ
リコン膜7Cを成長する。図２(C) において，第１のポリ
シリコン膜7Cをパターニングし, 記憶ノードの中央部を
残す。In FIG. 2B, a first polysilicon film 7C having a thickness of 2000 .ANG. Is grown on the substrate so as to cover the contact holes by the CVD method. In FIG. 2C, the first polysilicon film 7C is patterned to leave the central part of the storage node.
【００１８】図２(D) において，CVD 法により，基板上
に厚さ1000Åの第２のポリシリコン膜7Dを成長する。図
２(E) において，第２のポリシリコン膜7Dをパターニン
グし, 記憶ノードを形成する。In FIG. 2D, a second polysilicon film 7D having a thickness of 1000 ° is grown on the substrate by the CVD method. In FIG. 2E, the second polysilicon film 7D is patterned to form a storage node.
【００１９】図２(F) において，CVD 法により，キャパ
シタの誘電体膜となる厚さ70ÅのSi3N4 膜８を成長し，
パターニングして記憶ノードの露出面を残す。つぎに，
キャパシタの対向電極として，CVD 法により基板上に厚
さ1500Åの第３のポリシリコン膜９を成長してキャパシ
タの形成を終わる。[0019] In FIG. 2 (F), by a CVD method, growing the Si 3 N 4 film 8 having a thickness of 70Å as the dielectric film of the capacitor,
Pattern to leave exposed surface of storage node. Next,
As a counter electrode of the capacitor, a third polysilicon film 9 having a thickness of 1500 法 is grown on the substrate by the CVD method, thereby completing the formation of the capacitor.
【００２０】図３はDRAMセルの回路図である。図は実施
例の構造図に対応する回路図である。対応する箇所に構
造図と同じ符号を記入した。FIG. 3 is a circuit diagram of the DRAM cell. The figure is a circuit diagram corresponding to the structural diagram of the embodiment. Corresponding parts are indicated by the same reference numerals as in the structural drawing.
【００２１】[0021]
【発明の効果】記憶ノードのパターニングや上層膜の段
差被覆を悪化させないで，スタックトキャパシタの容量
を増加させることができた。As described above, the capacity of the stacked capacitor can be increased without deteriorating the patterning of the storage node and the step coverage of the upper layer film.
【００２２】この結果, 記憶保持の確実性が増し，DRAM
の製造歩留が向上した。As a result, the reliability of memory retention is increased,
The production yield has improved.
【図１】 本発明の一実施例によるスタックトキャパシ
タの断面図FIG. 1 is a sectional view of a stacked capacitor according to an embodiment of the present invention.
【図２】 本発明の実施例のスタックトキャパシタの製
造工程の概略を説明する断面図FIG. 2 is a sectional view schematically illustrating a manufacturing process of the stacked capacitor according to the embodiment of the present invention.
【図３】 DRAMセルの回路図FIG. 3 is a circuit diagram of a DRAM cell.
【図４】 従来例によるスタックトキャパシタの断面図FIG. 4 is a cross-sectional view of a conventional stacked capacitor.
１ 半導体基板でp-Si基板 ２ 分離絶縁膜でSiO2膜 ３ セルFET のソースドレイン領域 ４ セルFET のゲート絶縁膜 ５ セルFET のゲート ６ 層間絶縁膜でSiO2膜 ７ 記憶ノード 7C 記憶ノードの中央部を構成する第２のポリシリコン
膜 7D 記憶ノードで第１のポリシリコン膜 ８ キャパシタの誘電体膜でSi3N4 膜 ９ 対向電極でポリシリコン膜Reference Signs List 1 p-Si substrate as semiconductor substrate 2 SiO 2 film as isolation insulating film 3 source / drain region of cell FET 4 gate insulating film of cell FET 5 gate of cell FET 6 SiO 2 film as interlayer insulating film 7 storage node 7C storage node The second polysilicon film constituting the central part 7D The first polysilicon film at the storage node 8 The dielectric film of the capacitor Si 3 N 4 film 9 The polysilicon film at the counter electrode
Claims (2)
対向電極とが誘電体膜を介して積層されたセルキャパシ
タを有し，該記憶ノードは，第１のエッチング端で規定された第１
の記憶ノード用導電層と，該第１の記憶ノード用導電層
を覆い，該第１のエッチング端よりも外方の第２のエッ
チング端で規定された第２の記憶ノード用導電層とを有
し， 該記憶ノードの中央部の厚さが周辺部より厚いことを特
徴とする半導体メモリ装置。To 1. A substrate storage node formed of a conductive film and the counter electrode has a cell capacitor stacked via the dielectric film, the storage node is first defined by a first etching end 1
Storage node conductive layer, and the first storage node conductive layer
And a second edge outside the first etched end.
A second storage node conductive layer defined at the switching end.
And, a semiconductor memory device in which the thickness of the central portion of the storage node is equal to or thicker than the peripheral portion.
タの一端にコンタクトホールを開口し，A contact hole at one end of the 第１のポリシリコン層を形成したのち，選択的にエッチAfter forming the first polysilicon layer, selectively etch
ングして該コンタクトホールの領域に第１のエッチングEtching in the region of the contact hole.
端で規定された第１の記憶ノード用導電層を形成し，Forming a first storage node conductive layer defined by the end; 第２のポリシリコン層を形成したのち選択的にエッチンSelectively etch after forming second polysilicon layer
グして該第１の記憶用導電層を覆い，該第１のエッチンCover the first storage conductive layer, and remove the first etchant.
グ端よりも外方の第２のエッチング端で規定された第２Second edge defined by a second etched edge outside the edge
の記憶ノード用導電層を形成し，Forming a conductive layer for the storage node of 次いで，誘電体膜，対向電極を形成することによってキNext, a key is formed by forming a dielectric film and a counter electrode.
ャパシタを形成することを特徴とする半導体メモリ装置Semiconductor memory device forming capacitor
の製造方法。Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3035802A JP2956234B2 (en) | 1991-03-01 | 1991-03-01 | Semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3035802A JP2956234B2 (en) | 1991-03-01 | 1991-03-01 | Semiconductor memory device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04274360A JPH04274360A (en) | 1992-09-30 |
| JP2956234B2 true JP2956234B2 (en) | 1999-10-04 |
Family
ID=12452054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3035802A Expired - Fee Related JP2956234B2 (en) | 1991-03-01 | 1991-03-01 | Semiconductor memory device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP2956234B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08288472A (en) * | 1995-04-17 | 1996-11-01 | Oki Electric Ind Co Ltd | Semiconductor memory cell and its manufacture |
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1991
- 1991-03-01 JP JP3035802A patent/JP2956234B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| JPH04274360A (en) | 1992-09-30 |
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