JP2947828B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2947828B2 JP2947828B2 JP22735189A JP22735189A JP2947828B2 JP 2947828 B2 JP2947828 B2 JP 2947828B2 JP 22735189 A JP22735189 A JP 22735189A JP 22735189 A JP22735189 A JP 22735189A JP 2947828 B2 JP2947828 B2 JP 2947828B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- arsenic
- substrate
- heat treatment
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜形成方法に係り、段差急峻部の配線の低
抵抗化、基板への不純物拡散の低減を図り、LSIデバイ
ス製造の簡略化、低温化に好適なヒ素を含むシリコン膜
を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a thin film, which aims at reducing the resistance of wiring at a steep step portion, reducing impurity diffusion into a substrate, and simplifying LSI device manufacturing. The present invention relates to a method for forming a silicon film containing arsenic suitable for lowering the temperature.
モノシラン（SiH4）の熱分解を用い、減圧化学気相成
長法（LPCVD法）により形成した多結晶シリコン（Si）
膜は、広く半導体装置の電極や配線に利用されている。
LPCVD法により形成した多結晶Si膜は、そのままでは抵
抗が極めて大きいため、その後の工程で、不純物を周知
の熱拡散法あるいはイオン打込み法により導入し、導電
性を得ている。なお、この種の薄膜形成方法として関連
するものには、例えばジヤーナル オブ ジ エレクト
ロケミカル ソサイエテイー 127,（1980年）686頁か
ら690頁（J.Electrochem.Soc.127（1980）pp686−690）
が挙げられる。Polycrystalline silicon (Si) formed by low pressure chemical vapor deposition (LPCVD) using thermal decomposition of monosilane (SiH 4 )
The film is widely used for electrodes and wiring of a semiconductor device.
Since the polycrystalline Si film formed by the LPCVD method has an extremely high resistance as it is, impurities are introduced by a well-known thermal diffusion method or an ion implantation method in a subsequent step to obtain conductivity. Related to this type of thin film forming method include, for example, Journal of the Electrochemical Society 127, (1980) pp. 686 to 690 (J. Electrochem. Soc. 127 (1980) pp. 686-690).
Is mentioned.
上記従来技術のうち、多結晶Si膜にイオン打込みを行
なつた場合、急峻な段差側壁部では不純物濃度の不足す
る領域を生じ、電極あるいは配線に十分な導電性を付与
できない場合があつた。また、打込んだ不純物を拡散，
活性化するためには、900℃以上の熱処理が必要であつ
た。Among the above-mentioned prior arts, when ion implantation is performed on a polycrystalline Si film, a region where the impurity concentration is insufficient occurs at a steep step side wall portion, and sufficient conductivity may not be provided to an electrode or a wiring. Also diffuses the implanted impurities,
For activation, a heat treatment at 900 ° C. or higher was required.
一方、熱拡散法による不純物のドーピングにおいて
は、高温・長時間の拡散を行なえば、急峻な段差側壁部
へもドーピングが可能である。しかし、多結晶Si膜がSi
基板と接している場所では、基板にまで不純物が拡散
し、例えばMOSトランジスタを構成するソース・ドレイ
ンの不純物分布を乱すといつた不都合があつた。On the other hand, in the doping of impurities by a thermal diffusion method, if diffusion is performed at high temperature for a long time, it is possible to dope even to a steep step wall portion. However, the polycrystalline Si film
At a place in contact with the substrate, the impurity diffuses into the substrate, and for example, there is a disadvantage that the impurity distribution of the source / drain constituting the MOS transistor is disturbed.
更に、溝型構造キヤパシタにおいては、溝内に埋め込
まれた電極を多結晶Siで形成し、イオン打込み法あるい
は熱拡散法を行なつた場合、多結晶Si全体に充分な量の
不純物をドーピングすることは困難であつた。Furthermore, in the groove-type structure capacitor, an electrode embedded in the groove is formed of polycrystalline Si, and when ion implantation or thermal diffusion is performed, a sufficient amount of impurities is doped into the entire polycrystalline Si. It was difficult.
上記問題点を解決する１つの方法として、不純物をド
ーピングしながら多結晶Si膜を形成する方法（in−situ
ドーピング法）がある。すなわち、SiH4とともに不純物
源となるフオスフイン（PH3），ジボラン（B2H6），ア
ルシン（AsH3）等を流し、多結晶Si膜を形成しながら不
純物をドーピングする方法である。しかし、SiH4とPH3
あるいはAsH3を用いて膜を形成した場合には、PH3ある
いはAsH3を添加しない場合に比べて膜の成長速度が約１
桁減少し、量産性に乏しいこと、また、不純物を十分に
活性化するために900℃〜1000℃という高温の熱処理が
必要であるため、熱拡散法と同様に基板Si中への不純物
拡散を防ぐことができないといつた欠点があつた。As one method for solving the above problem, a method of forming a polycrystalline Si film while doping impurities (in-situ
Doping method). In other words, a method is used in which phos fin (PH 3 ), diborane (B 2 H 6 ), arsine (AsH 3 ), or the like, which serves as an impurity source, flows along with SiH 4 , and is doped with impurities while forming a polycrystalline Si film. But SiH 4 and PH 3
Alternatively, when a film is formed using AsH 3 , the growth rate of the film is about one time as compared with the case where PH 3 or AsH 3 is not added.
In order to sufficiently activate the impurities, a high-temperature heat treatment of 900 ° C. to 1000 ° C. is necessary, so that the impurity diffusion into the substrate Si is performed similarly to the thermal diffusion method. There was a disadvantage that I could not prevent.
膜の成長速度を増大するために、SiH4の代りにSi2H6
と、PH3とを用いる方法も試みられている。しかし、こ
れまでの技術では、Si2H6とPH3を原料ガスとしても、不
純物を活性化するためには、900〜1000℃の熱処理が必
要である。また、リンはヒ素に比べて拡散定数が大きい
ため、PH3を原料ガスに用いている限り、不純物の基板S
iへの拡散は避けられない。To increase the growth rate of the film, Si 2 H 6 was used instead of SiH 4.
When, it has been attempted a method of using a PH 3. However, in the conventional techniques, even if Si 2 H 6 and PH 3 are used as a source gas, a heat treatment at 900 to 1000 ° C. is necessary to activate the impurities. Further, since phosphorus has a larger diffusion constant than arsenic, as long as PH 3 is used as a source gas, the impurity substrate S
Spreading to i is inevitable.
本発明の目的は、上記従来技術の問題点を解決すべ
く、生産性に優れ、基板Siへの不純物拡散がほとんどな
い、導電性の高いSi膜を形成する薄膜形成方法を提供す
ることにある。An object of the present invention is to provide a thin film forming method for forming a highly conductive Si film which is excellent in productivity and hardly diffuses impurities into a substrate Si, in order to solve the above problems of the conventional technology. .
上記目的は、以下によつて達成される。 The above object is achieved by the following.
原料ガスとしてSi2H6あるいはSi3H8（トリシラン）
とAsH3を含む混合ガスを用いる。Si 2 H 6 or Si 3 H 8 (trisilane) as source gas
And a mixed gas containing AsH 3.
膜形成温度を450℃以上550℃以下とする。 The film formation temperature is set to 450 ° C. or higher and 550 ° C. or lower.
Si2H6は気相中で Si2H6（ｇ）→SiH2（ｇ）＋SiH4（ｇ） のように分解し、SiH2（シリレン）を生じる。SiH2はSi
H4に比べ反応性が高いので、AsH3により基板Si表面への
吸着を阻害されることがない。従って、AsH3の存在の有
無に関係なく、高速で膜を堆積することが可能である。Si 2 H 6 is decomposed in the gas phase as follows: Si 2 H 6 (g) → SiH 2 (g) + SiH 4 (g) to produce SiH 2 (silylene). SiH 2 is Si
Because of the high reactivity compared to H 4, not to be inhibited adsorption to the substrate Si surface by AsH 3. Therefore, it is possible to deposit a film at a high speed regardless of the presence or absence of AsH 3 .
Si2H6とAsH3を原料ガスとした場合、膜形成温度が550
℃以下では、形成した膜は非晶質となる。この膜は、65
0℃,15分間という比較的低温の熱処理で結晶化するが、
その後、更に高温で熱処理を行なつても結晶粒径に変化
を生じない。また不純物として導入されたヒ素は、650
℃の熱処理で完全に活性化される。従つて、650℃の熱
処理で十分な導電性が得られ、更に高温での熱処理を行
なつても抵抗率に変化を生じない。When Si 2 H 6 and AsH 3 are used as source gases, the film formation temperature is 550
At a temperature lower than or equal to ° C., the formed film becomes amorphous. This membrane has 65
It crystallizes with a relatively low temperature heat treatment of 0 ° C for 15 minutes,
Thereafter, even if heat treatment is performed at a higher temperature, the crystal grain size does not change. Arsenic introduced as an impurity is 650
It is completely activated by heat treatment at ℃. Accordingly, sufficient conductivity can be obtained by the heat treatment at 650 ° C., and the resistivity does not change even if the heat treatment is performed at a higher temperature.
なお、多結晶状態のSi膜にヒ素イオンを打込んだ場
合、及び、ヒ素をドーピングしながら多結晶のSi膜を形
成した場合には、結晶粒は900℃以上の熱処理を行なわ
ないと成長しないことは公知の事実である。Note that, when arsenic ions are implanted into a polycrystalline Si film, and when a polycrystalline Si film is formed while doping arsenic, crystal grains do not grow unless heat treatment is performed at 900 ° C. or higher. This is a known fact.
以上述べたように、Si2H6とAsH3を原料ガスとしてヒ
素をドーピングしながら非晶質状態でSi膜を形成する
と、650℃程度の熱処理により膜中の不純物の活性化と
結晶粒の成長が完了する。このため、従来法のような高
温の熱処理を行なわなくても、充分に抵抗の低いヒ素を
含むSi膜が得られる。また、ヒ素は、Si中での拡散定数
がリンに比べて約１桁小さい。従つて、本発明によれ
ば、不純物の下層Si層への拡散を防止することができ
る。As described above, when an Si film is formed in an amorphous state while doping arsenic with Si 2 H 6 and AsH 3 as source gases, heat treatment at about 650 ° C. activates impurities in the film and reduces crystal grain size. Growth is complete. Therefore, an arsenic-containing Si film having a sufficiently low resistance can be obtained without performing a high-temperature heat treatment as in the conventional method. In addition, arsenic has a diffusion constant in Si that is about one digit smaller than that of phosphorus. Therefore, according to the present invention, diffusion of impurities into the lower Si layer can be prevented.
以下、本発明の一実施例を説明する。 Hereinafter, an embodiment of the present invention will be described.
実施例１ 第３図に、実験に用いた装置の概略図を示す。石英管
10の中央に治具30を置き、これに18mmの間隔で、試料基
板40を装着した。試料基板には、Si上に熱酸化膜100nm
を形成したものを用いた。Example 1 FIG. 3 shows a schematic diagram of an apparatus used for the experiment. Quartz tube
A jig 30 was placed at the center of 10, and sample substrates 40 were mounted on the jig 30 at intervals of 18 mm. The sample substrate has a thermal oxide film of 100 nm on Si
Was used.
基板40を装着し、石英管10内を排気した後、バルブ50
及びバルブ60を開けて、Si2H6を50cc/min、AsH3を0.2cc
/min同時に流した。Si2H6とAsH3を流している間の石英
管10内圧力は30Paに保持した。所定時間ガスを流して膜
形成を行なつた後、試料基板40を取り出した。その後、
650℃,800℃,900℃,1000℃の窒素雰囲気中で20分間熱処
理を行なつた。熱処理を行なつた試料は、抵抗率を四探
針法により、また、キヤリア濃度と移動度をホール効果
測定により測定した。After mounting the substrate 40 and evacuating the quartz tube 10, the valve 50
And opening the valve 60, the Si 2 H 6 50cc / min, the AsH 3 0.2 cc
/ min at the same time. The pressure in the quartz tube 10 during the flow of Si 2 H 6 and AsH 3 was kept at 30 Pa. After forming a film by flowing gas for a predetermined time, the sample substrate 40 was taken out. afterwards,
Heat treatment was performed for 20 minutes in a nitrogen atmosphere at 650 ° C, 800 ° C, 900 ° C, and 1000 ° C. For the heat-treated sample, the resistivity was measured by a four-probe method, and the carrier concentration and the mobility were measured by the Hall effect measurement.
第１図は、上記基板40の抵抗率の測定結果を示すもの
で横軸に熱処理温度、縦軸に膜の抵抗率をとつたもので
ある。ここでは膜形成温度が525℃,550℃,575℃におけ
る結果を示した。膜形成温度が550℃より高温の場合、
抵抗率は熱処理温度の上昇に従い減少した。これに対
し、膜形成温度が550℃以下の場合には、650℃の熱処理
で十分な導電性が得られ、更に高温で熱処理を行なつて
も抵抗率に変化を生じなかつた。なお、550℃以下の温
度で形成した膜は、形成したままの状態では非晶質であ
つた。FIG. 1 shows the measurement results of the resistivity of the substrate 40, wherein the horizontal axis represents the heat treatment temperature and the vertical axis represents the film resistivity. Here, the results at film formation temperatures of 525 ° C, 550 ° C, and 575 ° C are shown. If the film formation temperature is higher than 550 ° C,
The resistivity decreased with increasing heat treatment temperature. On the other hand, when the film forming temperature was 550 ° C. or lower, sufficient conductivity was obtained by the heat treatment at 650 ° C., and even when the heat treatment was performed at a higher temperature, the resistivity did not change. The film formed at a temperature of 550 ° C. or lower was amorphous as it was formed.
第２図は、上記基板40についてのキヤリア濃度の測定
結果を示したもので、横軸に熱処理温度、縦軸にキヤリ
ア濃度をとつたものである。抵抗率と同様、550℃以下
の膜形成温度では、キヤリア濃度は熱処理温度によらず
ほぼ一定であつた。FIG. 2 shows the measurement results of the carrier concentration of the substrate 40, wherein the horizontal axis represents the heat treatment temperature and the vertical axis represents the carrier concentration. As with the resistivity, at a film formation temperature of 550 ° C. or less, the carrier concentration was almost constant regardless of the heat treatment temperature.
第１図，第２図から、550℃以下でヒ素をドーピング
しながら形成したSi膜は、650℃の熱処理で不純物の活
性化が完了し、それ以上高温での熱処理を行なつても膜
の電気特性に変化がないことがわかる。According to FIGS. 1 and 2, the Si film formed by doping arsenic at 550 ° C. or less completes the activation of impurities by the heat treatment at 650 ° C. It can be seen that there is no change in the electrical characteristics.
第１図，第２図には、比較のため、従来法における結
果も併せて示した。ここでいう従来法とは、SiH4とAsH3
を原料ガスとして用い、630℃,80Paの条件下でSiH4を20
0cc/min、AsH3を0.2cc/min流して、ヒ素をドーピングし
ながらSi膜を形成したものである。同膜は、形成したま
まの状態で、多結晶質であつた。Si2H6とAsH3を用いた
場合と同様の熱処理を行なつたが、不純物の活性化のた
めには900℃以上の熱処理が必要であつた。1 and 2 also show the results of the conventional method for comparison. Here, the conventional method refers to SiH 4 and AsH 3
Using SiH 4 as a source gas at 630 ° C and 80 Pa
An Si film was formed while doping arsenic by flowing AsH 3 at 0.2 cc / min at 0 cc / min. The film was polycrystalline as formed. The same heat treatment as in the case of using Si 2 H 6 and AsH 3 was performed, but a heat treatment at 900 ° C. or more was necessary for activating the impurities.
なお、SiH4を用いて630℃で多結晶状態のSi膜200nmを
形成し、これにヒ素イオンを打込んだ場合には、不純物
の活性化のために900℃以上の熱処理が必要なるとは公
知の事実である。It is publicly known that when arsenic ions are implanted into a 200 nm polycrystalline Si film formed at 630 ° C. using SiH 4 , a heat treatment at 900 ° C. or higher is required to activate impurities. It is a fact of.
本実施例によれば、原料ガスとしてSi2H6とAsH3を用
いて、ヒ素をドーピングしながら550℃以下の温度でSi
膜を形成することにより、SiH4とAsH3を原料ガスとして
ヒ素をドーピングしながら多結晶状態のSi膜を形成した
場合、あるいは、多結晶Si膜にイオン打込みによりヒ素
をドーピングした場合よりもはるかに低温（650℃程
度）の熱処理で不純物を活性化できるという効果があ
る。また、膜形成後の熱処理温度が変動しても、膜の抵
抗率が変化しないという利点がある。According to this embodiment, Si 2 H 6 and AsH 3 were used as source gases, and Si was doped at a temperature of 550 ° C. or less while doping arsenic.
By forming a film, a polycrystalline Si film is formed while doping arsenic with SiH 4 and AsH 3 as a source gas, or far more than a case where a polycrystalline Si film is doped with arsenic by ion implantation. In addition, there is an effect that impurities can be activated by heat treatment at a low temperature (about 650 ° C.). Further, there is an advantage that the resistivity of the film does not change even if the heat treatment temperature after the film formation changes.
なお、膜形成温度が550℃以上の膜では、キヤリアの
移動度が40cm2/v・ｓ以上と、従来法に比べ２倍程度大
きい。透過型電子顕微鏡による観察から、550℃以下で
形成した膜は、膜厚の約10倍という、従来法で形成した
Si膜の10倍以上の結晶粒を含むためであることが明らか
となつた。従つて、第１図及び第２図に示したように、
従来法により少ない不純物濃度でも充分な導電性を得る
ことが可能である。そのため、下地Si基板への不純物の
拡散量を低減できるという効果もある。In the case of a film having a film formation temperature of 550 ° C. or higher, the carrier mobility is 40 cm 2 / v · s or more, which is about twice as large as that of the conventional method. From observation with a transmission electron microscope, it was found that the film formed at 550 ° C or lower was formed by the conventional method, which was about 10 times the film thickness.
It became clear that the reason for this is that it contains crystal grains 10 times or more that of the Si film. Therefore, as shown in FIGS. 1 and 2,
It is possible to obtain sufficient conductivity with a low impurity concentration by the conventional method. Therefore, there is also an effect that the amount of diffusion of impurities into the underlying Si substrate can be reduced.
実施例２ 本実施例では、急峻な段差部の配線に多結晶Si膜を用
いた場合、不純物の導入法により配線抵抗がどの程度異
なるかを判定した例について述べる。Embodiment 2 In this embodiment, an example will be described in which when a polycrystalline Si film is used for a wiring at a steep step portion, how much the wiring resistance differs by an impurity introduction method is determined.
第４図に示す手順で、試料Ａ及び試料Ｂを作成した。
まず、Si基板101に厚さ１μｍの熱酸化膜102を形成した
（第４図（ａ））。次いで、周知のリソグラフイとドラ
イエツチング技術により、幅0.8μｍの溝103を等間隔に
なるように形成した（第４図（ｂ））。続いてLPCVD法
によりSiO2膜104を100nm形成した（第４図（ｃ））。Samples A and B were prepared according to the procedure shown in FIG.
First, a thermal oxide film 102 having a thickness of 1 μm was formed on a Si substrate 101 (FIG. 4A). Next, grooves 103 having a width of 0.8 μm were formed at regular intervals by well-known lithography and dry etching techniques (FIG. 4B). Subsequently, a 100 nm SiO 2 film 104 was formed by LPCVD (FIG. 4C).
次いで、以下の方法で、Si膜形成及び不純物ドーピン
グを行なつた。Next, Si film formation and impurity doping were performed by the following methods.
試料Ａでは、Si2H6 50cc/minとAsH3 0.2cc/minを石英
管内温度525℃、圧力30Paで同時に流し、ヒ素をドーピ
ングしながら200nmのSi膜を形成した。In sample A, 50 cc / min of Si 2 H 6 and 0.2 cc / min of AsH 3 were simultaneously flown at a temperature of 525 ° C. and a pressure of 30 Pa in a quartz tube, and a 200 nm Si film was formed while doping with arsenic.
試料Ｂについては、SiH4を原料ガスとし、630℃,80Pa
の石英管内で200nmの多結晶Si膜を形成した後、ヒ素イ
オンを打込みエネルギー180KeV、打込み量５×1015cm-2
で打込んだ。For Sample B, the SiH 4 as a raw material gas, 630 ° C., 80 Pa
After forming a 200 nm polycrystalline Si film in a quartz tube, the implantation energy of arsenic ions was 180 KeV and the implantation amount was 5 × 10 15 cm −2.
I hit it.
続いて試料Ａは650℃，試料Ｂは900℃の窒素雰囲気で
それぞれ60分間熱処理を行なつた。Subsequently, the sample A was subjected to a heat treatment in a nitrogen atmosphere at 650 ° C. and the sample B was subjected to a heat treatment in a nitrogen atmosphere at 900 ° C. for 60 minutes.
試料ＡのSi膜の平坦部におけるシート抵抗は50Ω／□
であり、段差10個を横切る幅0.8μｍの配線の抵抗は3.0
KΩと、充分な導電性が得られた。試料Ｂの多結晶Si膜
の平坦部におけるシート抵抗は120Ω／□であつたが、
段差10個を横切る幅0.8μｍの配線の抵抗は350KΩと非
常に高抵抗であつた。The sheet resistance at the flat part of the Si film of sample A is 50Ω / □
The resistance of a 0.8 μm-wide wiring across 10 steps is 3.0
KΩ and sufficient conductivity were obtained. Although the sheet resistance in the flat portion of the polycrystalline Si film of Sample B was 120Ω / □,
The resistance of the wiring having a width of 0.8 μm across the ten steps was 350 KΩ, which was extremely high.
本実施例によれば、ヒ素をドーピングしながらSi膜を
形成することにより、イオン打込み法に比べ、急峻な段
差部の配線抵抗を大幅に低減できるという効果がある。According to the present embodiment, by forming the Si film while doping arsenic, there is an effect that the wiring resistance at the steep step can be significantly reduced as compared with the ion implantation method.
実施例３ 本実施例では、不純物ドーピング法の違いが基板Si中
への不純物の拡散深さに与える影響を測定した例につい
て述べる。Embodiment 3 In this embodiment, an example in which the influence of the difference in the impurity doping method on the diffusion depth of the impurity into the substrate Si is measured will be described.
第４図（ｂ）に示した基板を試料として用いた。第３
図の装置を用い、試料Ｃは、石英管内温度525℃，圧力3
0PaでSi2H6 50cc/min、AsH3 0.2cc/minを同時に流し、
試料基板40上にヒ素を含むSi膜200nmを形成した。続い
て650℃の窒素雰囲気中で60分間熱処理した。The substrate shown in FIG. 4 (b) was used as a sample. Third
Using the apparatus shown in the figure, the sample C was 525 ° C.
At 0 Pa, simultaneously flow Si 2 H 6 50 cc / min and AsH 3 0.2 cc / min,
A 200 nm-thick arsenic-containing Si film was formed on the sample substrate 40. Subsequently, heat treatment was performed in a nitrogen atmosphere at 650 ° C. for 60 minutes.
試料Ｄは、石英管内温度630℃，圧力80PaでSiH4を原
料ガスとして200nmの多結晶Si膜を形成した。続いてヒ
素イオンを、180KeVのエネルギーで５×1015cm-2打込
み、その後900℃の窒素雰囲気中で60分間熱処理を行な
つた。For sample D, a 200 nm polycrystalline Si film was formed using SiH 4 as a source gas at a temperature of 630 ° C. and a pressure of 80 Pa in a quartz tube. Subsequently, arsenic ions were implanted at 5 × 10 15 cm −2 at an energy of 180 KeV, and then heat treatment was performed in a nitrogen atmosphere at 900 ° C. for 60 minutes.
試料Ｃ及び試料Ｄは、熱処理後、溝103と垂直を平面
に沿つて劈頭し、フツ酸・硝酸混合溶液でエツチングし
た後、断面を走査型電子顕微鏡で観察し、第４図（ｄ）
の拡散層幅ｘを拡散深さとして評価した。After heat treatment, the samples C and D were cleaved along a plane perpendicular to the groove 103, etched with a mixed solution of hydrofluoric acid and nitric acid, and observed with a scanning electron microscope for the cross section.
Was evaluated as the diffusion depth.
試料Ｄの拡散深さが0.1μｍであつたのに対し、試料
Ｃの拡散深さは0.01μｍ以下と、無視できる程小さかつ
た。While the diffusion depth of sample D was 0.1 μm, the diffusion depth of sample C was 0.01 μm or less, which was negligibly small.
本実施例によれば、原料ガスとしてSi2H6とAsH3を用
い、ヒ素をドーピングしながらSi膜を非晶質状態で形成
することにより、活性化のための熱処理が大幅に低温化
できるので、基板中への不純物の拡散深さを無視できる
ほどに小さくできるという効果が明らかである。According to this embodiment, by using Si 2 H 6 and AsH 3 as source gases and forming the Si film in an amorphous state while doping arsenic, the heat treatment for activation can be significantly reduced in temperature. Therefore, it is apparent that the diffusion depth of the impurity into the substrate can be reduced to a negligible level.
実施例４ 本実施例では、Si膜の形成方法と膜表面の凹凸の関係
について測定した例について述べる。Embodiment 4 In this embodiment, an example in which the relationship between the method of forming a Si film and the unevenness of the film surface is measured will be described.
実施例３で、走査型電子顕微鏡により断面を観察した
試料Ｃ及びＤについて、Si膜表面の凹凸を同じく走査型
電子顕微鏡により観察した。In the samples C and D whose cross sections were observed by the scanning electron microscope in Example 3, the unevenness of the surface of the Si film was also observed by the scanning electron microscope.
本発明の実施例によるSi2H6とAsH3を用いて、525℃で
非晶質状態で形成したSi膜（試料Ｃ）の表面は、５万倍
の倍率でも凹凸は全く観察されず、極めて平滑であつ
た。これに対し、従来例としての多結晶Si膜形成後にヒ
素イオン打込みを行なつた試料Ｄの表面には、0.1μｍ
程度の凹凸が観察された。なお、試料ＣおよびＤの表面
状態は、熱処理を行なつても変化しなかつた。The surface of the Si film (sample C) formed in an amorphous state at 525 ° C. using Si 2 H 6 and AsH 3 according to the embodiment of the present invention does not show any irregularities even at a magnification of 50,000 times. It was extremely smooth. On the other hand, the surface of the sample D in which arsenic ion implantation was performed after forming a polycrystalline Si film as a conventional example was 0.1 μm
A degree of unevenness was observed. The surface states of the samples C and D did not change even after the heat treatment.
試料３では525℃でSi膜を形成したが、膜形成温度は5
75℃以下であれば、平滑な表面を得ることができる。Si
2H6のかわりにSiH4を原料ガスとして用い、630℃でヒ素
を添加しながら形成した多結晶Si膜の表面では、0.05μ
ｍ程度の細かい凹凸が観察された。In Sample 3, a Si film was formed at 525 ° C.
At 75 ° C. or lower, a smooth surface can be obtained. Si
Using SiH 4 instead of 2 H 6 as the source gas, the surface of the polycrystalline Si film formed while adding arsenic at
m fine irregularities were observed.
本実施例によれば、原料ガスとしてSi2H6とAsH3を用
い、ヒ素をドーピングしながら非晶質状態でSi膜を形成
することにより、極めて平滑なSi表面を得られる効果が
ある。According to the present embodiment, by using Si 2 H 6 and AsH 3 as source gases and forming an Si film in an amorphous state while doping arsenic, an extremely smooth Si surface can be obtained.
実施例５ 本実施例では、本発明をMOS型トランジスタの形成に
実施した例を示す。Embodiment 5 This embodiment shows an example in which the present invention is applied to the formation of a MOS transistor.
第５図に示した試料を作成した。まず、10Ω・cm（10
0）ｐ型Si基板201の表面に、周知の選択酸化技術により
フイールド酸化膜202を形成した。次いで、酸素雰囲気
中でSi基板を酸化し、20nmのゲート酸化膜203を形成し
た。続いて、LPCVD法により、多結晶Si膜204を200nm形
成した後、リンの熱拡散を行ない、これを加工してゲー
ト電極とした。続いて、リン及びヒ素イオン打込みを順
次行なつた後、900℃の窒素雰囲気中で60分間熱処理を
行ない、ソース・ドレイン領域205を形成した。その
後、CVD法により層間SiO2膜206を形成した。これに接続
孔を開けた。The sample shown in FIG. 5 was prepared. First, 10Ω · cm (10
0) A field oxide film 202 was formed on the surface of a p-type Si substrate 201 by a known selective oxidation technique. Next, the Si substrate was oxidized in an oxygen atmosphere to form a gate oxide film 203 of 20 nm. Subsequently, a polycrystalline Si film 204 was formed to a thickness of 200 nm by LPCVD, and phosphorus was thermally diffused and processed to form a gate electrode. Subsequently, after phosphorus and arsenic ion implantation were sequentially performed, heat treatment was performed in a nitrogen atmosphere at 900 ° C. for 60 minutes to form source / drain regions 205. After that, an interlayer SiO 2 film 206 was formed by a CVD method. A connection hole was made in this.
続いて、Si2H6 50cc/minとAsH3 0.2cc/minを温度525
℃，圧力30Paの石英管内に流し、ヒ素をドーピングしな
がら200nmのSi膜207を非晶質状態で形成した。その後65
0℃の窒素雰囲気で60分間熱処理して、Si膜の結晶化と
ヒ素の活性化を行なつた。そして、Si膜207を加工し
て、引出配線とした。Subsequently, 50 cc / min of Si 2 H 6 and 0.2 cc / min of AsH 3 were added at a temperature of 525.
A 200 nm Si film 207 was formed in an amorphous state while flowing in a quartz tube at 30 ° C. and a pressure of 30 Pa while doping with arsenic. Then 65
Heat treatment was performed in a nitrogen atmosphere at 0 ° C. for 60 minutes to crystallize the Si film and activate arsenic. Then, the Si film 207 was processed into a lead wiring.
比較のため、従来技術として、Si膜207の形成を多結
晶状態で行ない、これにヒ素イオンを180KeV,5×1015cm
-2の条件に打込み、続いて900℃の窒素雰囲気中で60分
熱処理して引出配線を形成した試料も作成した。For comparison, as a conventional technique, a Si film 207 was formed in a polycrystalline state, and arsenic ions were added thereto at 180 KeV, 5 × 10 15 cm.
A sample in which a lead-out wiring was formed by implanting under the condition of -2 and subsequently heat-treating in a nitrogen atmosphere at 900 ° C. for 60 minutes was also prepared.
本発明の方法により作成したMOS型トランジスタは、
従来技術により作成したものに比べ、配線の抵抗が低
く、しかもより高いパンチスルー耐圧を示した。The MOS transistor prepared by the method of the present invention is:
Compared to those made by the prior art, the wiring resistance was lower and the punch-through breakdown voltage was higher.
本発明によれば、Si2H6とAsH3を用い、ヒ素をドーピ
ングしながら非晶質状態で形成し、これを結晶化したSi
膜をMOS型トランジスタのソース・ドレインの引出配線
に用いることにより、トランジスタのパンチスルー耐圧
が向上できるという効果がある。According to the present invention, Si 2 H 6 and AsH 3 are formed in an amorphous state while doping with arsenic, and this is crystallized Si.
The use of the film for the source / drain extraction wiring of the MOS transistor has the effect of improving the punch-through breakdown voltage of the transistor.
上記の実施例１から実施例５では、条件を限定して実
験を行なつた。石英管内の温度が450℃より低い場合に
は、膜の成長速度が1nm/min以下と極めて小さくなり、
スループツトが著しく低下するため、実際のLSIデバイ
ス製造には適さない。石英管内の温度が550℃より高い
場合には、第１図あるいは第２図に示した如く、熱処理
温度がかわると膜の抵抗率，キヤリア濃度，移動度が大
きく変化するため、制御性が悪くなる。石英管内温度が
450℃以上、550℃以下の範囲であれば、いずれの実施例
においても所望の効果を得ることができる。また、Si2H
6のかわりにSi3H8を用いた場合においても、上記実施例
のいずれにおいても所望の効果を得ることができる。な
お、キヤリアガスとして、窒素あるいはヘリウムなどの
不活性なガスを混合することにより、ウエーハ間の膜厚
・抵抗の均一性を向上することができる。このような場
合においても本発明が有効であることは言うまでもな
い。In Examples 1 to 5 described above, experiments were performed under limited conditions. When the temperature in the quartz tube is lower than 450 ° C., the growth rate of the film becomes extremely small at 1 nm / min or less,
Since the throughput is significantly reduced, it is not suitable for actual LSI device manufacturing. When the temperature in the quartz tube is higher than 550 ° C., as shown in FIG. 1 or FIG. 2, when the heat treatment temperature is changed, the resistivity, the carrier concentration, and the mobility of the film greatly change, so that the controllability is poor. Become. The temperature inside the quartz tube
In the range of 450 ° C. or more and 550 ° C. or less, a desired effect can be obtained in any of the embodiments. Also, Si 2 H
Even when Si 3 H 8 is used instead of 6, the desired effects can be obtained in any of the above embodiments. By mixing an inert gas such as nitrogen or helium as a carrier gas, the uniformity of film thickness and resistance between wafers can be improved. Needless to say, the present invention is effective in such a case.
本発明によれば、膜厚方向に所望の不純物分布を有す
るヒ素を含むSi膜を形成することができる。このSi膜中
の不純物は、従来法よりはるかに低温の熱処理で活性化
させることが可能である。従つて、基板の不純物分布を
乱すことなく、急峻な段差の側壁や溝内の多結晶Si膜へ
のドーピングが可能となり、電極・配線の低抵抗化が図
れる。更に、LSIデバイスの製造において、大幅な工程
の簡略化，低温化を図ることができ、歩留りの向上、生
産コストの低減にも大きな効果がある。According to the present invention, an Si film containing arsenic having a desired impurity distribution in a film thickness direction can be formed. The impurities in the Si film can be activated by a heat treatment at a much lower temperature than in the conventional method. Accordingly, it is possible to dope the polycrystalline Si film in the side wall or the trench having the steep step without disturbing the impurity distribution of the substrate, and to reduce the resistance of the electrode / wiring. Furthermore, in the manufacture of LSI devices, it is possible to greatly simplify the process and to lower the temperature, which has a great effect on improving the yield and reducing the production cost.
第１図は本発明の実施例と従来例によるSi薄膜の熱処理
温度と抵抗率の関係を示す測定図、第２図は本発明の実
施例と従来例によるSi薄膜の熱処理温度とキヤリア濃度
の関係を示す測定図、第３図は本発明を実施するにあた
り用いた装置の模式的側断面図、第４図は本発明の実施
例で用いた試料の作成手順を示す断面図、第５図は本発
明の方法を用いて作成した半導体装置の断面図である。 10……石英管、20……ヒータ、30……治具、40……基
板、50,60,70……バルブ、80……排気系、101……Si基
板、102……熱酸化膜、103……段差部、104……CVDSiO2
膜、105……多結晶Si膜、106……拡散層、201……Si基
板、202……フイールド酸化膜、203……ゲート酸化膜、
204……リンドープSi膜、205……拡散層、206……CVDSi
O2膜、207……ヒ素ドープSi膜。FIG. 1 is a measurement diagram showing the relationship between the heat treatment temperature and the resistivity of the Si thin film according to the embodiment of the present invention and the conventional example, and FIG. FIG. 3 is a measurement view showing the relationship, FIG. 3 is a schematic side sectional view of an apparatus used in carrying out the present invention, FIG. 4 is a sectional view showing a procedure for preparing a sample used in the embodiment of the present invention, FIG. FIG. 2 is a cross-sectional view of a semiconductor device manufactured by using the method of the present invention. 10 ... quartz tube, 20 ... heater, 30 ... jig, 40 ... substrate, 50, 60, 70 ... valve, 80 ... exhaust system, 101 ... Si substrate, 102 ... thermal oxide film, 103: Stepped portion, 104: CVD SiO 2
Film 105 polycrystalline silicon film 106 diffusion layer 201 silicon substrate 202 field oxide film 203 gate oxide film
204: phosphorus-doped Si film, 205: diffusion layer, 206: CVDSi
O 2 film, 207 ... Arsenic-doped Si film.
フロントページの続き (56)参考文献 特開 昭59−96723（ＪＰ，Ａ) 特開 昭63−137411（ＪＰ，Ａ) 特開 昭63−299363（ＪＰ，Ａ) 特開 昭64−53562（ＪＰ，Ａ) 特開 昭60−121716（ＪＰ，Ａ) 特開 昭61−15322（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/28 - 21/288 H01L 21/205 H01L 21/20 H01L 29/41 - 21/45 H01L 21/22 - 21/225 Continuation of front page (56) References JP-A-59-96723 (JP, A) JP-A-63-137411 (JP, A) JP-A-63-299363 (JP, A) JP-A-64-53562 (JP) , A) JP-A-60-121716 (JP, A) JP-A-61-15322 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/28-21/288 H01L 21/205 H01L 21/20 H01L 29/41-21/45 H01L 21/22-21/225
Claims (6)
い、半導体基板上に、砒素をドーピングしながら非晶質
のシリコン膜を形成する工程と、 前記半導体基板を650℃以上800℃以下で熱処理すること
により、前記シリコン膜を結晶化させ多結晶シリコン膜
を形成すると共に、前記砒素を前記半導体基板に拡散さ
せる工程とを有することを特徴とする半導体装置の製造
方法。1. A step of forming an amorphous silicon film on a semiconductor substrate while doping arsenic using disilane and arsine as a source gas, and heat-treating the semiconductor substrate at 650 ° C. to 800 ° C. Crystallizing the silicon film to form a polycrystalline silicon film, and diffusing the arsenic into the semiconductor substrate.
は、450℃以上550℃以下であることを特徴とする請求項
１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the step of forming the amorphous silicon film is performed at a temperature of 450 ° C. or more and 550 ° C. or less.
させる工程でもあることを特徴とする請求項１または２
に記載の半導体装置の製造方法。3. The method according to claim 1, wherein said heat-treating step is a step of activating said arsenic.
13. The method for manufacturing a semiconductor device according to item 5.
に拡散深さ0.01μｍ以下で拡散させる工程であることを
特徴とする請求項１乃至３何れかに記載の半導体装置の
製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of diffusing is a step of diffusing the semiconductor substrate with a diffusion depth of 0.01 μm or less.
及びアルシンを用い砒素を含んだ非晶質のシリコン膜を
形成する工程と、 前記基板を650℃以上800℃以下で熱処理することによ
り、前記非晶質のシリコン膜を結晶化させると共に、前
記砒素を前記基板内に拡散させる工程とを有することを
特徴とする半導体装置の製造方法。5. A step of forming an insulating film on a substrate, a step of forming an opening in the insulating film, and the step of forming an opening on the substrate in the opening using arsenic using disilane and arsine as a source gas. Forming an amorphous silicon film; and heat-treating the substrate at 650 ° C. to 800 ° C. to crystallize the amorphous silicon film and diffuse the arsenic into the substrate. And a method for manufacturing a semiconductor device.
に拡散深さ0.01μｍ以下で拡散させる工程であることを
特徴とする請求項５に記載の半導体装置の製造方法。6. The method according to claim 5, wherein the step of diffusing is a step of diffusing into the semiconductor substrate at a diffusion depth of 0.01 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22735189A JP2947828B2 (en) | 1989-09-04 | 1989-09-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22735189A JP2947828B2 (en) | 1989-09-04 | 1989-09-04 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0391239A JPH0391239A (en) | 1991-04-16 |
| JP2947828B2 true JP2947828B2 (en) | 1999-09-13 |
Family
ID=16859440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22735189A Expired - Fee Related JP2947828B2 (en) | 1989-09-04 | 1989-09-04 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2947828B2 (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2616554B2 (en) * | 1994-04-22 | 1997-06-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP4866534B2 (en) | 2001-02-12 | 2012-02-01 | エーエスエム アメリカ インコーポレイテッド | Improved deposition method for semiconductor films. |
| US7026219B2 (en) | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| US6815007B1 (en) | 2002-03-04 | 2004-11-09 | Taiwan Semiconductor Manufacturing Company | Method to solve IMD-FSG particle and increase Cp yield by using a new tougher UFUN season film |
| WO2004009861A2 (en) | 2002-07-19 | 2004-01-29 | Asm America, Inc. | Method to form ultra high quality silicon-containing compound layers |
| US7294582B2 (en) | 2002-07-19 | 2007-11-13 | Asm International, N.V. | Low temperature silicon compound deposition |
| US7186630B2 (en) | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| US7092287B2 (en) | 2002-12-18 | 2006-08-15 | Asm International N.V. | Method of fabricating silicon nitride nanodots |
| US7629270B2 (en) | 2004-08-27 | 2009-12-08 | Asm America, Inc. | Remote plasma activated nitridation |
| US7966969B2 (en) | 2004-09-22 | 2011-06-28 | Asm International N.V. | Deposition of TiN films in a batch reactor |
| US7674726B2 (en) | 2004-10-15 | 2010-03-09 | Asm International N.V. | Parts for deposition reactors |
| US7427571B2 (en) | 2004-10-15 | 2008-09-23 | Asm International, N.V. | Reactor design for reduced particulate generation |
| US7718518B2 (en) | 2005-12-16 | 2010-05-18 | Asm International N.V. | Low temperature doped silicon layer formation |
| US7553516B2 (en) | 2005-12-16 | 2009-06-30 | Asm International N.V. | System and method of reducing particle contamination of semiconductor substrates |
| US7851307B2 (en) | 2007-08-17 | 2010-12-14 | Micron Technology, Inc. | Method of forming complex oxide nanodots for a charge trap |
| US7833906B2 (en) | 2008-12-11 | 2010-11-16 | Asm International N.V. | Titanium silicon nitride deposition |
| KR101713434B1 (en) * | 2015-09-02 | 2017-03-07 | 길재수 | Sectional Furniture and Assemble Method thereof |
-
1989
- 1989-09-04 JP JP22735189A patent/JP2947828B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0391239A (en) | 1991-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2947828B2 (en) | Method for manufacturing semiconductor device | |
| KR900007686B1 (en) | Vapor-phase growth process | |
| US7176109B2 (en) | Method for forming raised structures by controlled selective epitaxial growth of facet using spacer | |
| US6713359B1 (en) | Semiconductor device and method of manufacturing the same including raised source/drain comprising SiGe or SiC | |
| KR19990072884A (en) | Method for producing a polycrystalline silicon structure | |
| JPH05343316A (en) | Manufacture of semiconductor device | |
| JPH1050989A (en) | Fabrication of semiconductor device | |
| JPH11150249A (en) | Forming method of uneven polysilicon layer and substrate treatment device used by the same and semiconductor memory device | |
| US5004702A (en) | Preparation method of selective growth silicon layer doped with impurities | |
| US5242859A (en) | Highly doped semiconductor material and method of fabrication thereof | |
| JPH08139278A (en) | Manufacture of semiconductor device | |
| US6514803B1 (en) | Process for making an amorphous silicon thin film semiconductor device | |
| JP3116163B2 (en) | Method of manufacturing insulated gate field effect transistor | |
| US8158495B2 (en) | Process for forming a silicon-based single-crystal portion | |
| JP2690917B2 (en) | Thin film forming method and semiconductor device manufacturing method | |
| KR19980024337A (en) | Method for manufacturing a silicon thin film conductive element | |
| JPH0653491A (en) | Fabrication of semiconductor device | |
| JP2707985B2 (en) | Method for manufacturing semiconductor device | |
| JPH097909A (en) | Method of manufacturing semiconductor device | |
| JPS5917529B2 (en) | Manufacturing method of semiconductor device | |
| KR100472855B1 (en) | Polycrystalline silicon thin film manufacturing method of semiconductor device | |
| JP3329628B2 (en) | Method for manufacturing semiconductor device | |
| US20070254450A1 (en) | Process for forming a silicon-based single-crystal portion | |
| JP3064363B2 (en) | Method of forming Si thin film | |
| JP2876414B2 (en) | Manufacturing method of diffusion resistance element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |