JP2943399B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2943399B2 JP2943399B2 JP3144320A JP14432091A JP2943399B2 JP 2943399 B2 JP2943399 B2 JP 2943399B2 JP 3144320 A JP3144320 A JP 3144320A JP 14432091 A JP14432091 A JP 14432091A JP 2943399 B2 JP2943399 B2 JP 2943399B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- memory cell
- semiconductor integrated
- diffusion layer
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に溝型メモリセルを有する半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having a groove type memory cell.
【０００２】[0002]
【従来の技術】従来の半導体集積回路は、半導体ウェー
ハの内部欠陥を評価するために、まず、半導体ウェーハ
を割って、その後シリコンのエッチング液に浸し、内部
析出欠陥部分とシリコン結晶部分のエッチングレートの
差による外観の差異を観察することにより内部欠陥を評
価していた。2. Description of the Related Art In a conventional semiconductor integrated circuit, in order to evaluate internal defects of a semiconductor wafer, a semiconductor wafer is first cracked and then immersed in a silicon etchant to etch an internal deposition defect portion and a silicon crystal portion. The internal defect was evaluated by observing the difference in appearance due to the difference in
【０００３】[0003]
【発明が解決しようとする課題】この従来の半導体集積
回路は、半導体ウェーハを割って評価するため、製品が
破壊されてしまうという問題点があった。また、エッチ
ングして外観を観察する作業であるため、電気的評価に
比較して時間がかかるという問題点があった。また半導
体ウェーハの面内の欠陥の分布を評価する事も困難であ
るという問題点があった。However, this conventional semiconductor integrated circuit has a problem in that the product is destroyed because the semiconductor wafer is divided and evaluated. In addition, since the work is performed to observe the external appearance by etching, there is a problem that it takes a longer time than the electrical evaluation. There is also a problem that it is difficult to evaluate the distribution of defects in the plane of the semiconductor wafer.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体集積回路
は、溝型メモリセルを有する半導体集積回路において、
半導体チップの周囲のスクライブ線領域上に設けた複数
の段差部と、前記段差部の各段の水平面に設けてリーク
電流の大小を検出するためのメモリセルと同等の拡散層
とを備えている。According to the present invention, there is provided a semiconductor integrated circuit having a groove type memory cell.
The semiconductor device includes a plurality of step portions provided on a scribe line region around a semiconductor chip, and a diffusion layer provided on a horizontal surface of each step of the step portion and equivalent to a memory cell for detecting a magnitude of a leak current. .
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００６】図１は、本発明の第１の実施例を示す半導
体チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
【０００７】図１に示すように、シリコン基板１の上面
に溝型メモリセル２を形成し、スクライブ線領域３に複
数の段差部を形成し、この段差部の水平面に溝型メモリ
部と同様の拡散層４を形成する。As shown in FIG. 1, a grooved memory cell 2 is formed on the upper surface of a silicon substrate 1, a plurality of steps are formed in a scribe line region 3, and a horizontal surface of the stepped portion is similar to the grooved memory section. Is formed.
【０００８】図２は本発明に使用するリーク電流検出回
路を示すブロック図である。FIG. 2 is a block diagram showing a leak current detecting circuit used in the present invention.
【０００９】図２に示すように、入力端子１３に印加さ
れた充電信号によりシリコン基板１と拡散層４との間の
拡散層容量１２を電源１５の電位に充電させる充電回路
１４と、節点１７に接続して拡散層容量１２の電位を検
出するＭＯＳトランジスタ１６を備えており、スクライ
ブ線領域に形成されている。ここで、入力端子１３の充
電信号により拡散層容量１２に充電された電位は拡散層
４に、結晶欠陥が存在すると基板へのリーク電流が増
え、節点７の充電電位は時間の経過と共に低下する。As shown in FIG. 2, a charging circuit 14 for charging the diffusion layer capacitance 12 between the silicon substrate 1 and the diffusion layer 4 to the potential of the power supply 15 by a charging signal applied to the input terminal 13, and a node 17 And a MOS transistor 16 for detecting the potential of the diffusion layer capacitor 12 connected to the scribe line region. Here, the potential charged in the diffusion layer capacitor 12 by the charge signal of the input terminal 13 increases the leakage current to the substrate when a crystal defect is present in the diffusion layer 4 and the charging potential of the node 7 decreases with time. .
【００１０】このため節点７に接続されたＭＯＳトラン
ジスタ１６の出力端子１８の電位も低下するため、この
電位変化をモニターする事で拡散層４のリーク電流の大
小を検出する事が出来る。As a result, the potential of the output terminal 18 of the MOS transistor 16 connected to the node 7 also decreases. By monitoring this potential change, the magnitude of the leakage current of the diffusion layer 4 can be detected.
【００１１】図３は本発明の第１の実施例を示すレイア
ウト図である。半導体チップ２０の周囲のスクライブ線
領域３に半導体チップ２０を囲む様に３つの段差領域
Ａ，Ｂ，Ｃを形成する。これらの領域に拡散層４および
欠陥チェック回路を形成する。拡散工程が完了して、こ
れらのチェック回路を試験する事により、内部欠陥析出
層がこれらの拡散層に到達しているかどうかが判定出来
る。溝メモリセルの深さと、これらの段差の比較より内
部欠陥析出層の位置が把握出来、溝メモリセル部への影
響の有無を判定する事が出来る。FIG. 3 is a layout diagram showing a first embodiment of the present invention. Three step regions A, B, and C are formed in the scribe line region 3 around the semiconductor chip 20 so as to surround the semiconductor chip 20. A diffusion layer 4 and a defect check circuit are formed in these regions. By testing these check circuits after the diffusion step is completed, it can be determined whether the internal defect deposition layer has reached these diffusion layers. By comparing the depth of the groove memory cell and these steps, the position of the internal defect deposition layer can be ascertained, and the presence or absence of an influence on the groove memory cell portion can be determined.
【００１２】図４は本発明の第２の実施例を示すレイア
ウト図である。スクライブ線領域上に、半導体チップ２
０の行方向，列方向及びコーナ部へ３つの段差領域Ａ，
Ｂ，Ｃを形成した以外は第１の実施例と同様の構成を有
しており、スクライブ線領域の幅全体を１つの段差とし
て形成することでこの平坦部に形成する拡散層を広範囲
に形成する事が出来る。このため、内部欠陥によるリー
ク電流の検出も比較的精度を向上させる事が出来る。FIG. 4 is a layout diagram showing a second embodiment of the present invention. The semiconductor chip 2 is placed on the scribe line area.
In the row direction, column direction and corner portion of 0, three step regions A,
It has the same configuration as that of the first embodiment except that B and C are formed. By forming the entire width of the scribe line region as one step, the diffusion layer formed on this flat portion is formed in a wide range. You can do it. For this reason, the accuracy of detecting a leak current due to an internal defect can be relatively improved.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、溝型メモ
リセルを有するダイナミックメモリにおいてスクライブ
線領域上に複数の段差を形成し、その平面部にメモリセ
ル部と同等の拡散層を形成することにより、これらのリ
ーク電流の大小を検出して内部欠陥析出層が溝型メモリ
セルに対してどの位置に存在しているかを把握する事が
出来、しかも半導体ウェーハを破壊する事無くかつ電気
的に試験可能であり効率的であるという効果を有する。As described above, according to the present invention, in a dynamic memory having a groove type memory cell, a plurality of steps are formed on a scribe line region, and a diffusion layer equivalent to the memory cell portion is formed on a plane portion thereof. By detecting the magnitude of these leak currents, it is possible to determine where the internal defect deposition layer is located with respect to the groove type memory cell, and furthermore, without breaking the semiconductor wafer and electrically. This has the effect of being testable and efficient.
【図１】本発明の第１の実施例を示す半導体チップの断
面図。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
【図２】本発明に使用するリーク電流検出回路を示すブ
ロック図。FIG. 2 is a block diagram showing a leakage current detection circuit used in the present invention.
【図３】本発明の第１の実施例を示すレイアウト図。FIG. 3 is a layout diagram showing a first embodiment of the present invention.
【図４】本発明の第２の実施例を示すレイアウト図。FIG. 4 is a layout diagram showing a second embodiment of the present invention.
１ シリコン基板 ２ 溝型メモリセル ３ スクライブ線領域 ４ 拡散層 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Groove type memory cell 3 Scribe line area 4 Diffusion layer
Claims (1)
において、半導体チップの周囲のスクライブ線領域上に
設けた複数の段差部と、前記段差部の各段の水平面に設
けてリーク電流の大小を検出するためのメモリセルと同
等の拡散層とを備えたことを特徴とする半導体集積回
路。In a semiconductor integrated circuit having a groove type memory cell, a plurality of steps provided on a scribe line area around a semiconductor chip and a level difference of a leak current are provided on a horizontal plane of each step of the step. A semiconductor integrated circuit comprising: a memory cell for detection; and a diffusion layer equivalent to a memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3144320A JP2943399B2 (en) | 1991-06-17 | 1991-06-17 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3144320A JP2943399B2 (en) | 1991-06-17 | 1991-06-17 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04368147A JPH04368147A (en) | 1992-12-21 |
| JP2943399B2 true JP2943399B2 (en) | 1999-08-30 |
Family
ID=15359353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3144320A Expired - Fee Related JP2943399B2 (en) | 1991-06-17 | 1991-06-17 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2943399B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451489B1 (en) * | 1996-12-28 | 2004-12-03 | 주식회사 하이닉스반도체 | Test pattern of semiconductor device and forming method thereof to precisely measure junction leakage current of storage node electrode and substrate |
| JP4308691B2 (en) | 2004-03-19 | 2009-08-05 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor substrate and method for manufacturing semiconductor substrate |
-
1991
- 1991-06-17 JP JP3144320A patent/JP2943399B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04368147A (en) | 1992-12-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990525 |
|
| LAPS | Cancellation because of no payment of annual fees |