JP2939402B2 - Semiconductor stack - Google Patents
Semiconductor stackInfo
- Publication number
- JP2939402B2 JP2939402B2 JP3662193A JP3662193A JP2939402B2 JP 2939402 B2 JP2939402 B2 JP 2939402B2 JP 3662193 A JP3662193 A JP 3662193A JP 3662193 A JP3662193 A JP 3662193A JP 2939402 B2 JP2939402 B2 JP 2939402B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- heat sink
- switching elements
- switching
- semiconductor stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Thyristors (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電力変換器の半導体素
子を組込み、冷却を行うスタックに係り、特に複数個の
スイッチング素子間の接続構成を改良した半導体スタッ
クに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack for incorporating a semiconductor element of a power converter and performing cooling, and more particularly to a semiconductor stack having an improved connection between a plurality of switching elements.
【０００２】[0002]
【従来の技術】半導体装置においては、電力変換器の高
性能のため高速スイッチング素子を用いた高周波ＰＷＭ
制御方式の採用が増加し、また、半導体装置の大容量化
に伴い、大容量の半導体素子を複数個並列して用いるよ
うにしている。スイッチング素子は、実装の容易さから
モジュール型素子が多く適用されるようになり、また、
装置の小形化を図るため、スタックを高密度実装化すべ
く冷却フィンの両面にスイッチング素子を実装する構成
が採用されるようになってきた。2. Description of the Related Art In a semiconductor device, a high-frequency PWM using a high-speed switching element is used for high performance of a power converter.
As the adoption of the control method increases and the capacity of the semiconductor device increases, a plurality of large-capacity semiconductor elements are used in parallel. As switching elements, many modular elements are applied because of ease of mounting, and
In order to reduce the size of the device, a configuration has been adopted in which switching elements are mounted on both sides of the cooling fins in order to increase the stack density.
【０００３】次に、従来の実装例を図５〜図７を参照し
て説明する。図５は、単相や三相ブリッジ回路に用いら
れる１ブリッジの回路図を示したもので、直流Ｐ，Ｎ間
の上下の２アームで構成されている。また、それぞれの
アームのスイッチング素子１，２は、４並列の場合を示
す。図６，図７は、図５に示す回路を実装した構成を示
し、図６はその正面図、図７は図６のＡ−Ａ矢視図であ
る。Next, a conventional mounting example will be described with reference to FIGS. FIG. 5 is a circuit diagram of one bridge used in a single-phase or three-phase bridge circuit, and is composed of two upper and lower arms between DC P and N. Also, the switching elements 1 and 2 of each arm are shown in a case of four parallel. 6 and 7 show a configuration in which the circuit shown in FIG. 5 is mounted, FIG. 6 is a front view thereof, and FIG. 7 is a view taken along line AA of FIG.
【０００４】図６および図７において、スタックは、ヒ
ートシンク６に対して一側面に２アームの２個並列分の
スイッチング素子１，２が配置され、他側面にも図示し
ないが同様に２アーム分の４個のスイッチング素子が配
置され、直流導体（Ｐ）３，直流導体（Ｎ）４と上下ア
ーム間を接続する交流導体５により、スイッチング素子
１，２が４個並列に接続されている。この直流導体
（Ｐ）３，直流導体（Ｎ）４，交流導体５は、ヒートシ
ンク６の前面と背面間を交流端子８，直流入力端子
（Ｐ）９，直流入力端子（Ｎ）10を介して接続されてい
る。[0006] In FIGS. 6 and 7, two stacks of two switching elements 1 and 2 are arranged on one side of a heat sink 6, and the other side is also shown in FIG. And four switching elements 1 and 2 are connected in parallel by a DC conductor (P) 3 and a DC conductor (N) 4 and an AC conductor 5 connecting the upper and lower arms. The DC conductor (P) 3, the DC conductor (N) 4, and the AC conductor 5 are connected between the front and back surfaces of the heat sink 6 via an AC terminal 8, a DC input terminal (P) 9, and a DC input terminal (N) 10. It is connected.
【０００５】また、11はゲート駆動基板を示し、スイッ
チング素子１，２のベース端子Ｂにゲート抵抗13を介し
てゲート駆動基板11上のコネクタ12により、ゲート信号
Ｇ1，Ｇ2 を供給する。ゲート抵抗13を介して供給する
ゲート信号Ｇ1 ，Ｇ2 は、各アームのスイッチング素子
１，２が複数個並列接続であっても共通の信号でよい。Reference numeral 11 denotes a gate drive board, which supplies gate signals G 1 and G 2 to base terminals B of the switching elements 1 and 2 via a gate resistor 13 and a connector 12 on the gate drive board 11. The gate signals G 1 and G 2 supplied via the gate resistor 13 may be a common signal even if a plurality of switching elements 1 and 2 of each arm are connected in parallel.
【０００６】以上説明したようにヒートシンク６の表面
および裏面の両側にスイッチング素子１，２を実装した
場合、ヒートシンク６の上下または前後等の空間を通じ
てゲート信号用の電線を配線することになる。As described above, when the switching elements 1 and 2 are mounted on both sides of the front and back surfaces of the heat sink 6, an electric wire for a gate signal is routed through a space such as above and below or before and after the heat sink 6.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このよ
うにゲート信号線をヒートシンク６の表裏面間を配線す
る場合、近傍に直流導体（Ｐ）３，直流導体（Ｎ）４，
交流導体５等の主回路電流を流す導体が配設されてお
り、スイッチング素子１，２は大電流を高周波，高速で
スイッチングしているので、ゲート信号Ｇ1 ，Ｇ2 が主
回路の影響を受けて半導体装置の所望の動作が困難にな
るという問題があった。However, when the gate signal line is wired between the front and back surfaces of the heat sink 6, the DC conductor (P) 3, DC conductor (N) 4,
Since a conductor such as an AC conductor 5 for flowing a main circuit current is provided, and the switching elements 1 and 2 switch a large current at a high frequency and a high speed, the gate signals G 1 and G 2 influence the main circuit. As a result, there has been a problem that a desired operation of the semiconductor device becomes difficult.
【０００８】また、特にゲート信号については、ゲート
信号線と直流導体（Ｐ）３や直流導体（Ｎ）４が平行し
て配線されると、主回路電流により発生する磁束の影響
で、ゲート信号Ｇ1 ，Ｇ2 のＯＮ，ＯＦＦ時の立上が
り，立下りに影響を受け、主回路スイッチング素子１，
２の正側，負側およびヒートシンク６の表面，裏面のス
イッチング時間に“ばらつき”を生じ、スイッチング時
のサージ電圧やスイッチング時に発生するスイッチング
損失が実装構成により変化してくる。In particular, regarding the gate signal, if the gate signal line and the DC conductor (P) 3 or the DC conductor (N) 4 are wired in parallel, the gate signal is affected by the magnetic flux generated by the main circuit current. G 1 , G 2 are affected by the rise and fall when ON and OFF, and the main circuit switching elements 1 and 2 are affected.
The switching time of the positive side and the negative side of 2 and the switching time of the front and back surfaces of the heat sink 6 causes "variation", and the surge voltage at the time of switching and the switching loss generated at the time of switching vary depending on the mounting configuration.
【０００９】このため、装置を大容量化すべくスイッチ
ング素子を並列接続しているにも拘らず、取得可能な容
量は、１並列の設計容量当りの取得容量に並列個数を乗
じたものではなく、スイッチングサージ電圧，発生熱量
等で最も実装条件の悪いスイッチング素子で決まる容量
に低減して持ちなければならなかった。For this reason, despite the fact that the switching elements are connected in parallel in order to increase the capacity of the device, the obtainable capacity is not the product of the obtained capacity per one parallel design capacity multiplied by the number in parallel. It had to be reduced to the capacity determined by the switching element with the worst mounting conditions due to switching surge voltage, generated heat, etc.
【００１０】そこで、本発明の目的は、ヒートシンクの
側面に実装されたスイッチング素子等の電気部品間の配
線経路を短縮すると共に主回路からの影響を受け難くし
て信頼性を向上し、配線処理も容易とした半導体スタッ
クを提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to shorten the wiring path between electrical components such as switching elements mounted on the side surface of a heat sink, to reduce the influence of the main circuit, to improve reliability, and to improve the wiring processing. Another object of the present invention is to provide a semiconductor stack which is also easy.
【００１１】[0011]
【課題を解決するための手段】本発明は、上記目的を達
成するため、中間に空隙を形成した放熱体の側部に半導
体素子を含む電気部品を装着し、この電気部品に接続す
る電線の配線処理スペースを放熱体の上部または下部に
配置し、かつ放熱体に一体で配線するように構成したも
のである。According to the present invention, an electric component including a semiconductor element is mounted on a side of a heat radiator having an air gap therebetween, and an electric wire connected to the electric component is provided. The wiring processing space is arranged above or below the radiator, and is configured so as to be integrated with the radiator.
【００１２】[0012]
【作用】半導体素子を含む電気部品間の配線経路が短縮
されると共に主回路からの影響が受け難くなり、配線経
路が固定化されて配線処理が容易になる。The wiring path between the electric components including the semiconductor element is shortened, the influence of the main circuit is reduced, the wiring path is fixed, and the wiring processing is facilitated.
【００１３】[0013]
【実施例】以下、発明の実施例を図面を参照して説明す
る。図１は、本発明の一実施例を一部切断して示す斜視
図、図２は、本発明の一実施例に用いるヒートシンクの
斜視図、図３は、本発明の一実施例の回路図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing a part of an embodiment of the present invention, FIG. 2 is a perspective view of a heat sink used in the embodiment of the present invention, and FIG. 3 is a circuit diagram of the embodiment of the present invention. It is.
【００１４】図１において、１，２はスイッチング素
子、16はこのスイッチング素子１，２を取付けるヒート
シンクを示す。このヒートシンク16は、図３に示すよう
に熱伝導性の良好な銅またはアルミニウム等の材料から
形成され、両側の縁部を厚くし中間部を薄くした板状の
単体16ａを、所要数重ねて縁部をボルト16ｂで締付けて
一体にしたもので、単体16ａ相互の中間部に形成される
隙間16ｃに冷却風を流通させて放熱できるように構成さ
れている。In FIG. 1, reference numerals 1 and 2 denote switching elements, and reference numeral 16 denotes a heat sink on which the switching elements 1 and 2 are mounted. As shown in FIG. 3, the heat sink 16 is made of a material having good thermal conductivity, such as copper or aluminum. The edges are integrally tightened with bolts 16b, and are configured so that cooling air can flow through a gap 16c formed at an intermediate portion between the single bodies 16a to radiate heat.
【００１５】このように構成されたヒートシンク16の側
面部に、長手方向に沿ってスイッチング素子１，２を配
列し、ボルト（図示しない）を介して取付ける。なお、
図１には、スイッチング素子１，２がヒートシンク16の
一方（右側）の側面部に取付けられている状態を示して
いるが、他方（左側）の側面部にも同様にスイッチング
素子１，２（ただし、図示しない）が取付けられ、全体
として図２に示す回路図の直流Ｐ，Ｎ間上下アームの２
並列が取付けられる。The switching elements 1 and 2 are arranged along the longitudinal direction on the side surface of the heat sink 16 configured as described above, and are mounted via bolts (not shown). In addition,
FIG. 1 shows a state in which the switching elements 1 and 2 are attached to one (right) side of the heat sink 16, but the switching elements 1 and 2 ( However, not shown) is attached, and as a whole, two of the upper and lower arms between DC P and N in the circuit diagram shown in FIG.
Parallel is installed.
【００１６】スイッチング素子１のＣ端子には直流導体
（Ｐ）17が接続され、スイッチング素子２のＥ端子には
直流導体（Ｎ）18が接続され、スイッチング素子１，２
のＥ，Ｃ端子には交流導体19が接続されている。ここ
で、直流導体（Ｐ）17，直流導体（Ｎ）18，交流導体19
は、平面で見た形状を水平部と垂直部で形成した⊥状と
している。この水平部の両端を下方に折曲げてスイッチ
ング素子１，２への接続部とし、垂直部はヒートシンク
16の上面に取付けた絶縁支持体20の内部に収納し、直流
導体（Ｐ）17の端部には図２に示す直流入力端子（Ｐ）
９、直流入力端子（Ｎ）10，交流端子11を形成する。な
お、直流導体（Ｐ）17と直流導体（Ｎ）18は、交流導体
19を上下から挟むように配置される。A DC conductor (P) 17 is connected to the C terminal of the switching element 1, a DC conductor (N) 18 is connected to the E terminal of the switching element 2, and the switching elements 1 and 2 are connected.
The AC conductor 19 is connected to the E and C terminals. Here, DC conductor (P) 17, DC conductor (N) 18, AC conductor 19
Has a rectangular shape formed by a horizontal portion and a vertical portion in a plan view. Both ends of this horizontal portion are bent downward to connect to the switching elements 1 and 2, and the vertical portion is a heat sink.
The DC input terminal (P) shown in FIG. 2 is housed inside the insulating support 20 attached to the upper surface of
9. A DC input terminal (N) 10 and an AC terminal 11 are formed. The DC conductor (P) 17 and DC conductor (N) 18 are AC conductors.
It is arranged so as to sandwich 19 from above and below.
【００１７】ヒートシンク16の下部にはゲート駆動基板
11Ａが取付けられ、ヒートシンク16の上部には絶縁支持
体20を介して中継基板21が取付けられる。ゲート駆動基
板11Ａは、従来と同様な構成としたゲート駆動基板の基
板をヒートシンク16の各側面より突出させる構成とし、
それぞれの突出部11ａにコネクタ12，12を取付ける。ま
た、中継基板21は、ゲート信号Ｇ1 ，Ｇ2 を中継するた
めの中継基板で、ヒートシンク16の各側面側にそれぞれ
コネクタ15，15を取付ける。右側面と左側面のスイッチ
ング素子１，２間のゲート信号は、この中継基板21のコ
ネクタ15と基板上のパターンを介して接続される。な
お、中継基板21の上部には、カバー22を取付け、中継基
板21を保護する。A gate drive substrate is provided below the heat sink 16.
11A is mounted, and a relay board 21 is mounted on the heat sink 16 with an insulating support 20 interposed therebetween. The gate drive substrate 11A has a configuration in which the substrate of the gate drive substrate having the same configuration as the conventional one is protruded from each side surface of the heat sink 16,
The connectors 12, 12 are mounted on the respective protruding portions 11a. The relay board 21 is a relay board for relaying the gate signals G 1 and G 2, and the connectors 15 and 15 are attached to the respective side surfaces of the heat sink 16. Gate signals between the switching elements 1 and 2 on the right and left sides are connected to the connector 15 of the relay board 21 via a pattern on the board. Note that a cover 22 is attached to the upper part of the relay board 21 to protect the relay board 21.
【００１８】一方、ヒートシンク16の各側面には電線支
持台23，23を取付ける。この電線支持台23は、絶縁材か
ら形成され、ゲート駆動基板11Ａに取付けたコネクタ12
と中継基板21に取付けたコネクタ15を接続する電線やゲ
ート抵抗13を支持する。On the other hand, electric wire supports 23, 23 are attached to each side surface of the heat sink 16. The wire support 23 is formed of an insulating material, and is connected to the connector 12 mounted on the gate drive board 11A.
And a wire connecting the connector 15 attached to the relay board 21 and the gate resistor 13.
【００１９】次に、以上のように構成された実施例の作
用を説明する。上述したようにスイッチング素子１，２
をヒートシンク16の両側面に実装し、スイッチング素子
１，２間の配線を実質的にヒートシンク16に一体構成さ
れた中継基板21を介して施すことにより、配線経路を固
定でき、基板のパターン，シールド処理等によりゲート
信号Ｇ1 ，Ｇ2 が主回路電流を流す直流導体（Ｐ）17，
直流導体（Ｎ）18，交流導体19からの電磁誘導の影響を
受けることを防止し、装置の信頼性を向上することがで
きる。Next, the operation of the embodiment configured as described above will be described. As described above, the switching elements 1 and 2
Are mounted on both sides of the heat sink 16, and the wiring between the switching elements 1 and 2 is substantially provided through the relay board 21 integrally formed on the heat sink 16, so that the wiring path can be fixed. DC conductors (P) 17, through which the gate signals G 1 and G 2 pass the main circuit current by processing, etc.
The influence of electromagnetic induction from the DC conductor (N) 18 and the AC conductor 19 can be prevented, and the reliability of the device can be improved.
【００２０】以上のように構成することにより、ヒート
シンクの両側面に実装したスイッチング素子間のゲート
信号の配線を、ヒートシンクと一体化した中継基板を介
して施すので、主回路からゲート信号が電磁誘導を受け
ることがなく、実装密度を高くし小形で信頼性を向上し
た半導体スタックが得られる。With the above configuration, the wiring of the gate signal between the switching elements mounted on both side surfaces of the heat sink is provided via the relay board integrated with the heat sink, so that the gate signal is transmitted from the main circuit by electromagnetic induction. A semiconductor stack with high mounting density, small size, and improved reliability can be obtained without receiving such problems.
【００２１】なお、本発明は、上述した実施例に限定さ
れるものでなく、種々変形実施できる。図４は、上述し
た実施例のブリッジ回路を２段積重ねた単相ブリッジ回
路の実施例を一部切断して示す斜視図である。この実施
例の場合、ゲート駆動基板11Ａには、それぞれの突出部
11ａにコネクタ12を４個取付ける。また、下方のスタッ
クの直流導体（Ｐ）17Ａと上方のスタックの直流導体
（Ｐ）17Ｂの直流入力端子（Ｐ）をそれぞれ接近するよ
うに伸ばし、この接続部に直流入力端子（Ｐ）９を形成
し、下方のスタックの直流導体（Ｎ）18Ａと上方のスタ
ックの直流導体（Ｎ）18Ｂの直流入力端子（Ｎ）をそれ
ぞれ接近するように伸ばし、この接続部に直流入力端子
（Ｎ）10を形成し、下方のスタックの交流導体19Ａと上
方のスタックの交流導体19Ｂの交流端子をそれぞれ接近
するように伸ばし、この接続部に交流端子11を形成す
る。The present invention is not limited to the above-described embodiment, but can be variously modified. FIG. 4 is a perspective view showing a partially cut embodiment of a single-phase bridge circuit in which the bridge circuits of the above-described embodiment are stacked in two stages. In the case of this embodiment, each protrusion is provided on the gate drive substrate 11A.
Attach four connectors 12 to 11a. Further, the DC input terminals (P) of the lower stack DC conductor (P) 17A and the upper stack DC conductor (P) 17B are extended so as to approach each other, and the DC input terminal (P) 9 is connected to this connection part. The DC input terminals (N) of the DC conductor (N) 18A of the lower stack and the DC conductor (N) 18B of the upper stack are extended so as to approach each other. The AC terminals of the AC conductor 19A of the lower stack and the AC conductor 19B of the upper stack are extended so as to approach each other, and the AC terminal 11 is formed at this connection portion.
【００２２】このように構成することにより、２つのヒ
ートシンク16を、絶縁支持体20，中継基板21，カバー22
等を介して一体構成とし実装することができ、ヒートシ
ンク16が増加しても常に主回路導体とゲート信号線の配
線関係を各相同等とすることができる。この実施例は、
ヒートシンク16の両側面に合わせて２並列分実装した例
であるが、ヒートシンク16の一側面当りのスイッチング
素子１，２の実装数を変えることにより、任意並列数を
実装できることはいうまでもない。With this configuration, the two heat sinks 16 are separated from each other by the insulating support 20, the relay board 21, and the cover 22.
And the like, and can be mounted in an integrated manner, so that even when the number of heat sinks 16 increases, the wiring relationship between the main circuit conductor and the gate signal line can always be made the same or the like. This example is
In this example, two parallel mountings are provided in accordance with both side surfaces of the heat sink 16. However, it is needless to say that an arbitrary number of parallel mountings can be achieved by changing the mounting number of the switching elements 1 and 2 per one side surface of the heat sink 16.
【００２３】また、以上の各実施例は、ゲート信号を例
にとって説明したが、ブリッジ回路にはゲート信号以外
にも、スイッチング素子のスイッチングサージを吸収す
るスナバ回路、スイッチング素子の保護のためにコレク
ター・エミッタ間の電圧を検出する電線等種々の接続が
考えられるが、何れに対してもヒートシンクと一体構成
にした中継基板を介して接続することが可能である。さ
らに、ヒートシンク間に中継基板を実装した構成を適用
して、ヒートシンク間の空間を利用してケーブル等の配
線もできることはいうまでもない。さらに、半導体スタ
ックの容量等に応じてヒートシンクに図４に矢印で示す
ように冷却風を流すことにより、スイッチング素子等を
効果的に冷却することができる。In each of the embodiments described above, the gate signal is used as an example. However, in addition to the gate signal, the bridge circuit includes a snubber circuit for absorbing switching surge of the switching element, and a collector for protecting the switching element. Various connections such as an electric wire for detecting the voltage between the emitters are conceivable, but any of them can be connected via a relay board integrated with the heat sink. Furthermore, it goes without saying that a configuration in which a relay board is mounted between heat sinks is applied, and wiring such as cables can be performed by utilizing the space between the heat sinks. Further, the switching element and the like can be effectively cooled by flowing cooling air through the heat sink according to the capacity and the like of the semiconductor stack as shown by an arrow in FIG.
【００２４】[0024]
【発明の効果】以上説明したように本発明によれば、中
間に空隙を形成した放熱体の側部に半導体素子を含む電
気部品を装着し、この電気部品に接続する電線の配線処
理スペースを放熱体の上部または下部に配置し、かつ放
熱体に一体で配線するようにしているので、配線短絡が
短縮され主回路からの影響を受け難くして信頼性を向上
し、配線処理も容易とした半導体スタックを提供するこ
とができる。As described above, according to the present invention, an electric component including a semiconductor element is mounted on the side of a heat radiator having an air gap in the middle, and a wiring processing space for electric wires connected to this electric component is reduced. Since it is located above or below the radiator and wired integrally with the radiator, wiring short-circuits are reduced, making it less susceptible to the main circuit, improving reliability, and simplifying wiring processing. Semiconductor stack can be provided.
【図１】本発明の一実施例を一部切断して示す斜視図。FIG. 1 is a perspective view showing an embodiment of the present invention by partially cutting it out.
【図２】本発明の一実施例に用いるヒートシンクを示す
斜視図。FIG. 2 is a perspective view showing a heat sink used in one embodiment of the present invention.
【図３】本発明の一実施例の回路図。FIG. 3 is a circuit diagram of one embodiment of the present invention.
【図４】本発明の他の実施例を一部切断して示す斜視
図。FIG. 4 is a perspective view partially cut away showing another embodiment of the present invention.
【図５】従来の半導体スタックの回路図。FIG. 5 is a circuit diagram of a conventional semiconductor stack.
【図６】従来の半導体スタックの正面図。FIG. 6 is a front view of a conventional semiconductor stack.
【図７】図６のＡ−Ａ矢視図。FIG. 7 is a view taken in the direction of arrows AA in FIG. 6;
１，２…スイッチング素子、９…直流入力端子（Ｐ）、
10…直流入力端子（Ｎ）、11…交流端子、11Ａ…ゲート
駆動基板、12，15…コネクタ、16…ヒートシンク、17，
17Ａ，17Ｂ…直流導体（Ｐ）、18，18Ａ，18Ｂ…直流導
体（Ｎ）、19，19Ａ，19Ｂ…交流導体、20…絶縁支持
体、21…中継基板、22…カバー。1, 2, switching element, 9 DC input terminal (P),
10: DC input terminal (N), 11: AC terminal, 11A: Gate drive board, 12, 15: Connector, 16: Heat sink, 17,
17A, 17B: DC conductor (P), 18, 18A, 18B: DC conductor (N), 19, 19A, 19B: AC conductor, 20: insulating support, 21: relay board, 22: cover.
Claims (3)
導体素子を含む電気部品を装着し、この電気部品に接続
する電線の配線処理スペースを前記放熱体の上部または
下部に配置し、かつ前記放熱体に一体で配線するように
したことを特徴とする半導体スタック。1. An electric component including a semiconductor element is mounted on a side of a heat radiator having a gap formed in the middle, and a wiring processing space for an electric wire connected to the electric component is disposed above or below the heat radiator. A semiconductor stack, wherein wiring is formed integrally with the radiator.
て、電気部品に接続する機能を有する基板を、配線処理
スペースに配置すると共に放熱体に一体に装着したこと
を特徴とする半導体スタック。2. The semiconductor stack according to claim 1, wherein a substrate having a function of connecting to an electric component is arranged in a wiring processing space and is integrally mounted on a heat radiator.
において、放熱体の空隙に冷却風を流通させるようにし
たことを特徴とする半導体スタック。3. The semiconductor stack according to claim 1, wherein cooling air is circulated in a gap of the heat radiator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3662193A JP2939402B2 (en) | 1993-02-25 | 1993-02-25 | Semiconductor stack |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3662193A JP2939402B2 (en) | 1993-02-25 | 1993-02-25 | Semiconductor stack |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06252343A JPH06252343A (en) | 1994-09-09 |
| JP2939402B2 true JP2939402B2 (en) | 1999-08-25 |
Family
ID=12474883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3662193A Expired - Fee Related JP2939402B2 (en) | 1993-02-25 | 1993-02-25 | Semiconductor stack |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2939402B2 (en) |
-
1993
- 1993-02-25 JP JP3662193A patent/JP2939402B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06252343A (en) | 1994-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6101114A (en) | Power conversion system having multi-chip packages | |
| US10153708B2 (en) | Three-level power converter | |
| US5907475A (en) | Circuit board system having a mounted board and a plurality of mounting boards | |
| US4905123A (en) | Heat sink bus assembly | |
| JP3300566B2 (en) | Power module and power converter | |
| JP2006148098A (en) | Power module, phase-leg power module assembly, and three-phase inverter assembly | |
| JP4220731B2 (en) | Power semiconductor device | |
| JPH06261556A (en) | Semiconductor switch apparatus | |
| JP4839096B2 (en) | Power converter | |
| JP2001274322A (en) | Power semiconductor module | |
| JP2000133768A (en) | Semiconductor power module | |
| JP2005252305A (en) | Semiconductor device for electric power | |
| JPH07170723A (en) | Semiconductor stack | |
| CN111316767B (en) | Circuit arrangement | |
| JPH1118429A (en) | Control module | |
| JP2003018860A (en) | Power converter | |
| CN113632364B (en) | Power conversion unit | |
| JP3220366B2 (en) | Semiconductor device | |
| JP2939402B2 (en) | Semiconductor stack | |
| JP4878424B2 (en) | Power converter | |
| JP3085453B2 (en) | Semiconductor module and inverter device using the same | |
| JP2002125381A (en) | Power converter | |
| JP2004063681A (en) | Semiconductor device | |
| JP3051003B2 (en) | Semiconductor stack | |
| JPH02174564A (en) | Main circuitry for inverter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080611 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080611 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090611 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100611 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20100611 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 12 Free format text: PAYMENT UNTIL: 20110611 |
|
| LAPS | Cancellation because of no payment of annual fees |