JP2910802B2 - Inspection method for semiconductor device - Google Patents
Inspection method for semiconductor deviceInfo
- Publication number
- JP2910802B2 JP2910802B2 JP3336547A JP33654791A JP2910802B2 JP 2910802 B2 JP2910802 B2 JP 2910802B2 JP 3336547 A JP3336547 A JP 3336547A JP 33654791 A JP33654791 A JP 33654791A JP 2910802 B2 JP2910802 B2 JP 2910802B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- burn
- diameter
- test
- inspection method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の検査方法
に関し、さらに詳しくは、形状記憶合金コンタクト部に
より加熱することで導通をとる検査方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor device, and more particularly, to an inspection method for establishing conduction by heating a semiconductor device with a shape memory alloy contact portion.
【０００２】[0002]
【従来の技術】従来の半導体装置の製造工程は、図３の
様に拡散工程の終了したＳｉウェハーは、ウェハー状態
のままで特性検査を実施し、良品・不良品の選別を行い
マーキングを行う。この後、ウェハーを個片のチップと
するためダイシングを行い、良品のみを、リードフレー
ムにダイボンディングおよびワイヤーボンディングを行
う。この後プラスチックで封止し、リードをカットベン
ディングする。この後、ＤＣ特性の検査で良品のみを、
高温（７５〜１５０℃）・高印加電圧（５〜８Ｖ）で数
時間加速動作させ、プロセスでの潜在不良品を除去する
為の負荷をかける。これをバーンインテストとよぶ。こ
の後、ＤＣ・ＡＣ検査を行い、マーキングすることで半
導体装置が完成する。しかしながら、最近、製品の小型
・薄型化の為に半導体装置をプラスチックで封止した形
でなく、Ｓｉチップの状態で、図４のようにプリント基
板等に実装されるケースが増加してきた。2. Description of the Related Art In a conventional semiconductor device manufacturing process, as shown in FIG. 3, a Si wafer having undergone a diffusion process is subjected to a characteristic inspection in a wafer state, and a non-defective / defective product is selected for marking. . Thereafter, dicing is performed to make the wafer into individual chips, and only non-defective products are subjected to die bonding and wire bonding to a lead frame. Thereafter, the package is sealed with plastic, and the lead is cut and bent. After that, only non-defective products are inspected by DC characteristics inspection.
The accelerating operation is performed for several hours at a high temperature (75 to 150 ° C.) and a high applied voltage (5 to 8 V), and a load for removing a latent defective in the process is applied. This is called a burn-in test. Thereafter, a DC / AC inspection is performed and marking is performed to complete the semiconductor device. However, recently, in order to reduce the size and thickness of the product, the number of cases where the semiconductor device is mounted on a printed circuit board or the like as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】Ｓｉチップの状態で
は、バーンインテストを実施する手段がなく、プリント
基板に実装後テストを行う為、潜在不良品もプリント基
板に実装されてしまう。例えば同一の半導体装置を２０
個実装する時、潜在不良率を１％とすると、製品の良品
率は（１−０．０１）20＝８２％となり、歩留りが非常
に低下し、製品のコストアップ又はベアチップの採用が
不可能となるという欠点があった。In the state of a Si chip, there is no means for performing a burn-in test, and a test is performed after mounting on a printed circuit board. Therefore, a latent defective product is also mounted on the printed circuit board. For example, 20 identical semiconductor devices
At the time of individual mounting, assuming that the latent defect rate is 1%, the non-defective rate of the product is (1-0.01) 20 = 82%, the yield is extremely reduced, and it is impossible to increase the cost of the product or adopt bare chips. There was a disadvantage that it becomes.
【０００４】この発明は、このような従来技術がもって
いた、小型・薄型化の為、ベアチップを使用する時、バ
ーンインテストが出来ない為、歩留りが低下し、コスト
アップするという欠点を解消して、ベアチップでバーン
インテストが可能で高歩留りで小型・薄型製品を提供す
ることを目的とする。The present invention solves the drawbacks of the prior art in that a bare chip cannot be used to perform a burn-in test for the purpose of miniaturization and thinning, thereby reducing the yield and increasing the cost. It is an object of the present invention to provide a small and thin product with a high yield, capable of performing a burn-in test with bare chips.
【０００５】[0005]
【課題を解決するための手段】このような目的を達成す
るための本発明の検査方法は、常温状態でソケットコン
タクト部の開孔部に対して、ベアチップ状態の半導体装
置の外部電極上に設けられた突起状の外部電極を入れ、
前記ソケットコンタクト部およびベアの半導体装置をバ
ーンイン炉にて加熱してバーンインテストする半導体装
置の検査方法であって、前記突起状の外部電極をソケッ
トコンタクト部の開孔部に入れる際は開孔部の径は前記
突起状の外部電極の径より大きく、バーンインテストの
加熱により前記開孔部の径が徐々に小さくなって前記突
起状の外部電極と電気的に導通してバーンインテストす
るものである。 In order to achieve the above object, the inspection method of the present invention provides a socket control at room temperature.
Insert the bare chip semiconductor device into the opening of the tact
Put the protruding external electrode provided on the external electrode of
The socket contact portion and the bare semiconductor device are
Semiconductor equipment for burn-in test by heating in burn-in furnace
A method of inspecting a location, wherein the protruding external electrodes are socketed.
The diameter of the hole when inserting into the hole of the contact
Larger than the diameter of the protruding external electrode
The diameter of the opening gradually decreases due to heating, and
The burn-in test is performed by electrically connecting to the raised external electrodes.
Things.
【０００６】[0006]
【作用】半導体装置と検査装置との電気的導通を、コン
タクト部の加熱、冷却によりオン、オフすることが可能
となる。The electrical conduction between the semiconductor device and the inspection device can be turned on and off by heating and cooling the contact portion.
【０００７】[0007]
【実施例】以下、本発明の一実施例について図面を参照
して説明を行う。An embodiment of the present invention will be described below with reference to the drawings.
【０００８】図１は、この発明による検査方法の一実施
例を示す断面図で、図２は、その斜視図である。FIG. 1 is a sectional view showing an embodiment of the inspection method according to the present invention, and FIG. 2 is a perspective view thereof.
【０００９】図１において、半導体装置１の外部電極上
に、メッキ、蒸着、ワイヤボンディング等の方法を用い
て、高さ１０〜７０μｍ程度の突起物２を設ける。突起
物の材質としては、Ａｕ、Ｃｕが望ましい。次にＮｉ−
Ｔｉ合金を用いて、中央に開孔部４を持つ、ソケットを
作製する。常温においては、開孔部４の径は、突起電極
の径より１０〜５０μｍ程度大きくなるようにしておく
（図１（Ａ））。次に、ソケット上に半導体装置１を逆
さにして、開孔部の中に突起電極が入るようにする。こ
の後、ソケット全体を７５〜１５０℃程度の炉の中に入
れると、開孔部の径が小さくなり、突起電極と電気的導
通がとれる。この状態で、炉の外部より各端子に信号を
送り、半導体装置を動作させる。所定の時間（２〜４８
ｈ）が経過後、ソケット全体を炉より取出し、常温まで
温度が低下すると開孔部の径が大きくなり、半導体装置
をソケットより取り出す（図１（Ｂ））。この後、ＤＣ
・ＡＣテストを実施して、潜在不良品を除去する。残っ
た良品をプリント基板等に実装すると歩留りの高い製品
が完成する。In FIG. 1, a projection 2 having a height of about 10 to 70 μm is provided on an external electrode of a semiconductor device 1 by using a method such as plating, vapor deposition, or wire bonding. Au and Cu are desirable as the material of the projection. Next, Ni-
Using a Ti alloy, a socket having an opening 4 in the center is produced. At room temperature, the diameter of the opening 4 is set to be about 10 to 50 μm larger than the diameter of the protruding electrode (FIG. 1A). Next, the semiconductor device 1 is turned upside down on the socket so that the protruding electrode enters the opening. Thereafter, when the entire socket is placed in a furnace at about 75 to 150 ° C., the diameter of the opening becomes small, and electrical connection with the protruding electrode can be obtained. In this state, a signal is sent from the outside of the furnace to each terminal to operate the semiconductor device. Predetermined time (2-48
After e), the entire socket is taken out of the furnace, and when the temperature drops to room temperature, the diameter of the opening increases, and the semiconductor device is taken out of the socket (FIG. 1B). After this, DC
-Perform an AC test to remove potential defective products. When the remaining good products are mounted on a printed circuit board or the like, a product with a high yield is completed.
【００１０】[0010]
【発明の効果】以上説明したように、本発明では、突起
電極のついたベアの半導体装置をバーンインテストを行
って、潜在不良品を除去できるので、製品の小型・薄型
化が高歩留りで実現でき、そのコストも大幅に低下し
た。As described above, according to the present invention, a bare semiconductor device having a protruding electrode can be subjected to a burn-in test to remove a potential defective product, so that the product can be reduced in size and thickness with a high yield. Yes, and its cost has dropped significantly.
【図１】本発明による検査方法の一実施例を示す断面図FIG. 1 is a sectional view showing an embodiment of an inspection method according to the present invention.
【図２】本発明による検査方法のソケットの一実施例を
示す斜視図FIG. 2 is a perspective view showing one embodiment of a socket of the inspection method according to the present invention.
【図３】従来技術による半導体装置の製造フロー図FIG. 3 is a manufacturing flowchart of a semiconductor device according to a conventional technique.
【図４】従来の半導体装置を多数個実装したモジュール
の一例を示す斜視図FIG. 4 is a perspective view showing an example of a module in which a number of conventional semiconductor devices are mounted.
１ 半導体装置 ２ 突起状電極 ３ ソケットコンタクト部 ４ 開孔部 ５ プリント基板 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Protruding electrode 3 Socket contact part 4 Opening part 5 Printed circuit board
Claims (1)
部に対して、ベアチップ状態の半導体装置の外部電極上
に設けられた突起状の外部電極を入れ、前記ソケットコ
ンタクト部およびベアの半導体装置をバーンイン炉にて
加熱してバーンインテストする半導体装置の検査方法で
あって、前記突起状の外部電極をソケットコンタクト部
の開孔部に入れる際は開孔部の径は前記突起状の外部電
極の径より大きく、バーンインテストの加熱により前記
開孔部の径が徐々に小さくなって前記突起状の外部電極
と電気的に導通してバーンインテストすることを特徴と
する半導体装置の検査方法。1. Opening of a socket contact portion at normal temperature
On the external electrodes of the semiconductor device in a bare chip state
Insert the protruding external electrode provided in
Contact and bare semiconductor devices in a burn-in furnace
A semiconductor device inspection method that performs a burn-in test by heating
The projecting external electrode is connected to a socket contact portion.
When inserting into the hole of the hole, the diameter of the hole is
Larger than the diameter of the pole.
The diameter of the opening gradually decreases, and the protrusion-shaped external electrode
It is characterized by conducting a burn-in test electrically connected to
For testing semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3336547A JP2910802B2 (en) | 1991-12-19 | 1991-12-19 | Inspection method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3336547A JP2910802B2 (en) | 1991-12-19 | 1991-12-19 | Inspection method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05164816A JPH05164816A (en) | 1993-06-29 |
| JP2910802B2 true JP2910802B2 (en) | 1999-06-23 |
Family
ID=18300263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3336547A Expired - Lifetime JP2910802B2 (en) | 1991-12-19 | 1991-12-19 | Inspection method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2910802B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2880695B2 (en) * | 1996-09-27 | 1999-04-12 | 松下電子工業株式会社 | Method for accelerated test of semiconductor memory device |
-
1991
- 1991-12-19 JP JP3336547A patent/JP2910802B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05164816A (en) | 1993-06-29 |
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