JP2909406B2 - Variable capacitance diode device - Google Patents
Variable capacitance diode deviceInfo
- Publication number
- JP2909406B2 JP2909406B2 JP7086117A JP8611795A JP2909406B2 JP 2909406 B2 JP2909406 B2 JP 2909406B2 JP 7086117 A JP7086117 A JP 7086117A JP 8611795 A JP8611795 A JP 8611795A JP 2909406 B2 JP2909406 B2 JP 2909406B2
- Authority
- JP
- Japan
- Prior art keywords
- variable capacitance
- capacitance
- electrodes
- terminals
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子同調方式のＡＭ受
信機やＦＭ受信機に用いられる可変容量ダイオード装置
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance diode device used for an electronically tuned AM receiver or FM receiver.
【０００２】[0002]
【従来の技術】電子同調方式のＡＭ受信機のチュナー部
の回路としては、図９の回路図に示すような回路が公知
であり、車載用、家庭用の受信機に広く用いられてい
る。図９には、可変容量ダイオードＤ１、Ｄ２、トリマ
コンデンサＣ１、同調コイルＬ２からなるアンテナ同調
回路ＲＦ１、可変容量ダイオードＤ３、Ｄ４、トリマコ
ンデンサＣ２、同調コイルＬ３からなる高周波同調回路
ＲＦ２、可変容量ダイオードＤ５、Ｄ６、トリマコンデ
ンサＣ３、パディングコンデンサＣ４、発振コイルＬ５
からなる局部発振回路ＯＳＣが示されている。なお、Ｌ
１はアンテナとアンテナ同調回路ＲＦ１間、Ｌ４は高周
波同調回路ＲＦ２と混合回路ＭＩＸ間、Ｌ６は局部発振
回路ＯＳＣと混合回路ＭＩＸ間の夫々結合コイルであ
る。2. Description of the Related Art As a circuit of a tuner section of an electronically tuned AM receiver, a circuit as shown in a circuit diagram of FIG. 9 is known, and is widely used in on-vehicle and home receivers. FIG. 9 shows an antenna tuning circuit RF1 including variable capacitance diodes D1 and D2, a trimmer capacitor C1, a tuning coil L2, a high frequency tuning circuit RF2 including variable capacitance diodes D3 and D4, a trimmer capacitor C2 and a tuning coil L3, and a variable capacitance diode. D5, D6, trimmer capacitor C3, padding capacitor C4, oscillation coil L5
Is shown in FIG. Note that L
1 is a coupling coil between the antenna and the antenna tuning circuit RF1, L4 is a coupling coil between the high-frequency tuning circuit RF2 and the mixing circuit MIX, and L6 is a coupling coil between the local oscillation circuit OSC and the mixing circuit MIX.
【０００３】電圧源ＶＳからバイアス抵抗Ｒ１、Ｒ２、
Ｒ３を経て夫々の回路の可変容量ダイオードにバイアス
電圧が供給され、そのバイアス電圧を変化させることに
より、希望する周波数を受信できる。可変容量ダイオー
ドのカソードを共通接続する構成は、特にアンテナ同調
回路ＲＦ１、高周波同調回路ＲＦ２において単体の可変
容量ダイオードを用いる場合に比較して次の利点があ
る。[0003] The bias resistors R1, R2,
A bias voltage is supplied to the variable capacitance diodes of the respective circuits via R3, and a desired frequency can be received by changing the bias voltage. The configuration in which the cathodes of the variable capacitance diodes are connected in common has the following advantages as compared with the case where a single variable capacitance diode is used in the antenna tuning circuit RF1 and the high frequency tuning circuit RF2.
【０００４】夫々の回路の可変容量ダイオードが単体の
場合には、電界強度の強い入力信号による電流が可変容
量ダイオードに流れると、その整流作用によって波形が
歪むことによる高調波の発生や、入力信号の振幅に応じ
て容量値が変動することによる希望する周波数近傍の周
波数の信号の混入等があるが、一対の可変容量ダイオー
ドを用いることによりこのような不都合が防がれる。局
部発振回路ＯＳＣでは、アンテナ同調回路ＲＦ１、高周
波同調回路ＲＦ２に対応させて容量値を変化させるため
に同じ構成にしてある。可変容量ダイオードは夫々の回
路間の干渉を避けるために、一対づつ別々の容量素子と
して形成され、その別々に形成された容量素子が樹脂封
止されて可変容量ダイオード装置としてチュナー部の回
路に接続されるのが一般的である。When the variable capacitance diode of each circuit is a single unit, if a current due to an input signal having a strong electric field flows through the variable capacitance diode, the rectification of the circuit causes distortion of the waveform, thereby generating harmonics, There is a possibility that a signal of a frequency near a desired frequency is mixed due to a change in the capacitance value according to the amplitude of the signal. However, such inconvenience can be prevented by using a pair of variable capacitance diodes. The local oscillation circuit OSC has the same configuration to change the capacitance value corresponding to the antenna tuning circuit RF1 and the high-frequency tuning circuit RF2. In order to avoid interference between the circuits, the variable capacitance diode is formed as a pair of separate capacitance elements, and the separately formed capacitance elements are sealed with resin and connected to the circuit of the tuner section as a variable capacitance diode device. It is generally done.
【０００５】図７は従来の可変容量ダイオード装置を示
す平面図であり、点線で囲った樹脂パッケージを透視し
て示してある。図７において、Ｓ１はアンテナ同調回路
ＲＦ１の可変容量ダイオードＤ１、Ｄ２が形成されてい
る容量素子、Ｓ２は高周波同調回路ＲＦ２の可変容量ダ
イオードＤ３、Ｄ４が形成されている容量素子、Ｓ３は
局部発振回路ＯＳＣの可変容量ダイオードＤ５、Ｄ６の
形成されている容量素子であり、Ｓ１ 、Ｓ２、Ｓ３の
符号は図９にも対応させて示してある。FIG. 7 is a plan view showing a conventional variable capacitance diode device, which is seen through a resin package surrounded by a dotted line. In FIG. 7, S1 is a capacitance element of the antenna tuning circuit RF1 on which the variable capacitance diodes D1 and D2 are formed, S2 is a capacitance element of the high frequency tuning circuit RF2 on which the variable capacitance diodes D3 and D4 are formed, and S3 is local oscillation. This is a capacitance element in which the variable capacitance diodes D5 and D6 of the circuit OSC are formed, and reference numerals S1, S2 and S3 are also shown corresponding to FIG.
【０００６】１乃至１０は硬化した樹脂パッケージ２４
の側面に露呈する端子であり、樹脂パッケージ２４の対
向する側面に露呈している。２１は容量素子のアノード
電極であり、夫々の容量素子には一対の可変容量ダイオ
ードが形成されているので、容量素子の片側の主面には
２個のアノード電極２１が設けられ、対向する主面には
共通接続されたカソード電極が形成されている。 ２０
Ａ、２０Ｂ、２０Ｃは金属片であり、夫々端子１、８、
９に接続している。そして、容量素子Ｓ１、Ｓ２、Ｓ３
が夫々別の金属片２０Ａ、２０Ｂ、２０Ｃ上にカソード
電極を固着された状態で載置されている。1 to 10 are cured resin packages 24
Are exposed on the opposite side surface of the resin package 24. Reference numeral 21 denotes an anode electrode of the capacitance element. Since a pair of variable capacitance diodes are formed in each capacitance element, two anode electrodes 21 are provided on one main surface of the capacitance element and opposing main electrodes are provided. A cathode electrode connected in common is formed on the surface. 20
A, 20B, and 20C are metal pieces, and terminals 1, 8, and
9 is connected. Then, the capacitive elements S1, S2, S3
Are mounted on separate metal pieces 20A, 20B, and 20C, respectively, with the cathode electrode fixed thereto.
【０００７】容量素子Ｓ１では可変容量ダイオードＤ
１、Ｄ２のアノード電極２１が夫々端子２、６に接続さ
れ、容量素子Ｓ２では可変容量ダイオードＤ３、Ｄ４の
アノード電極２１が夫々端子４、７、容量素子Ｓ３では
可変容量ダイオードＤ５、Ｄ６のアノード電極２１が夫
々端子５、１０に接続されている。図８はこのように接
続された図７の結線図を示すと共に、可変容量ダイオー
ド装置がチュナー部の回路に接続される場合の他の回路
素子との接続関係を示す。図７と図８からわかるよう
に、従来の可変容量ダイオード装置は一対の可変容量ダ
イオードのアノード電極２１が樹脂２４の対向する側面
の端子に接続している。つまり、対向する側面から引き
出されている。In the capacitance element S1, a variable capacitance diode D
The anode electrodes 21 of D1 and D2 are connected to the terminals 2 and 6, respectively. The anode electrodes 21 of the variable capacitance diodes D3 and D4 are connected to the terminals 4 and 7, respectively, and the anodes of the variable capacitance diodes D5 and D6 are connected to the capacitance element S3. Electrodes 21 are connected to terminals 5 and 10, respectively. FIG. 8 shows the connection diagram of FIG. 7 connected in this way, and shows the connection relationship with other circuit elements when the variable capacitance diode device is connected to the circuit of the tuner unit. As can be seen from FIGS. 7 and 8, in the conventional variable capacitance diode device, the anode electrodes 21 of the pair of variable capacitance diodes are connected to the terminals on the opposite side surfaces of the resin 24. That is, it is pulled out from the opposite side surface.
【０００８】このために、可変容量ダイオード装置を回
路基板上でチュナー部の回路に接続する場合、図８から
明らかなように導体パターン２３が長くなり、導体パタ
ーン２３の配置に要する回路基板の面積が広くなる。す
なわち、同調回路ＲＦ１、同調回路ＲＦ２、局部発振回
路ＯＳＣを形成する導体パターン２３は、可変容量ダイ
オード装置の点線で囲った樹脂パッケージ２４を跨いで
配置されるで、長くなる。For this reason, when the variable capacitance diode device is connected to the circuit of the tuner section on the circuit board, as is apparent from FIG. 8, the conductor pattern 23 becomes longer, and the area of the circuit board required for the arrangement of the conductor pattern 23 is increased. Becomes wider. That is, the conductor patterns 23 forming the tuning circuit RF1, the tuning circuit RF2, and the local oscillation circuit OSC are extended over the resin package 24 surrounded by the dotted line of the variable capacitance diode device, and thus become longer.
【０００９】また、二個の回路、図８では容量素子Ｓ３
の可変容量ダイオードＤ５、Ｄ６が接続する局部発振回
路ＯＳＣと、容量素子Ｓ２の可変容量ダイオードＤ４、
Ｄ５が接続する同調回路ＲＦ２は平面的に内側と外側と
いうように導体パターン２３が配置されるので、その長
さが長くなると同時に、導体パターン２３の配置に要す
る回路基板の面積も広くなる。さらに図示されていない
が、端子１、８、６にはバイアス電圧を供給する導体パ
ターンが接続され、同調回路ＲＦ１、同調回路ＲＦ２、
局部発振回路ＯＳＣを形成する導体パターン２３とバイ
アス電圧を供給する導体パターンが混在するので、その
導体パターン全体の配置が複雑になる。In addition, two circuits, a capacitive element S3 in FIG.
The local oscillation circuit OSC to which the variable capacitance diodes D5 and D6 are connected, and the variable capacitance diode D4 and
In the tuning circuit RF2 to which D5 is connected, the conductor patterns 23 are arranged such that they are inside and outside in a plan view. Therefore, the length of the circuit is increased, and at the same time, the area of the circuit board required for arrangement of the conductor patterns 23 is increased. Although not shown, a conductor pattern for supplying a bias voltage is connected to the terminals 1, 8, and 6, and a tuning circuit RF1, a tuning circuit RF2,
Since the conductor pattern 23 forming the local oscillation circuit OSC and the conductor pattern supplying the bias voltage are mixed, the arrangement of the entire conductor pattern becomes complicated.
【００１０】さらにまた、導体パターンが長くなると夫
々の回路の浮遊容量が増加するので、大きな容量値の可
変範囲が必要なＡＭ受信機のアンテナ同調回路ＲＦ１、
高周波同調回路ＲＦ２では容量値の可変範囲が実質的に
小さくなり望ましくない。無論、これらの技術問題は回
路基板を多層にすることにより、ある程度解決できるが
回路基板を高価にする欠点がある。Further, since the stray capacitance of each circuit increases as the conductor pattern becomes longer, the antenna tuning circuits RF1 and RF1 of the AM receiver which require a large variable range of capacitance value.
In the high-frequency tuning circuit RF2, the variable range of the capacitance value becomes substantially small, which is not desirable. Of course, these technical problems can be solved to some extent by making the circuit board multilayer, but there is a disadvantage that the circuit board is expensive.
【００１１】[0011]
【発明が解決しようとする課題】本発明の課題は、可変
容量ダイオード装置を用いた回路が回路基板上に形成さ
れる場合に、回路の導体パターンを短くでき、また回路
の導体パターンの配置に要する回路基板の面積を狭くで
きる可変容量ダイオード装置を提供することにある。こ
のことによって、夫々の回路の浮遊容量を小さくし、可
変容量ダイオードによる容量値の可変範囲を実質的に大
きくできる。また、例えばチュナー回路のような回路全
体の小型化に寄与できる。SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit using a variable capacitance diode device which is formed on a circuit board. An object of the present invention is to provide a variable capacitance diode device capable of reducing a required circuit board area. Thus, the stray capacitance of each circuit can be reduced, and the variable range of the capacitance value by the variable capacitance diode can be substantially increased. Further, for example, it is possible to contribute to miniaturization of the entire circuit such as a tuner circuit.
【００１２】[0012]
【課題を解決するための手段】本発明は、一対の可変容
量ダイオードを形成した容量素子を複数個並列に並べて
樹脂封止し、共通接続した電極、共通接続していない電
極を夫々の容量素子ごとに端子に接続した可変容量ダイ
オード装置において、一対の可変容量ダイオードは容量
素子の並ぶ方向に沿って並べて形成され、そのカソード
電極とアノード電極は対向する主面に形成され、夫々の
容量素子は共通接続する電極を他の容量素子のものとは
分離されしかも独立した端子を備えた金属片上に固着し
て載置され、少なくとも一個の容量素子の共通接続され
ていない電極は樹脂パッケージの同じ側面の端子に接続
されていることを特徴とする。According to the present invention, a plurality of capacitance elements each having a pair of variable capacitance diodes are arranged in parallel and sealed with a resin, and electrodes connected in common and electrodes not connected in common are respectively connected to the capacitance elements. In the variable capacitance diode device connected to each terminal, a pair of variable capacitance diodes are formed side by side along the direction in which the capacitance elements are arranged, and the cathode electrode and the anode electrode are formed on opposing main surfaces. The electrodes to be connected in common are separated from those of the other capacitive elements and fixedly mounted on a metal piece provided with independent terminals, and the electrodes that are not connected to at least one of the capacitive elements are connected to the same side of the resin package. Characterized by being connected to the terminal of
【００１３】[0013]
【作用】容量素子の共通接続されていない電極が樹脂パ
ッケージの同じ側面の端子に接続されることにより、そ
の容量素子の接続される回路の導体パターンは樹脂パッ
ケージを跨ぐことなく形成されるので、導体パターンは
短くでき、導体パターンの配置に要する面積を狭くでき
る。このことにより、回路の浮遊容量が小さくなり、可
変容量ダイオードによる容量値の可変範囲を実質的に大
きくできる。また、回路全体の小型化に寄与できる。When the electrodes of the capacitive element that are not commonly connected are connected to the terminals on the same side of the resin package, the conductor pattern of the circuit to which the capacitive element is connected is formed without straddling the resin package. The conductor pattern can be shortened, and the area required for disposing the conductor pattern can be reduced. As a result, the stray capacitance of the circuit is reduced, and the variable range of the capacitance value by the variable capacitance diode can be substantially increased. In addition, it can contribute to miniaturization of the entire circuit.
【００１４】[0014]
【実施例】以下、本発明の可変容量ダイオード装置の第
１の実施例を示す図１、図２、図３を参照しながら説明
する。図１は平面図、図２は図１の結線図であり、可変
容量ダイオード装置が図９のチュナー部の回路に接続さ
れる場合の他の回路素子との接続関係を同時に示してあ
る。図３は、正面図である。なお、図８、図７と同一部
分は同じ符号を付与してある。図１には硬化した樹脂パ
ッケージ２４を透視した内部が示されているが、容量素
子Ｓ１、Ｓ２、Ｓ３は細長く形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A variable capacitance diode device according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3. FIG. FIG. 1 is a plan view, and FIG. 2 is a connection diagram of FIG. 1, which also shows a connection relationship with other circuit elements when the variable capacitance diode device is connected to the circuit of the tuner unit of FIG. FIG. 3 is a front view. 8 and FIG. 7 are denoted by the same reference numerals. FIG. 1 shows the inside of the cured resin package 24 seen through, but the capacitance elements S1, S2, and S3 are formed to be elongated.
【００１５】容量素子Ｓ１には一対の可変容量ダイオー
ドＤ１、Ｄ２、容量素子Ｓ２には一対の可変容量ダイオ
ードＤ３、Ｄ４、容量素子Ｓ３には一対の可変容量ダイ
オードＤ５、Ｄ６が形成されており、三個の容量素子Ｓ
１、Ｓ２、Ｓ３は長辺をほぼ平行にして並列に並べられ
ている。そして、一対の可変容量ダイオードは夫々の容
量素子の主面をその並ぶ方向に沿って二分した細長い領
域に一個づつ並べて形成されている。片側の主面には一
対の可変容量ダイオードのアノード電極３１が別々に形
成されており、対向する主面には共通接続されたカソー
ド電極が形成されている。A pair of variable capacitance diodes D1 and D2 are formed in the capacitance element S1, a pair of variable capacitance diodes D3 and D4 are formed in the capacitance element S2, and a pair of variable capacitance diodes D5 and D6 are formed in the capacitance element S3. Three capacitive elements S
1, S2 and S3 are arranged in parallel with their long sides substantially parallel. The pair of variable capacitance diodes are formed one by one in a slender area where the main surfaces of the respective capacitance elements are bisected along the direction in which the capacitance elements are arranged. The anode electrodes 31 of the pair of variable capacitance diodes are separately formed on one main surface, and the commonly connected cathode electrodes are formed on the opposing main surfaces.
【００１６】３０Ａ、３０Ｂ、３０Ｃは板状の金属片で
あり、夫々樹脂パッケージ２４の片側の側面に露呈する
独立の端子２、３、４を備えている。容量素子Ｓ１、Ｓ
２、Ｓ３は、夫々金属片３０Ａ、３０Ｂ、３０Ｃに共通
接続されたカソード電極を固着された状態で該金属片上
に載置されている。そして、可変容量ダイオードＤ１、
Ｄ２、Ｄ３、Ｄ４、Ｄ５、Ｄ６のアノード電極３１は、
容量素子Ｓ１、Ｓ２、Ｓ３の並ぶ方向と交差する方向に
延びるリード２２によってその方向にある夫々端子６、
７、８、９、１０、５に接続されている。つまり、二つ
の容量素子Ｓ１、Ｓ２のアノード電極３１は樹脂パッケ
ージ２４の同じ側面の端子に接続しており、同じ側面か
ら引き出される。しかも、その容量素子の一対の可変容
量ダイオードのアノード電極３１の接続する端子は隣接
している。Reference numerals 30A, 30B, and 30C denote plate-shaped metal pieces, each having independent terminals 2, 3, and 4 exposed on one side surface of the resin package 24. Capacitance elements S1, S
2 and S3 are mounted on the metal pieces 30A, 30B, and 30C, respectively, in a state where cathode electrodes commonly connected to the metal pieces are fixed. And the variable capacitance diode D1,
The anode electrodes 31 of D2, D3, D4, D5, and D6 are:
The leads 6 extending in the direction intersecting the direction in which the capacitive elements S1, S2, S3 are arranged are connected to the terminals 6,
7, 8, 9, 10, and 5. That is, the anode electrodes 31 of the two capacitive elements S1 and S2 are connected to the terminals on the same side of the resin package 24 and are drawn out from the same side. Moreover, the terminals to which the anode electrodes 31 of the pair of variable capacitance diodes of the capacitance element are connected are adjacent to each other.
【００１７】また、二つの容量素子Ｓ１、Ｓ２の共通接
続されたカソード電極は、アノード電極３１の接続され
る端子が露呈する側面とは反対側の側面の端子に接続さ
れている。容量素子Ｓ３の一対の可変容量ダイオードの
アノード電極３１だけが、樹脂パッケージ２４の対向す
る側面の端子に接続されている。The commonly connected cathode electrodes of the two capacitive elements S1 and S2 are connected to terminals on the side opposite to the side where the terminal to which the anode electrode 31 is connected is exposed. Only the anode electrode 31 of the pair of variable capacitance diodes of the capacitance element S3 is connected to the terminal on the opposite side surface of the resin package 24.
【００１８】このように構成された可変容量ダイオード
装置は、図３に示すように樹脂パッケージ２４の対向す
る両側面に端子が露呈するいわゆるデュアルラインパッ
ケージの構造になっている。なお、容量素子に形成され
ている可変容量ダイオードの構成はどの容量素子も同じ
であるが、一例を容量素子Ｓ１の横断面図として図４に
示してある。The variable capacitance diode device configured as described above has a so-called dual line package structure in which terminals are exposed on both opposite sides of the resin package 24 as shown in FIG. The configuration of the variable capacitance diode formed in the capacitance element is the same for all the capacitance elements, but an example is shown in FIG. 4 as a cross-sectional view of the capacitance element S1.
【００１９】図４において、５０は極めて高濃度に不純
物をドープされている導電形がＮ形のシリコンの半導体
基板、５１は低濃度に不純物をドープされた導電形がＮ
形のエピタキシャル層であり、エピタキシャル層５１内
に高濃度の不純物を拡散されたＮ形の拡散層５２とＰ形
の拡散層５３によってＰＮ接合が形成されている。一つ
のＰＮ接合によって一つの可変容量ダイオードが形成さ
れており、エピタキシャル層５１には二つのＰＮ接合を
形成する二つの領域がある。夫々の領域は、容量素子Ｓ
１の主面をその並ぶ方向に沿って二分した形状になる。In FIG. 4, reference numeral 50 denotes a semiconductor substrate of N-type silicon which is doped with an impurity at a very high concentration, and 51 denotes an N-type semiconductor substrate doped with an impurity at a low concentration.
A PN junction is formed by an N-type diffusion layer 52 and a P-type diffusion layer 53 in which a high-concentration impurity is diffused in the epitaxial layer 51. One variable capacitance diode is formed by one PN junction, and the epitaxial layer 51 has two regions forming two PN junctions. Each region has a capacitive element S
One main surface is divided into two along the direction in which the main surfaces are arranged.
【００２０】アノード電極３１が拡散層５３に接して設
けられているが、その対向する主面である半導体基板５
０の裏面には一対の可変容量ダイオードＤ１、Ｄ２の共
通接続されたカソード電極５４が設けられている。この
電極５４は金属片３０Ａの表面と共晶合金を形成した状
態で該金属片３０に固着されている。なお、カソード電
極５４は図４を除く説明では符号を付されていない。可
変容量ダイオード装置は、リードフレームを用いた一般
的な技術によって形成することができる。Although the anode electrode 31 is provided in contact with the diffusion layer 53, the semiconductor substrate 5 which is the main surface facing the anode electrode 31 is provided.
The cathode electrode 54 of the pair of variable capacitance diodes D1 and D2 is provided on the back surface of the pair 0. The electrode 54 is fixed to the metal piece 30 in a state of forming a eutectic alloy with the surface of the metal piece 30A. The cathode electrode 54 is not denoted by a reference numeral in the description except for FIG. The variable capacitance diode device can be formed by a general technique using a lead frame.
【００２１】このように構成された可変容量ダイオード
装置では、アンテナ同調回路ＲＦ１に接続される端子
６、７、高周波同調回路ＲＦ２に接続される端子８、９
が樹脂パッケージ２４の同じ側面に露呈しており、しか
も隣接しているので夫々の回路の導体パターン３３は樹
脂パッケージ２４を跨いで形成する必要はない。また、
高周波同調回路ＲＦ２が別の回路である局部発振回路Ｏ
ＳＣを平面的に内側にして囲む配置も生じない。なお、
端子２、３に接続するバイアス電圧を供給する導体パタ
ーンもアンテナ同調回路ＲＦ１、高周波同調回路ＲＦ２
を形成する導体パターン３３とは離れて別に形成される
ので導体パターン全体の配置が簡潔になる。In the variable capacitance diode device thus configured, terminals 6, 7 connected to the antenna tuning circuit RF1, and terminals 8, 9 connected to the high frequency tuning circuit RF2.
Are exposed on the same side surface of the resin package 24 and are adjacent to each other, so that the conductor pattern 33 of each circuit does not need to be formed across the resin package 24. Also,
Local oscillation circuit O in which high-frequency tuning circuit RF2 is another circuit
There is no arrangement in which the SC is planarly inward and surrounds the SC. In addition,
The conductor pattern for supplying a bias voltage to be connected to the terminals 2 and 3 also includes an antenna tuning circuit RF1 and a high-frequency tuning circuit RF2.
Is formed separately from the conductor pattern 33 forming the conductor pattern, so that the arrangement of the entire conductor pattern is simplified.
【００２２】したがって、アンテナ同調回路ＲＦ１、高
周波同調回路ＲＦ２の導体パターンを短くできるし、導
体パターン３３の配置に要する回路基板の面積を狭くで
きる。そして、アンテナ同調回路ＲＦ１、高周波同調回
路ＲＦ２の浮遊容量を小さくできるので、容量素子Ｓ
１、Ｓ２による容量値の可変範囲を大きくできる。これ
は、容量値の大きな可変範囲を必要とするＡＭ受信機の
アンテナ同調回路ＲＦ１、高周波同調回路ＲＦ２にとっ
て利点となる。また、これらの回路を形成するための回
路基板の面積を狭くできるので、チュナー部の回路全体
の小型化に寄与できる。Therefore, the conductor patterns of the antenna tuning circuit RF1 and the high-frequency tuning circuit RF2 can be shortened, and the area of the circuit board required for disposing the conductor pattern 33 can be reduced. Since the stray capacitances of the antenna tuning circuit RF1 and the high-frequency tuning circuit RF2 can be reduced, the capacitance element S
1. The variable range of the capacitance value by S2 can be increased. This is advantageous for the antenna tuning circuit RF1 and the high-frequency tuning circuit RF2 of the AM receiver requiring a large variable range of the capacitance value. Further, since the area of a circuit board for forming these circuits can be reduced, it is possible to contribute to miniaturization of the entire circuit of the tuner section.
【００２３】図５は本発明の可変容量ダイオード装置の
第２の実施例を示す平面図である。図５では、容量素子
Ｓ１の一対の可変容量ダイオードＤ１、Ｄ２のアノード
電極３１は端子６、７に接続され、容量素子Ｓ２の一対
の可変容量ダイオードＤ３、Ｄ４のアノード電極３１は
対向する側面の端子２、３に接続する。容量素子Ｓ３の
一対の可変容量ダイオードＤ５、Ｄ６のアノード電極３
１は端子５、１０に接続される。FIG. 5 is a plan view showing a second embodiment of the variable capacitance diode device according to the present invention. In FIG. 5, the anode electrodes 31 of the pair of variable capacitance diodes D1 and D2 of the capacitance element S1 are connected to the terminals 6 and 7, and the anode electrodes 31 of the pair of variable capacitance diodes D3 and D4 of the capacitance element S2 are opposite to each other. Connect to terminals 2 and 3. Anode electrode 3 of a pair of variable capacitance diodes D5 and D6 of capacitance element S3
1 is connected to terminals 5 and 10.
【００２４】また、金属片４０Ａ、４０Ｂ、４０Ｃは独
立した端子１、８、９を備える。二つの容量素子Ｓ１と
容量素子Ｓ２は、アノード電極３１の接続する端子が反
対側の側面から露呈しているが、夫々の容量素子の一対
の可変容量ダイオードのアノード電極３１は同じ側面か
ら露呈する端子に接続する。また、共通接続されたカソ
ード電極は、夫々の容量素子ごとにアノード電極３１の
接続する端子とは反対側の側面の端子に接続する。この
ように構成しても、容量素子Ｓ１と容量素子Ｓ２の接続
する回路の浮遊容量を第１の実施例と同じように小さく
できる。また、その回路を形成するための回路基板の面
積を狭くできる。The metal pieces 40A, 40B, and 40C have independent terminals 1, 8, and 9, respectively. In the two capacitance elements S1 and S2, the terminal to which the anode electrode 31 is connected is exposed from the opposite side surface, but the anode electrodes 31 of the pair of variable capacitance diodes of each capacitance element are exposed from the same side surface. Connect to terminal. The commonly connected cathode electrodes are connected to the terminals on the side opposite to the terminals to which the anode electrode 31 is connected for each of the capacitive elements. Even with such a configuration, the stray capacitance of the circuit connecting the capacitive element S1 and the capacitive element S2 can be reduced as in the first embodiment. Further, the area of a circuit board for forming the circuit can be reduced.
【００２５】図６は本発明の第３の実施例を示す平面図
であるが、樹脂パッケージ２４の外側に露呈する端子を
１２個設けてある。容量素子Ｓ１の一対の可変容量ダイ
オードＤ１、Ｄ２のアノード電極３１は端子７、８、容
量素子Ｓ２の可変容量ダイオードＤ３、Ｄ４のアノード
電極３１は端子９、１０、容量素子Ｓ３の可変容量ダイ
オードＤ５、Ｄ６のアノード電極３１は端子１１、１２
に接続する。金属片５０Ａ、５０Ｂ、５０Ｃは夫々独立
した端子１、３、５を備えている。FIG. 6 is a plan view showing a third embodiment of the present invention, in which twelve terminals exposed outside the resin package 24 are provided. The anode electrodes 31 of the pair of variable capacitance diodes D1 and D2 of the capacitance element S1 are terminals 7 and 8, the anode electrodes 31 of the variable capacitance diodes D3 and D4 of the capacitance element S2 are terminals 9 and 10, and the variable capacitance diode D5 of the capacitance element S3. , D6 are connected to terminals 11, 12
Connect to The metal pieces 50A, 50B, and 50C have independent terminals 1, 3, and 5, respectively.
【００２６】図６では、全ての容量素子の可変容量ダイ
オードのアノード電極３１が、容量素子Ｓ１、Ｓ２、Ｓ
３の並ぶ方向と交差する方向に延びるリード２２により
片側の側面の端子に接続し、共通接続された全てのカソ
ード電極が反対側の側面の端子に接続している。夫々の
端子はリード２２の延びる方向にある。図６では他の実
施例に比較して端子数が増加するが、全てのアノード電
極が片側から取り出され、また共通接続されたカソード
電極が対向する側面から取り出されるので、局部発振回
路ＯＳＣを形成する回路基板の面積も狭くなり、チュナ
ー部の回路全体を形成する回路基板の面積を他の実施例
に比較していっそう狭くできる。In FIG. 6, the anode electrodes 31 of the variable capacitance diodes of all the capacitance elements are the capacitance elements S1, S2, S
The leads 22 extending in a direction intersecting the direction in which the three electrodes 3 are arranged are connected to terminals on one side surface, and all commonly connected cathode electrodes are connected to terminals on the opposite side surface. Each terminal is in the direction in which the lead 22 extends. Although the number of terminals is increased in FIG. 6 as compared with the other embodiments, all the anode electrodes are taken out from one side and the commonly connected cathode electrodes are taken out from the opposite side, so that the local oscillation circuit OSC is formed. Also, the area of the circuit board that forms the entire circuit of the tuner section can be made smaller as compared with the other embodiments.
【００２７】なお、実施例では可変容量ダイオード装置
がＡＭ受信機のチュナー部の回路に用いられる場合を説
明したが、他の回路に用い得ることはいうまでもない。
また、実施例ではカソード電極を共通接続したが、アノ
ード電極を共通接続する場合もある。Although the embodiment has been described in connection with the case where the variable capacitance diode device is used in the tuner circuit of the AM receiver, it goes without saying that the variable capacitance diode device can be used in other circuits.
Although the cathode electrodes are commonly connected in the embodiment, the anode electrodes may be commonly connected.
【００２８】[0028]
【発明の効果】以上述べたように本発明の可変容量ダイ
オード装置は、夫々一対の可変容量ダイオードを形成し
てある複数の容量素子を一列に並べて樹脂封止してあ
り、少なくとも一個の容量素子の共通接続されていない
アノード電極又はカソード電極を樹脂パッケージの同じ
側面に露呈する端子に接続してある。夫々の端子は容量
素子の並ぶ方向に交差する方向にある。共通接続された
電極は、反対側の側面の端子に接続するとよい。このよ
うに構成すると、この容量素子を用いる回路では、回路
基板の導体パターンを短くできるので浮遊容量が小さく
なり、可変容量ダイオードの容量値の可変範囲を実質的
に大きくできる。このことは、アンテナ同調回路や高周
波同調回路では大きな利点である。また、回路を形成す
る回路基板の面積も狭くできるので、それらの回路から
なる回路全体の小型化に寄与できる。さらに、導体パタ
ーン全体の配置が簡潔になり、その設計が容易になる利
点もある。As described above, in the variable capacitance diode device of the present invention, a plurality of capacitance elements each forming a pair of variable capacitance diodes are arranged in a line and resin-sealed, and at least one capacitance element is formed. Are connected to the terminals exposed on the same side surface of the resin package. Each terminal is in a direction crossing the direction in which the capacitance elements are arranged. The commonly connected electrodes may be connected to terminals on the opposite side. With such a configuration, in a circuit using this capacitance element, the conductor pattern of the circuit board can be shortened, so that the stray capacitance decreases, and the variable range of the capacitance value of the variable capacitance diode can be substantially increased. This is a great advantage in antenna tuning circuits and high-frequency tuning circuits. Further, since the area of the circuit board on which the circuits are formed can be reduced, it is possible to contribute to miniaturization of the entire circuit including the circuits. Further, there is an advantage that the arrangement of the entire conductor pattern is simplified and the design thereof is facilitated.
【図１】 本発明の可変容量ダイオード装置の第１の実
施例を示す平面図である。FIG. 1 is a plan view showing a first embodiment of a variable capacitance diode device according to the present invention.
【図２】 図１の結線図である。FIG. 2 is a connection diagram of FIG.
【図３】 図１の正面図である。FIG. 3 is a front view of FIG. 1;
【図４】 図１の容量素子の横断面図である。FIG. 4 is a cross-sectional view of the capacitive element of FIG.
【図５】 本発明の可変容量ダイオード装置の第２の実
施例を示す平面図である。FIG. 5 is a plan view showing a second embodiment of the variable capacitance diode device according to the present invention.
【図６】 本発明の可変容量ダイオード装置の第３の実
施例を示す平面図である。FIG. 6 is a plan view showing a third embodiment of the variable capacitance diode device according to the present invention.
【図７】 従来の可変容量ダイオード装置の一例を示す
平面図である。FIG. 7 is a plan view showing an example of a conventional variable capacitance diode device.
【図８】 図７の結線図である。FIG. 8 is a connection diagram of FIG. 7;
【図９】 本発明の可変容量ダイオード装置が用いられ
るＡＭラジオ受信機ののチュナー部の回路図である。FIG. 9 is a circuit diagram of a tuner section of an AM radio receiver using the variable capacitance diode device of the present invention.
１乃至１２ 端子 Ｓ１乃至Ｓ３ 容量素子 Ｄ１乃至Ｄ６ 可変容量ダイオード ３１ アノード電極 1 to 12 terminals S1 to S3 Capacitance element D1 to D6 Variable capacitance diode 31 Anode electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田中 一郎 埼玉県鶴ケ島市大字五味ケ谷18番地 東 光株式会社埼玉事業所内 (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 25/04 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Ichiro Tanaka 18 Ogomi-gaya, Tsurugashima-shi, Saitama Toko Co., Ltd. Saitama Office (58) Field surveyed (Int.Cl. 6 , DB name) H01L 25 / 04
Claims (2)
る三個の容量素子を並列に並べて樹脂封止し、共通接続
した電極、共通接続していない電極を夫々の容量素子ご
とに端子に接続した可変容量ダイオード装置において、
一対の可変容量ダイオードは容量素子の並ぶ方向に沿っ
て並べて形成され、そのカソード電極とアノード電極は
対向する主面に形成され、夫々の容量素子は共通する電
極を他の容量素子のものとは分離されしかも独立した端
子を備えた金属片上に載置され、少なくとも二個の容量
素子の共通接続されていない電極は容量素子ごとに樹脂
パッケージの同じ側面の隣接する端子に接続され、その
共通接続された電極は共通接続されていない電極に接続
する端子が露呈する樹脂パッケージの側面とは反対側の
側面に露呈する金属片の端子に接続していることを特徴
とする可変容量ダイオード装置。The method according to claim 1 a pair of variable capacitance diodes formed Citea
A variable capacitance diode device in which three capacitance elements are arranged in parallel and resin-sealed, and a commonly connected electrode and a non-commonly connected electrode are connected to a terminal for each capacitance element.
A pair of variable capacitance diodes are formed side by side along the direction in which the capacitance elements are arranged, the cathode electrode and the anode electrode are formed on opposing main surfaces, and each capacitance element has a common electrode different from that of another capacitance element. The electrodes that are placed on a metal piece with separate and independent terminals and that are not connected to at least two capacitive elements in common are made of resin for each capacitive element.
Connected to adjacent terminals on the same side of the package,
Commonly connected electrodes are connected to non-commonly connected electrodes
Terminals on the opposite side of the resin package
The feature is that it is connected to the terminal of the metal piece exposed on the side
Variable capacitance diode device according to.
量素子を三個並列に並べて樹脂封止し、共通接続した電
極、共通接続していない電極を夫々の容量素子ごとに端
子に接続した可変容量ダイオード装置において、一対の
可変容量ダイオードは容量素子の並ぶ方向に沿って並べ
て形成され、そのカソード電極とアノード電極は対向す
る主面に形成され、夫々の容量素子は共通接続する電極
を他の容量素子のものとは分離されしかも独立した端子
を備えた金属片上に載置され、少なくとも二個の容量素
子の共通接続されていない電極は樹脂パッケージの同じ
側面の隣接した端子に接続され、その共通接続された電
極は共通接続されていない電極に接続する端子が露呈す
る樹脂パッケージの側面とは反対側の側面から露呈する
金属片の端子に接続していることを特徴とする可変容量
ダイオード装置。2. A capacitor having a pair of variable capacitance diodes formed therein.
The three elements are arranged in parallel and sealed with resin.
Poles and electrodes that are not connected in common to each capacitive element.
In the variable capacitance diode device connected to the
Variable capacitance diodes are arranged in the direction in which the capacitance elements are arranged.
The cathode electrode and the anode electrode face each other.
The electrodes are formed on the main surface of each
Is separated from those of other capacitive elements and independent terminals
At least two capacitors placed on a metal strip with
The electrodes that are not connected in common are the same in the resin package.
Connected to adjacent terminals on the side, and
The poles have exposed terminals that connect to non-commonly connected electrodes
Exposed from the side opposite to the side of the resin package
A variable capacitance diode device connected to a terminal of a metal piece .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7086117A JP2909406B2 (en) | 1995-03-17 | 1995-03-17 | Variable capacitance diode device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7086117A JP2909406B2 (en) | 1995-03-17 | 1995-03-17 | Variable capacitance diode device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08264713A JPH08264713A (en) | 1996-10-11 |
| JP2909406B2 true JP2909406B2 (en) | 1999-06-23 |
Family
ID=13877760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7086117A Expired - Lifetime JP2909406B2 (en) | 1995-03-17 | 1995-03-17 | Variable capacitance diode device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2909406B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10012872C1 (en) * | 2000-03-16 | 2001-08-09 | Infineon Technologies Ag | Electronic component with capacitance diodes, use of the component in a receiving unit and circuit arrangement with the component (e.g. three-band television tuner) |
| JP4857531B2 (en) * | 2004-07-08 | 2012-01-18 | 三菱電機株式会社 | Semiconductor device |
| US7923818B2 (en) * | 2005-11-24 | 2011-04-12 | Technische Universiteit Delft | Varactor element and low distortion varactor circuit arrangement |
-
1995
- 1995-03-17 JP JP7086117A patent/JP2909406B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08264713A (en) | 1996-10-11 |
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