JP2906757B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2906757B2 JP2906757B2 JP22415891A JP22415891A JP2906757B2 JP 2906757 B2 JP2906757 B2 JP 2906757B2 JP 22415891 A JP22415891 A JP 22415891A JP 22415891 A JP22415891 A JP 22415891A JP 2906757 B2 JP2906757 B2 JP 2906757B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- oscillation
- reset signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明はリセット信号の入力回路
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal input circuit.
【０００２】[0002]
【従来の技術】図２に従来の半導体装置のブロック図を
示す。2. Description of the Related Art FIG. 2 is a block diagram of a conventional semiconductor device.
【０００３】発振回路１は基準信号２を分周回路３に出
力し、分周回路３は第一の分周信号４と第二の分周信号
５を出力する。The oscillation circuit 1 outputs a reference signal 2 to a frequency dividing circuit 3, and the frequency dividing circuit 3 outputs a first frequency divided signal 4 and a second frequency divided signal 5.
【０００４】発振停止検出回路６は第一の分周信号４の
状態により発振回路１の停止を検出する。The oscillation stop detection circuit 6 detects the stop of the oscillation circuit 1 based on the state of the first frequency-divided signal 4.
【０００５】リセット信号９は、入力端子７よりノイズ
除去回路８に入力される。The reset signal 9 is input from the input terminal 7 to the noise elimination circuit 8.
【０００６】ノイズ除去回路８はリセット信号９と第二
の分周信号５のパルス幅を比較し、リセット信号９が設
定値以上のパルス幅の場合、初期化信号１０を出力す
る。The noise elimination circuit 8 compares the pulse width of the reset signal 9 with the pulse width of the second frequency-divided signal 5, and outputs an initialization signal 10 when the reset signal 9 has a pulse width equal to or larger than a set value.
【０００７】[0007]
【発明が解決しようとする課題】しかし、電源投入時な
ど発振回路１が動作を停止している場合、ノイズ除去回
路８に第二の分周信号５が入力されずリセット信号９が
入力された場合でも初期化信号１０が出力されず半導体
装置が初期化されない。However, when the oscillation circuit 1 stops operating, such as when the power is turned on, the second frequency-divided signal 5 is not input to the noise removing circuit 8 but the reset signal 9 is input. Even in this case, the initialization signal 10 is not output and the semiconductor device is not initialized.
【０００８】確実な初期化を行うためには発振回路１が
発振を開始するまでリセット信号９を入力する必要があ
り、発振回路１が水晶発振回路の場合では発振開始に数
秒を要するため、リセット信号９のパルス幅も数秒が必
要となってしまいＣＲの時定数による入力が不可能とな
る。In order to perform reliable initialization, it is necessary to input a reset signal 9 until the oscillation circuit 1 starts oscillating. When the oscillation circuit 1 is a crystal oscillation circuit, it takes several seconds to start oscillation. The pulse width of the signal 9 also requires several seconds, so that input by the CR time constant becomes impossible.
【０００９】また、発振回路１の影響をなくすためにノ
イズ除去回路８を使用せずリセット信号９を直接初期化
信号とすることも考えられるがノイズによる誤動作の恐
れが大きい。It is also conceivable to use the reset signal 9 directly as an initialization signal without using the noise removing circuit 8 in order to eliminate the influence of the oscillation circuit 1, but there is a great risk of malfunction due to noise.
【００１０】そこで本発明の半導体装置はノイズでの誤
動作を防止しつつ、発振回路の動作状態によらずリセッ
ト信号による初期化を確実に、短いパルス幅で行えるよ
うにすることを目的する。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of reliably performing initialization with a reset signal with a short pulse width irrespective of the operation state of an oscillation circuit while preventing a malfunction due to noise.
【００１１】[0011]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置は、ａ）基準信号を出力する発
振回路と、ｂ）前記基準信号を分周し、分周信号を出力
する分周回路と、ｃ）前記基準信号または前記分周信号
を入力し、前記発振回路の動作状態を検出する発振停止
検出回路と、ｄ）リセット信号を入力する入力端子と、
ｅ）前記リセット信号と前記発振信号または前記分周信
号を入力し、前記リセット信号が設定値以上のパルス幅
の時初期化信号を出力するノイズ除去回路とを少なくと
も具備する半導体装置に於いて、ｆ）前記発振停止検出
回路で発振停止が検出された場合、前記リセット信号を
前記ノイズ除去回路を介さずに初期化信号とすることを
特徴とする。In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises: a) an oscillation circuit for outputting a reference signal; and b) dividing the reference signal and outputting a divided signal. A frequency divider circuit, c) an oscillation stop detection circuit that receives the reference signal or the frequency-divided signal, and detects an operation state of the oscillator circuit, and d) an input terminal that receives a reset signal.
e) a semiconductor device having at least a noise removal circuit that receives the reset signal and the oscillation signal or the frequency-divided signal and outputs an initialization signal when the reset signal has a pulse width equal to or greater than a set value. f) When the oscillation stop is detected by the oscillation stop detection circuit, the reset signal is an initialization signal without passing through the noise removal circuit.
【００１２】[0012]
【実施例】図１に本発明の半導体装置の一実施例のブロ
ック図を示す。FIG. 1 is a block diagram showing an embodiment of a semiconductor device according to the present invention.
【００１３】発振回路１は基準信号２を分周回路３に出
力し、分周回路３は第一の分周信号４と第二の分周信号
５を出力する。The oscillation circuit 1 outputs the reference signal 2 to the frequency dividing circuit 3, and the frequency dividing circuit 3 outputs the first frequency divided signal 4 and the second frequency divided signal 5.
【００１４】発振停止検出回路６は第一の分周信号４の
状態により発振回路１の停止を検出し、発振停止時は検
出信号１１を出力する。The oscillation stop detection circuit 6 detects the stop of the oscillation circuit 1 based on the state of the first frequency-divided signal 4, and outputs a detection signal 11 when the oscillation stops.
【００１５】リセット信号９は、入力端子７よりノイズ
除去回路８に入力される。The reset signal 9 is input from the input terminal 7 to the noise elimination circuit 8.
【００１６】ノイズ除去回路８はリセット信号９と第二
の分周信号５のパルス幅を比較し、リセット信号９が設
定値以上のパルス幅の場合、第一の初期化信号１２を出
力する。The noise elimination circuit 8 compares the pulse width of the reset signal 9 with the pulse width of the second frequency-divided signal 5, and outputs a first initialization signal 12 when the reset signal 9 has a pulse width equal to or larger than a set value.
【００１７】バイパス回路１３は検出信号１１が入力さ
れるとリセット信号９をノイズ除去回路８を介さずに第
一の初期化信号１２と加算し、初期化信号１０を出力す
る。発振回路１が正常動作している場合は検出信号１１
は低レベルとなり、リセット信号９はノイズ除去回路８
によりノイズを除かれリセット信号９が設定値以上のパ
ルス幅の場合、半導体装置の初期化を行う。When the detection signal 11 is input, the bypass circuit 13 adds the reset signal 9 to the first initialization signal 12 without passing through the noise elimination circuit 8, and outputs the initialization signal 10. When the oscillation circuit 1 is operating normally, the detection signal 11
Is at a low level, and the reset signal 9 is
When the reset signal 9 has a pulse width equal to or larger than the set value, the semiconductor device is initialized.
【００１８】発振回路１が停止している場合は検出信号
１１は高レベルとなり、リセット信号９はノイズ除去回
路８を介さずリセット信号９のパルス幅によらず半導体
装置の初期化を行う。When the oscillation circuit 1 is stopped, the detection signal 11 goes high, and the reset signal 9 initializes the semiconductor device regardless of the pulse width of the reset signal 9 without passing through the noise removing circuit 8.
【００１９】発振回路１が停止している場合としては電
源投入時や電源電圧低下時が考えられ、このような場合
はリセット信号９のノイズによる誤動作より半導体装置
の初期化が重要となる。The oscillation circuit 1 may be stopped when the power is turned on or when the power supply voltage drops. In such a case, the initialization of the semiconductor device is more important than the malfunction due to the noise of the reset signal 9.
【００２０】[0020]
【発明の効果】以上述べたように本発明によれば発振回
路が発振状態によらずリセット信号での初期化が確実に
行える。As described above, according to the present invention, the initialization by the reset signal can be reliably performed regardless of the oscillation state of the oscillation circuit.
【００２１】また電源投入時の初期化がＣＲの時定数な
ど短いパルス幅のリセット信号で行え、初期化のための
外付け回路が簡略化できる。Further, initialization at the time of power-on can be performed by a reset signal having a short pulse width such as a CR time constant, and an external circuit for initialization can be simplified.
【図１】本発明の半導体装置の一実施例のブロック図を
示す。FIG. 1 is a block diagram showing one embodiment of a semiconductor device of the present invention.
【図２】従来の半導体装置のブロック図を示す。FIG. 2 shows a block diagram of a conventional semiconductor device.
１‥‥‥発振回路 ２‥‥‥基準信号 ３‥‥‥分周回路 ４‥‥‥第一の分周信号 ５‥‥‥第二の分周信号 ６‥‥‥発振停止検出回路 ７‥‥‥入力端子 ８‥‥‥ノイズ除去回路 ９‥‥‥リセット信号 １０‥‥‥初期化信号 １１‥‥‥検出信号 １２‥‥‥第一の初期化信号 １３‥‥‥バイパス回路 1 oscillator circuit 2 reference signal 3 divider circuit 4 first divider signal 5 second divider signal 6 oscillation stop detection circuit 7 ‥ Input terminal 8 ‥‥‥ Noise removal circuit 9 ‥‥‥ Reset signal 10 ‥‥‥ Initialization signal 11 ‥‥‥ Detection signal 12 ‥‥‥ First initialization signal 13 ‥‥‥ Bypass circuit
Claims (1)
路と、 ｃ）前記基準信号または前記分周信号を入力し、前記発
振回路の動作状態を検出する発振停止検出回路と、 ｄ）リセット信号を入力する入力端子と、 ｅ）前記リセット信号と前記発振信号または前記分周信
号を入力し、前記リセット信号が設定値以上のパルス幅
の時初期化信号を出力するノイズ除去回路とを少なくと
も具備する半導体装置に於いて、 ｆ）前記発振停止検出回路で発振停止が検出された場
合、前記リセット信号を前記ノイズ除去回路を介さずに
初期化信号とすることを特徴とする半導体装置。A) an oscillation circuit for outputting a reference signal; b) a frequency divider for dividing the reference signal and outputting a frequency-divided signal; c) inputting the reference signal or the frequency-divided signal; An oscillation stop detection circuit for detecting an operation state of the oscillation circuit; d) an input terminal for inputting a reset signal; e) inputting the reset signal and the oscillation signal or the frequency division signal, and setting the reset signal. A noise elimination circuit that outputs an initialization signal when the pulse width is equal to or greater than a value. F) When oscillation stop is detected by the oscillation stop detection circuit, the reset signal is converted to the noise elimination signal. A semiconductor device, wherein an initialization signal is used without passing through a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22415891A JP2906757B2 (en) | 1991-09-04 | 1991-09-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22415891A JP2906757B2 (en) | 1991-09-04 | 1991-09-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0563530A JPH0563530A (en) | 1993-03-12 |
| JP2906757B2 true JP2906757B2 (en) | 1999-06-21 |
Family
ID=16809445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22415891A Expired - Fee Related JP2906757B2 (en) | 1991-09-04 | 1991-09-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2906757B2 (en) |
-
1991
- 1991-09-04 JP JP22415891A patent/JP2906757B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0563530A (en) | 1993-03-12 |
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