JP2897088B2 - Manufacturing method and mounting structure of chip parts - Google Patents
Manufacturing method and mounting structure of chip partsInfo
- Publication number
- JP2897088B2 JP2897088B2 JP3201353A JP20135391A JP2897088B2 JP 2897088 B2 JP2897088 B2 JP 2897088B2 JP 3201353 A JP3201353 A JP 3201353A JP 20135391 A JP20135391 A JP 20135391A JP 2897088 B2 JP2897088 B2 JP 2897088B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- chip component
- electrode
- forming surface
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Details Of Resistors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップ部品の実装・接
続方式に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting and connecting chip components.
【０００２】[0002]
【従来の技術】図７にはコンデンサ、抵抗等の一般的な
チップ部品の斜視図が示されている。このチップ部品１
の両端側に一対の外部電極２が形成されている。この外
部電極２は上面電極４と、底面電極５と、前後電極１０
と、側面電極３とが一体的に接続されたものである。こ
のチップ部品１を回路基板７に搭載し、半田９で接続し
た状態が図８に示されている。図９にはチップ部品１の
底面電極５と基板７側の導体部であるランド８の関係が
示されており、底面電極５に対してランド８が大きくは
み出している。このはみ出し部分を利用してチップ部品
１とランド８とを図８に示すように半田フィレット（半
田の盛り上がり形状）６を形成することによって接続し
ている。2. Description of the Related Art FIG. 7 is a perspective view of a general chip component such as a capacitor and a resistor. This chip part 1
A pair of external electrodes 2 are formed at both ends of the. The external electrode 2 includes a top electrode 4, a bottom electrode 5, and front and rear electrodes 10.
And the side electrode 3 are integrally connected. FIG. 8 shows a state in which the chip component 1 is mounted on the circuit board 7 and connected by the solder 9. FIG. 9 shows the relationship between the bottom electrode 5 of the chip component 1 and the land 8 which is a conductor on the substrate 7 side, and the land 8 protrudes greatly from the bottom electrode 5. The protruding portion is used to connect the chip component 1 and the land 8 by forming a solder fillet (bump shape of solder) 6 as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、基板７
側のランド８の大きさが、チップ部品１に対して非常に
大きく設けられており、また、半田フィレット６がチッ
プ部品１から外に大きく突き出しているので、他の回路
素子をチップ部品１に近接配置できず、高密度実装の障
害となっている。However, the substrate 7
The size of the land 8 on the side is provided to be very large with respect to the chip component 1 and the solder fillet 6 protrudes greatly from the chip component 1, so that other circuit elements are attached to the chip component 1. They cannot be placed close to each other, which is an obstacle to high-density mounting.
【０００４】また、半田フィレット６を形成してチップ
部品１と回路基板７とを接続する方式は、半田９の供給
量や形状がばらついて変わり易く、コントロールが難し
く半田接続の信頼性の上でも問題がある。Further, the method of forming the solder fillet 6 to connect the chip component 1 and the circuit board 7 is apt to change due to variations in the supply amount and shape of the solder 9 and is difficult to control, so that the solder connection reliability is high. There's a problem.
【０００５】本発明は上記従来の課題を解決するために
なされたものであり、その目的は、回路基板へチップ部
品を実装接続する際に、高密度実装、高信頼性接続ので
きるチップ部品の製造方法と実装構造を提供することに
ある。[0005] The present invention has been made to solve the conventional problems, and its object is in mounting connecting the chip component to a circuit board, high-density mounting, tip parts which can secure connection to provide a method of manufacturing the mounting structure.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するために、次のように構成されている。すなわち、本
発明のチップ部品の実装構造は、チップ部品の少なくと
も底面に少なくとも一対の底面電極を形成し、これら底
面電極領域にそれぞれ半田形成面を設け、この半田形成
面以外の電極表面を半田になじまない半田排除面とし、
回路基板側には前記チップ部品が載置される導体のラン
ドがチップ部品からはみ出ない大きさで形成されてお
り、このランド上にチップ部品の半田形成面が載せら
れ、半田形成面に形成された半田によってチップ部品が
ランドに半田接続されていることを特徴として構成され
ている。さらに、本発明のチップ部品の第１の製造方法
は、チップ部品の少なくとも底面に少なくとも一対の底
面電極を形成し、これら底面電極の領域をそれぞれマス
クで覆った後に電極の表面を半田レジストで覆い、然る
後に前記マスクを除去して電極表面を露出し、その電極
の露出部に半田膜を形成することを特徴として構成され
ている。さらに、本発明のチップ部品の第２の製造方法
は、チップ部品の少なくとも底面に半田になじまない金
属層で少なくとも一対の底面電極を形成し、然る後にこ
れら底面電極の領域に半田になじむ金属層を設けて半田
形成面を形成し、この半田形成面上に半田膜を形成する
ことを特徴として構成されている。The present invention is configured as follows to achieve the above object. That is , in the mounting structure of the chip component of the present invention, at least a pair of bottom electrodes are formed on at least the bottom surface of the chip component, and solder forming surfaces are provided in these bottom electrode regions, respectively. The surface is a solder removal surface that does not fit into the solder,
On the circuit board side, a land of the conductor on which the chip component is mounted is formed in a size that does not protrude from the chip component, and the solder forming surface of the chip component is placed on this land and formed on the solder forming surface. The chip component is solder-connected to the land by the solder. Further, in the first method of manufacturing a chip component according to the present invention, at least a pair of bottom electrodes are formed on at least the bottom surface of the chip component, and the surfaces of the bottom electrodes are respectively covered with a mask, and then the surfaces of the electrodes are covered with a solder resist. Thereafter, the mask is removed to expose the electrode surface, and a solder film is formed on the exposed portion of the electrode. Further, in the second method for manufacturing a chip component according to the present invention, at least a pair of bottom electrodes are formed on at least the bottom surface of the chip component with a metal layer that does not fit into the solder, and then the metal that fits the solder in the region of these bottom electrodes. A layer is provided to form a solder forming surface, and a solder film is formed on the solder forming surface.
【０００７】[0007]
【作用】上記構成の本発明において、チップ部品の底面
に形成した電極の領域に半田形成面を形成し、その周囲
に半田排除面を設ける。一方、チップ部品搭載の回路基
板のランドを前記チップ部品からはみ出さない大きさに
形成し、半田形成面をランドと対向させてチップ部品を
ランドに搭載し、半田形成面とランドとを半田接続す
る。In the present invention having the above-described structure, a solder forming surface is formed in the region of the electrode formed on the bottom surface of the chip component, and a solder removing surface is provided around the surface. On the other hand, the land of the circuit board on which the chip component is mounted is formed so as not to protrude from the chip component, the chip component is mounted on the land with the solder forming surface facing the land, and the solder forming surface and the land are connected by soldering. I do.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１には本発明の製造方法と実装構造の対象とな
るチップ部品の要部構成図が示されている。このチップ
部品１の両端側には従来例と同様に一対の外部電極２が
形成されており、この外部電極２の底面電極５の白抜き
部分が、このチップ部品１の半田形成面１１を構成する
もので、この半田形成面１１の形状は様々な形態を採る
ことができ、例えば、図１の（ａ）の半田形成面１１は
矩形状を呈しており、その半田形成面１１以外の外部電
極２の電極表面、つまり、図１の（ａ）に示す底面電極
５の斜線領域と、上面電極４と、前後電極１０と、側面
電極３との各電極表面には半田レジスト１２等の半田排
除面が形成されている。図１の（ｂ）は円形の半田形成
面１１を左右２個ずつ計４個設けたもので、この方式
は、チップ部品１を回路基板７のランド８に搭載する際
に４つの支点があるので載置状態が最も安定し、半田接
続作業を安定に行うことができる。図１の（ｃ）の半田
形成面１１はさらに他の形態例を示したものである。そ
して、これら各半田形成面１１には適宜の手段により半
田膜が形成されている。Embodiments of the present invention will be described below with reference to the drawings. It has been shown to block diagram illustrating the principal components of a target Do <br/> Ru chip component manufacturing method as mounting structure of the present invention in FIG. A pair of external electrodes 2 are formed on both end sides of the chip component 1 as in the conventional example, and a white portion of the bottom electrode 5 of the external electrode 2 forms a solder forming surface 11 of the chip component 1. The shape of the solder forming surface 11 can take various forms. For example, the solder forming surface 11 in FIG. The electrode surface of the electrode 2, that is, the hatched area of the bottom electrode 5, the upper electrode 4, the front and rear electrodes 10, and the side electrodes 3 shown in FIG. An exclusion surface is formed. FIG. 1B shows a case in which two circular solder forming surfaces 11 are provided, two on each of the left and right sides. In this method, there are four fulcrums when the chip component 1 is mounted on the lands 8 of the circuit board 7. Therefore, the mounting state is most stable, and the solder connection work can be stably performed. The solder forming surface 11 in FIG. 1C shows another embodiment. A solder film is formed on each of the solder forming surfaces 11 by an appropriate means.
【０００９】図２には前記のチップ部品１を回路基板７
に搭載して半田接続した本発明に係る実装構造が示され
ている。このチップ部品１を実装接続するための回路基
板７側には、導体層としてのランド８が、チップ部品１
をはみ出さない大きさで形成されている。このランド８
上には半田形成面１１をランド８に対向させてチップ部
品１をランド８に搭載し、適宜の加熱手段等によって、
半田形成面１１に形成されている半田膜を溶融して半田
形成面１１とランド８とを半田接続している。上記のよ
うにチップ部品１と基板７とを半田接続する際に、半田
９は外部電極２の表面に形成された半田排除面には付着
せず、したがって、半田排除面から外にはみ出すことが
なく、半田形成面１１とランド８とが、チップ部品１の
大きさ内で半田接続されることとなり、半田の量や形状
もばらつきなく、安定した信頼性の高い半田接続が可能
となる。FIG. 2 shows that the above-mentioned chip component 1 is
1 shows a mounting structure according to the present invention, which is mounted and soldered. A land 8 as a conductor layer is provided on the circuit board 7 side for mounting and connecting the chip component 1.
Is formed so as not to protrude. This land 8
The chip component 1 is mounted on the land 8 with the solder forming surface 11 opposed to the land 8 on the top, and the heating is performed by appropriate heating means or the like.
The solder film formed on the solder forming surface 11 is melted and the solder forming surface 11 and the land 8 are connected by soldering. When the chip component 1 and the substrate 7 are connected by soldering as described above, the solder 9 does not adhere to the solder exclusion surface formed on the surface of the external electrode 2 and therefore may protrude from the solder exclusion surface. Instead, the solder forming surface 11 and the lands 8 are connected by soldering within the size of the chip component 1, so that the amount and shape of the solder are not varied and stable and reliable soldering is possible.
【００１０】次に、本発明に係るチップ部品の製造方法
例を図面に基づいて説明する。図３〜図５は第１の実施
例の製造方法を示すもので、まず、チップ部品１の底面
電極５の局部領域、例えば円形の白抜き部（図３の
（ａ））にマスクとして機能する低融点（６０℃程度）
のパラフィン系ワックス１３の融液をディスペンサ等に
よって塗布する。このワックス１３を塗布したチップ部
品１を半田レジスト１２に常温で浸漬して引き上げた
後、レジスト１２を乾燥硬化する。この状態が図４の
（ａ）に示されている。このチップ部品１を熱風等によ
って加熱して、ワックス１３を除去すると、図４の
（ｂ）に示すように局部領域の電極表面１６が露出され
て、半田形成面１１を得る。この半田形成面１１の周り
は半田レジスト１２の半田排除面となる。次いで、この
チップ部品を溶融している半田浴中に浸漬して引き上げ
ると図５に示すように、露出した電極表面１６に半田９
が形成される。Next, an example of a method for manufacturing a chip component according to the present invention will be described with reference to the drawings. FIGS. 3 to 5 show a manufacturing method of the first embodiment. First, a local region of the bottom electrode 5 of the chip component 1, for example, a circular white portion (FIG. 3A) functions as a mask. Low melting point (about 60 ° C)
Is applied by a dispenser or the like. The chip component 1 coated with the wax 13 is immersed in the solder resist 12 at normal temperature and pulled up, and then the resist 12 is dried and hardened. This state is shown in FIG. When the chip 13 is heated by hot air or the like to remove the wax 13, the electrode surface 16 in the local region is exposed as shown in FIG. The periphery of the solder forming surface 11 becomes a solder removal surface of the solder resist 12. Then, as shown in FIG. 5 by pulling by immersion in a solder bath which melts the chip components, the solder on the electrode surface 16 exposed 9
Is formed.
【００１１】本実施例では、チップ部品１の底面電極５
の半田形成面１１の周りを半田排除面としたので、チッ
プ部品を半田浴中に浸漬して引き上げるとき、半田形成
面に付着した半田は半田排除面を通って流出することが
なく、半田形成面上に定量の半田９が溜められた状態と
なるので、半田量を一定量にコントロールすることがで
きる。In this embodiment, the bottom electrode 5 of the chip component 1
Since the periphery of the solder forming surface 11 is used as the solder removing surface, when the chip component is immersed in the solder bath and pulled up, the solder attached to the solder forming surface does not flow out through the solder removing surface. Since a certain amount of solder 9 is stored on the surface, the amount of solder can be controlled to a constant amount.
【００１２】次に、チップ部品の製造方法の第２の実施
例を図６に基づいて説明する。本実施例は半田レジスト
１２の替わりに半田９になじまない金属層を利用して半
田排除面を形成するもので、まず、チップ部品１の両端
側に設けた一対の外部電極２の表面に半田９になじまな
い金属、例えばクロム１４等をメッキして電極表面に半
田排除面を形成する。次いで、底面電極５の局部領域、
つまり、半田排除面の局部領域に半田９になじむ金属、
例えば銅又はニッケル等の金属層１５を形成して半田形
成面１１を作り、この半田形成面１１を半田浴にディッ
プして、半田形成面１１上に半田９を形成し、チップ部
品１を作製する。Next, a second embodiment of a method for manufacturing a chip component will be described with reference to FIG. In this embodiment, a solder excluding surface is formed by using a metal layer which does not fit into the solder 9 instead of the solder resist 12. First, the surface of a pair of external electrodes 2 provided on both ends of the chip component 1 is soldered. A metal which is not compatible with 9, for example, chrome 14 or the like is plated to form a solder removal surface on the electrode surface. Next, a local region of the bottom electrode 5,
In other words, a metal that is compatible with the solder 9 in a local area of the solder removal surface,
For example, a metal layer 15 such as copper or nickel is formed to form a solder forming surface 11, the solder forming surface 11 is dipped in a solder bath, and the solder 9 is formed on the solder forming surface 11 to produce the chip component 1. I do.
【００１３】なお、本発明は、上記実施例に限定される
ことはなく、様々な実施の態様を採り得る。例えば上記
各例では底面電極５の局部領域に半田形成面を形成した
が、底面電極の全面を半田形成面としてもよい。この場
合においても底面電極以外の電極部分は半田排除面とな
っているので、半田が半田排除面側にはみ出し付着して
フィレットが生じることがなく、チップ部品を良好に基
板側のランドに接続することができる。Note that the present invention is not limited to the above-described embodiment, but can adopt various embodiments. For example, although the solder forming surface is formed in the local region of the bottom electrode 5 in each of the above examples, the entire surface of the bottom electrode may be used as the solder forming surface. Also in this case, since the electrode portion other than the bottom electrode is a solder exclusion surface, the solder does not protrude and adhere to the solder exclusion surface side so that no fillet is generated, and the chip component is connected to the land on the board side satisfactorily. be able to.
【００１４】また、本実施例の図３の例では底面電極５
の局部領域のマスク材としてパラフィン系低融点ワック
ス１３を用いたが、高融点ワックスやこれに類似の撥水
性マスク材を用いてもよい。In the embodiment shown in FIG.
Although the paraffin-based low-melting wax 13 is used as the mask material for the local region, a high-melting wax or a similar water-repellent mask material may be used.
【００１５】また、図６の例では半田排除金属としてク
ロム１４を用いたが、これを半田９になじまない金属で
あれば、その他の金属又は金属化合物を用いてもよい。In the example of FIG. 6, chromium 14 is used as the solder-excluded metal. However, any other metal or metal compound may be used as long as it does not fit into the solder 9.
【００１６】さらに、同実施例ではクロム１４をメッキ
によって金属層を形成したが、半田９になじまない金属
層を蒸着等によって形成してもよい。Further, in the embodiment, the metal layer is formed by plating chromium 14, but a metal layer which does not fit in the solder 9 may be formed by vapor deposition or the like.
【００１７】さらに、上記実施例では半田形成面１１に
半田膜１７を形成したチップ部品を作製しているが、半
田膜１７を除いたチップ部品の作製でもよく、この場合
には、ランド８上に半田クリーム等を塗布して、半田接
続に際して加熱溶融する。Further, in the above embodiment, a chip component in which the solder film 17 is formed on the solder forming surface 11 is manufactured, but a chip component in which the solder film 17 is removed may be manufactured. Is applied and soldered and melted at the time of solder connection.
【００１８】さらに、上記実施例ではチップ部品１の電
極金属表面上に半田排除面を形成したが、電極を半田に
なじまない導体金属によって形成して電極自体を半田排
除面とし、この半田排除面上に半田形成面を形成しても
よい。Further, in the above embodiment, the solder exclusion surface is formed on the electrode metal surface of the chip component 1. However, the electrode itself is used as a solder exclusion surface by forming the electrode with a conductive metal that does not fit into the solder. A solder forming surface may be formed thereon.
【００１９】[0019]
【発明の効果】本発明は、チップ部品の両端側に形成さ
れている外部電極のうち、回路基板に接続する底面電極
の領域に半田形成面を形成し、この半田形成面以外の外
部電極部には半田になじまない半田排除面を形成した構
成としたので、半田の溶融時に、溶融した半田は底面電
極の半田形成面には付着するが、半田の濡れ性に起因し
て半田排除面には付着しないことから、半田形成面から
溶融半田が流れ出て半田形成面以外の外部電極表面に半
田が漏洩付着することを防止することができる。このこ
とから、半田形成面の面積によって半田量を、また、半
田形成面の形状によって半田形状をそれぞれ制御するこ
とが可能となり、つまり、半田量および半田形状のコン
トロールが容易となるので、高信頼性の半田実装接続が
できる。According to the present invention, among the external electrodes formed on both ends of a chip component, a solder forming surface is formed in a region of a bottom electrode connected to a circuit board, and an external electrode portion other than the solder forming surface is formed. Has a solder removal surface that is not compatible with solder. Since no solder adheres, it is possible to prevent the molten solder from flowing out from the solder forming surface and preventing the solder from leaking and attaching to the external electrode surface other than the solder forming surface. This makes it possible to control the amount of solder by the area of the solder forming surface and the shape of the solder by the shape of the solder forming surface. In other words, it is easy to control the amount of solder and the shape of the solder, so that high reliability is achieved. Solder connection.
【００２０】また、上記の如く、チップ部品の外部電極
の底面電極に半田形成面を設け、この半田形成面以外の
外部電極表面を半田排除面に形成したので、半田は外部
電極のうち、底面電極の半田形成面のみに付着形成され
ることになるから、その半田形成面の半田に対応する回
路基板の領域だけに回路基板側の導体部としてのランド
を設ければよく、つまり、回路基板のランドをチップ部
品からはみ出して形成する必要がなく、回路基板のラン
ドをチップ部品からはみ出さない大きさに形成すること
ができる。Further, as described above, the solder forming surface is provided on the bottom electrode of the external electrode of the chip component, and the surface of the external electrode other than the solder forming surface is formed on the solder exclusion surface. Since the electrodes are formed only on the solder forming surface of the electrodes, it is sufficient to provide lands as conductors on the circuit board only in the region of the circuit board corresponding to the solder on the solder forming surface. It is not necessary to form the land protruding from the chip component, and the land of the circuit board can be formed in a size that does not protrude from the chip component.
【００２１】このように、チップ部品の底面電極に半田
形成面を形成し該半田形成面以外の外部電極表面を半田
排除面に形成し、回路基板のランドをチップ部品からは
み出さない大きさに形成することによって、底面電極の
半田形成面と回路基板のランドとの間に半田を挟み込む
形態でチップ部品を回路基板に半田接続実装することが
可能となる。すなわち、半田形成面と回路基板のランド
との間に挟み込まれた半田の溶融時に、溶融した半田は
半田の濡れ性に起因して半田形成面とランドだけに付着
し、半田排除面やランド周辺の回路基板表面には漏洩付
着しないので、溶融半田が半田形成面とランドの間か
ら、例えば、チップ部品の側面に形成された外部電極の
側面電極に回り込んで付着することはなく、すなわち、
チップ部品と回路基板間のみに半田を形成することがで
き、従来のように半田がチップ部品から外に大きくはみ
出した形態でチップ部品を回路基板に実装する場合に比
べて、チップ部品から半田や回路基板のランドがはみ出
さない分、チップ部品を他の回路素子との間隔を狭めて
実装することができ、回路基板の高密度実装を達成させ
ることが可能となる。As described above, the solder forming surface is formed on the bottom electrode of the chip component, the external electrode surface other than the solder forming surface is formed on the solder exclusion surface, and the size of the land of the circuit board does not protrude from the chip component. By forming the chip component, it is possible to solder-mount the chip component on the circuit board in a form in which the solder is sandwiched between the solder forming surface of the bottom electrode and the land of the circuit board. That is, when the solder sandwiched between the solder forming surface and the land of the circuit board is melted, the melted solder adheres only to the solder forming surface and the land due to the wettability of the solder, and the solder removing surface and the periphery of the land are melted. Since the molten solder does not adhere to the surface of the circuit board, the molten solder does not wrap around and attach to the side electrodes of the external electrodes formed on the side surfaces of the chip components, for example, between the solder forming surface and the lands.
Solder can be formed only between the chip component and the circuit board, and compared to the case where the chip component is mounted on the circuit board with the solder largely protruding out of the chip component as in the related art, the solder amount that the land does not protrude the circuit board, can be implemented by narrowing the intervals of the switch-up components and other circuit elements, it becomes possible to achieve high density mounting of the circuit board.
【図１】本発明に係る製造方法と実装構造の対象となる
チップ部品の要部構成例の説明図である。FIG. 1 is an explanatory diagram of a configuration example of a main part of a chip component to be subjected to a manufacturing method and a mounting structure according to the present invention.
【図２】同チップ部品を回路基板に搭載し半田接続した
実装状態の説明図である。FIG. 2 is an explanatory diagram of a mounting state in which the chip component is mounted on a circuit board and connected by soldering.
【図３】同チップ部品の第１の製造方法の工程におい
て、底面電極に半田形成面を形成するためのマスクを施
した状態の説明図である。FIG. 3 is an explanatory view showing a state in which a mask for forming a solder forming surface is applied to a bottom electrode in a step of a first manufacturing method of the chip component.
【図４】図３の工程後、底面電極の表面に半田レジスト
を形成する工程と、マスクを除去して半田形成面を形成
する工程の説明図である。FIG. 4 is an explanatory view of a step of forming a solder resist on the surface of the bottom electrode after the step of FIG. 3 and a step of forming a solder formation surface by removing a mask.
【図５】図４の状態からチップ部品の半田形成面に半田
膜を形成した状態の説明図である。FIG. 5 is an explanatory view of a state in which a solder film is formed on a solder forming surface of the chip component from the state of FIG. 4;
【図６】同チップ部品の製造方法の第２の実施例の説明
図である。FIG. 6 is an explanatory view of a second embodiment of the method of manufacturing the chip component.
【図７】従来のチップ部品の斜視図である。FIG. 7 is a perspective view of a conventional chip component.
【図８】同チップ部品と回路基板とを半田接続した状態
の説明図である。FIG. 8 is an explanatory diagram of a state where the chip component and a circuit board are connected by soldering.
【図９】同チップ部品の底面電極と基板側のランドとの
関係を示す説明図である。FIG. 9 is an explanatory diagram showing a relationship between a bottom electrode of the chip component and a land on the substrate side.
１ チップ部品 ２ 外部電極 ５ 底面電極 ６ 半田フィレット ７ 回路基板 １１ 半田形成面 １２ 半田レジスト １３ ワックス １４ クロム（半田排除面） DESCRIPTION OF SYMBOLS 1 Chip component 2 External electrode 5 Bottom electrode 6 Solder fillet 7 Circuit board 11 Solder forming surface 12 Solder resist 13 Wax 14 Chrome (Solder excluding surface)
Claims (3)
も一対の底面電極を形成し、これら底面電極領域にそれ
ぞれ半田形成面を設け、この半田形成面以外の電極表面
を半田になじまない半田排除面とし、回路基板側には前
記チップ部品が載置される導体のランドがチップ部品か
らはみ出ない大きさで形成されており、このランド上に
チップ部品の半田形成面が載せられ、半田形成面に形成
された半田によってチップ部品がランドに半田接続され
ているチップ部品の実装構造。 At least a pair of bottom electrodes are formed on at least the bottom surface of the chip component, and solder formation surfaces are provided in these bottom electrode regions, respectively, and the electrode surface other than the solder formation surface is a solder exclusion surface that does not adapt to solder. On the circuit board side, a land of the conductor on which the chip component is mounted is formed in a size that does not protrude from the chip component, and the solder forming surface of the chip component is placed on this land and formed on the solder forming surface. The mounting structure of chip components where the chip components are soldered to the lands by solder.
も一対の底面電極を形成し、これら底面電極の領域をそ
れぞれマスクで覆った後に電極の表面を半田レジストで
覆い、然る後に前記マスクを除去して電極表面を露出
し、その電極の露出部に半田膜を形成するチップ部品の
製造方法。 2. At least a pair of bottom electrodes are formed on at least the bottom surface of the chip component, the surfaces of the bottom electrodes are respectively covered with a mask, the surfaces of the electrodes are covered with a solder resist, and then the mask is removed. A method for manufacturing a chip component, in which an electrode surface is exposed and a solder film is formed on an exposed portion of the electrode.
じまない金属層で少なくとも一対の底面電極を形成し、
然る後に底面電極の領域に半田になじむ金属層を設けて
半田形成面を形成し、この半田形成面上に半田膜を形成
するチップ部品の製造方法。 3. At least a pair of bottom electrodes are formed on at least the bottom surface of the chip component with a metal layer that does not fit into solder.
Thereafter, a method of manufacturing a chip component in which a metal layer compatible with solder is provided in the area of the bottom electrode to form a solder forming surface, and a solder film is formed on the solder forming surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3201353A JP2897088B2 (en) | 1991-07-16 | 1991-07-16 | Manufacturing method and mounting structure of chip parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3201353A JP2897088B2 (en) | 1991-07-16 | 1991-07-16 | Manufacturing method and mounting structure of chip parts |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10314099A Division JPH11251177A (en) | 1998-10-16 | 1998-10-16 | Chip component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0521260A JPH0521260A (en) | 1993-01-29 |
| JP2897088B2 true JP2897088B2 (en) | 1999-05-31 |
Family
ID=16439633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3201353A Expired - Lifetime JP2897088B2 (en) | 1991-07-16 | 1991-07-16 | Manufacturing method and mounting structure of chip parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2897088B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3152834B2 (en) * | 1993-06-24 | 2001-04-03 | 株式会社東芝 | Electronic circuit device |
| JP2005251904A (en) * | 2004-03-03 | 2005-09-15 | Denso Corp | Substrate front surface mounting part, substrate circuit, substrate, solder connecting method and method of manufacturing substrate circuit |
| JP5403344B2 (en) | 2009-07-14 | 2014-01-29 | 株式会社リコー | Sheet material and image forming apparatus |
| JP6357740B2 (en) * | 2013-08-27 | 2018-07-18 | Tdk株式会社 | Ceramic electronic components |
| JP6229371B2 (en) * | 2013-08-27 | 2017-11-15 | Tdk株式会社 | Ceramic electronic components |
| JP6233397B2 (en) * | 2015-12-16 | 2017-11-22 | Tdk株式会社 | Solder mounting structure for ceramic electronic components |
| JP6508156B2 (en) * | 2016-09-26 | 2019-05-08 | 株式会社村田製作所 | Method of manufacturing laminated electronic component |
| JP7358692B2 (en) * | 2018-06-15 | 2023-10-11 | サムソン エレクトロ－メカニックス カンパニーリミテッド． | Capacitor parts and capacitor parts manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3056121U (en) * | 1998-07-24 | 1999-02-12 | 逸郎 米永 | Advertising display device |
-
1991
- 1991-07-16 JP JP3201353A patent/JP2897088B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521260A (en) | 1993-01-29 |
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