JP2893522B2 - BGA semiconductor package and manufacturing method thereof - Google Patents

BGA semiconductor package and manufacturing method thereof

Info

Publication number
JP2893522B2
JP2893522B2 JP34808096A JP34808096A JP2893522B2 JP 2893522 B2 JP2893522 B2 JP 2893522B2 JP 34808096 A JP34808096 A JP 34808096A JP 34808096 A JP34808096 A JP 34808096A JP 2893522 B2 JP2893522 B2 JP 2893522B2
Authority
JP
Japan
Prior art keywords
chip
semiconductor chip
groove
connection
shortened
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP34808096A
Other languages
Japanese (ja)
Other versions
JPH09186267A (en
Inventor
スン キム ジン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ERU JII SEMIKON CO Ltd
Original Assignee
ERU JII SEMIKON CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ERU JII SEMIKON CO Ltd filed Critical ERU JII SEMIKON CO Ltd
Publication of JPH09186267A publication Critical patent/JPH09186267A/en
Application granted granted Critical
Publication of JP2893522B2 publication Critical patent/JP2893522B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＢＧＡ（ball gri
d array ）半導体パッケージ及びその製造方法に係るも
ので、詳しくは、半導体チップと外部装置との電気的接
続を短縮した接続層を設けて行うようにして半導体パッ
ケージを薄型化させ、半導体素子のアクセス時間を短縮
して高速素子（high speed device ）に適用し得るよう
にしたＢＧＡ半導体パッケージ及びその製造方法に関す
るものである。TECHNICAL FIELD The present invention relates to a BGA (ball gri
d array) The present invention relates to a semiconductor package and a method for manufacturing the same. More specifically, the semiconductor package is thinned by providing a connection layer in which electrical connection between a semiconductor chip and an external device is shortened, and access to a semiconductor element is performed. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA semiconductor package which can be applied to a high speed device with a reduced time, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】従来、ＢＧＡ半導体パッケージにおいて
は、図４に示すように、金属パターン３が内部に埋設さ
れた基板１上に半導体チップ５が接着剤４によりダイボ
ンディングされ、該半導体チップ５上のチップパッド
（図示されず）がワイヤ７により前記基板１内の金属パ
ターン３と電気的に接続されている。かつ、前記半導体
チップ５及びワイヤ７の包含された基板１上所定部位が
エポキシモールディング樹脂６により覆われ、前記基板
１の下面に複数個の導電パッド２が形成され、それら導
電パッド２下面にリフロー工程により夫々ソルダボール
８が付着されて構成されていた。2. Description of the Related Art Conventionally, in a BGA semiconductor package, as shown in FIG. 4, a semiconductor chip 5 is die-bonded with an adhesive 4 on a substrate 1 in which a metal pattern 3 is embedded. Chip pads (not shown) are electrically connected to the metal patterns 3 in the substrate 1 by wires 7. A predetermined portion of the substrate 1 including the semiconductor chip 5 and the wires 7 is covered with an epoxy molding resin 6, and a plurality of conductive pads 2 are formed on the lower surface of the substrate 1. The solder balls 8 were adhered by the respective steps.

【０００３】そして、前記ＢＧＡ半導体パッケージは、
印刷回路基板（図示されず）に上記各ソルダボール８に
より実装され所定情報を貯蔵、又は、該貯蔵情報を読み
取るようになっていた。[0003] The BGA semiconductor package comprises:
Storing predetermined information is a printed circuit board (not shown) implemented by the respective solder balls 8, or was supposed to read the reservoir information.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のＢＧＡ半導体パッケージにおいては、出力端
子として用いるソルダボールが半導体チップの活性表面
（acctive surface ；半導体チップの上面）の反対側に
位置されるため、半導体チップからワイヤを経て印刷回
路基板まで至る電気的経路が長くなってアクセス時間も
長くなり、半導体パッケージの大きさを縮小させること
が難しくなるという不都合な点があった。However, in such a conventional BGA semiconductor package, a solder ball used as an output terminal is located on the side opposite to the active surface (the upper surface of the semiconductor chip) of the semiconductor chip. Therefore, there is an inconvenience that an electric path from the semiconductor chip to the printed circuit board via the wire becomes longer and an access time becomes longer, which makes it difficult to reduce the size of the semiconductor package.

【０００５】また、ソルダボールを半導体チップの活性
表面上にレイアウトする場合、接続のためのタブボンデ
ィング（TAB bonding ）工程を必要とするため、生産性
が低下して原価が上昇するという不都合な点があった。
本発明の目的は、半導体チップの活性表面上にチップパ
ッドを短縮接続層により電気的に短い経路で接続させて
アクセス時間を減らし、高速素子に適用することが可能
で、かつ、パッケージの大きさを縮小し得るようにした
ＢＧＡ半導体パッケージ及びその製造方法を提供しよう
とするものである。Further, when laying out the solder balls on the active surface of the semiconductor chip, a tab bonding (TAB bonding) step for connection is required, so that the productivity is reduced and the cost is increased. was there.
SUMMARY OF THE INVENTION It is an object of the present invention to reduce the access time by connecting chip pads on the active surface of a semiconductor chip with a short connection layer via an electrically short path, to be applicable to high-speed devices, and to reduce the size of a package. And a method of manufacturing the same.

【０００６】[0006]

【課題を解決するための手段】このような本発明に係る
ＢＧＡ半導体パッケージにおいては、所定深さを有する
溝の形成されたパッケージ本体と、上面にチップパッド
が形成され、前記溝内に接着された半導体チップと、別
途に製作されて、内部には銅膜配線が形成され、上下面
には前記銅膜配線と電気的接続された接続パッドが夫々
形成され、前記上面の接続パッドには出力端子の形成さ
れた短縮接続手段と、該短縮接続手段の下面の接続パッ
ドと前記半導体チップのチップパッドとを接着させる異
方性接着剤と、を備えて構成され、前記溝の内部は樹脂
で密封されたことを特徴とする。また、本発明に係るＢ
ＧＡ半導体パッケージの製造方法においては、所定深さ
を有する溝の形成されたパッケージ本体を準備する工程
と、前記溝内に、形成されたチップパッドが上向きにな
るようにして半導体チップを接着する工程と、内部には
銅膜配線が形成され、上下面には前記銅膜配線と電気的
接続された接続パッドが夫々接続され、前記上面の接続
パッドには出力端子の接続された短縮接続手段を準備す
る工程と、前記半導体チップの上面のチップパッドと前
記短縮接続手段の下面の接続パッドとが整列されるよう
に、異方性接着剤を利用して前記半導体チップと前記短
縮接続手段とを熱圧着させて接着させる工程と、前記溝
内に樹脂を密封する工程と、を順次行うことを特徴とす
る。 The BGA semiconductor package according to the present invention has a predetermined depth.
Package body with groove and chip pad on top
Is formed, and the semiconductor chip bonded in the groove is separated from the semiconductor chip.
The copper film wiring is formed inside,
Has connection pads electrically connected to the copper film wiring, respectively.
Output terminals are formed on the connection pads on the upper surface.
Shortened connecting means, and a connection pad on the lower surface of the shortened connecting means.
To bond the semiconductor chip and the chip pad of the semiconductor chip.
Anisotropic adhesive, and the inside of the groove is made of resin
It is characterized by being sealed with. Further, B according to the present invention
In the method of manufacturing a GA semiconductor package, a predetermined depth
For preparing a package body having a groove formed therein
The chip pads formed in the grooves face upward.
Bonding the semiconductor chip in such a way that
Copper film wiring is formed, and the upper and lower surfaces are electrically connected to the copper film wiring.
The connected connection pads are respectively connected, and the connection on the upper surface is performed.
Prepare short connection means with output terminals on the pads.
And a chip pad on the upper surface of the semiconductor chip.
The connection pads on the underside of the shortened connection means are aligned
The semiconductor chip and the short
Bonding the compression connection means by thermocompression bonding; and
And a step of sealing the resin inside.
You.

【０００７】[0007]

【０００８】[0008]

【０００９】[0009]

【００１０】[0010]

【発明の実施の形態】以下、本発明の実施の形態に対し
説明する。本発明に係るＢＧＡ半導体パッケージ及びそ
の製造方法においては、図１に示すように、プラスチッ
ク又はセラミック材質のパッケージ本体１１内に所定大
きさの溝１１ａが切刻形成され、該溝１１ａ内底面上に
半導体チップ１５がエポキシ接着剤（epoxy adhesive）
１４により接着され、前記半導体チップ１５の活性領域
上面の両側に夫々チップパッド１７が形成され、それら
チップパッド１７と電気的接続される短縮接続手段とし
ての短縮接続層２０が前記半導体チップ１５上に接着フ
ィルム２４により接着されて構成されている。Embodiments of the present invention will be described below. BGA semiconductor package according to the present invention and its
In the method of manufacturing, as shown in FIG. 1, a plastic or ceramic predetermined size of the groove 11a in the package body 11 of material is formed Setsukoku, the semiconductor chip 15 on the groove 11a in the bottom surface epoxy adhesive ( epoxy adhesive)
14, chip pads 17 are respectively formed on both sides of the upper surface of the active region of the semiconductor chip 15, and are used as shortened connection means for electrically connecting to the chip pads 17.
All of the shortened connection layers 20 are bonded to the semiconductor chip 15 by an adhesive film 24.

【００１１】かつ、図２に示すように、前記半導体チッ
プ１５のチップパッド１７と短縮接続層２０とは接着剤
２７により熱圧着されて電気的に接続され、該接着剤２
７の大きさはチップパッド１７の大きさよりもやや小さ
く形成され熱圧着過程中チップパッド１７と容易に整列
（align ）されながら接着されるようになっている。こ
の場合、前記チップパッド１７上にソルダバンプを形成
した後（図示されず）、短縮接続層２０を接着剤２７を
用いて電気的に接続させることもできる。As shown in FIG. 2, the chip pad 17 of the semiconductor chip 15 and the shortened connection layer 20 are electrically connected to each other by thermocompression bonding using an adhesive 27.
The size of the chip 7 is slightly smaller than the size of the chip pad 17 so that the chip 7 can be easily aligned and adhered to the chip pad 17 during the thermocompression bonding process. In this case, after a solder bump is formed on the chip pad 17 (not shown), the shortened connection layer 20 can be electrically connected using an adhesive 27.

【００１２】また、前記短縮接続層２０においては、図
３に示すように、銅膜配線２３が内部に埋設された回路
器２１と、該回路器２１の両側下面に形成され前記銅膜
配線２３に電気的接続される接続パッド（interconnect
ion pad ）２６と、前記回路器２１の上面に所定間隔を
おいて夫々形成され、前記銅膜配線２３に電気的接続さ
れる複数の接続パッドである導電パッド２２と、を備え
ている。In the shortened connection layer 20, as shown in FIG. 3, a circuit device 21 having a copper film wiring 23 buried therein, and the copper film formed on the lower surface on both sides of the circuit device 21 are formed. A connection pad (interconnect) electrically connected to the wiring 23
and ion Pad) 26, are respectively formed at predetermined intervals on the upper surface of the circuit 21, and a, a plurality of conductive pads 22 is a connection pad that is electrically connected to the copper film wires 23.

【００１３】さらに、前記各導電パッド２２上に前記短
縮接続層２０の出力端子（outputterminal ）としてソ
ルダボール２５を付着するか、それら導電パッド２２上
に出力端子としてソルダバンプを形成することもでき
る。そして、前記回路器２１は、フレキシブルプリント
回路器（flexible printcircuitor）が用いられ、該回
路器２１下面に単面又は両面接着フィルム２４が位置さ
れて該接着フィルム２４により短縮接続層２０が半導体
チップ１５上に熱圧着されるようになっており、該接着
フィルム２４は熱硬化性若しくは熱可燒性樹脂フィルム
が用いられる。かつ、前記回路器２１の厚さは５〜４０
０μｍで、接着フィルム２４の厚さは１０〜４００μｍ
である。Further, a solder ball 25 may be attached to each of the conductive pads 22 as an output terminal of the shortened connection layer 20 or a solder bump may be formed on each of the conductive pads 22 as an output terminal. As the circuit device 21, a flexible print circuit is used, and a single-sided or double-sided adhesive film 24 is positioned on the lower surface of the circuit device 21, and the shortened connection layer 20 is formed by the adhesive film 24. The adhesive film 24 is a thermosetting or heat sinterable resin film. Further, the thickness of the circuit device 21 is 5 to 40.
0 μm, the thickness of the adhesive film 24 is 10 to 400 μm
It is.

【００１４】また、前記接着剤２７は、液状の異方性接
着剤（anisotropic conductive adhesive ）又は固体状
の異方性電導膜（anisotropic coductive film）が用い
られ、その厚さは５〜２００μｍで、内部に電導ボール
２８が形成されている。さらに、前記接続パッド２６
は、前記回路器２１の両方側下面にスパッタリング、電
気鍍金（electroplating）、及び蒸発（evaporation ）
中、いずれか一つを施して蒸着され、銅又は銅／金の合
金が用いられ、最大１ｍｍ以下の高さと、０．３ｍｍ以
上の幅とを有している。Further, the adhesive 27 is liquid anisotropic adhesive (anisot ro pic conductive adhesive) or solid anisotropic conductive film (anis ot ropic coductive film) and has a thickness of 5 A conductive ball 28 is formed inside the conductive ball 28. Further, the connection pad 26
Are sputtering, electroplating, and evaporation on the lower surface of both sides of the circuit device 21.
Among them, one of them is deposited and copper or a copper / gold alloy is used, and has a maximum height of 1 mm or less and a width of 0.3 mm or more.

【００１５】そして、前記短縮接続層２０の接続パッド
２６は、前記半導体チップ１５上のチップパッド１７上
に前記接着剤２７により接着され、それら短縮接続層２
０とチップパッド１７との電気的経路が形成されてい
る。かつ、前記短縮接続層２０は、半導体チップ１５の
活性領域上に前記接着フィルム２４により熱圧着され、
それら半導体チップ１５及び短縮接続層２０の収納され
た前記パッケージ本体１１の溝１１ａ内空間部位はモー
ルディング樹脂１６により密封されている。The connection pads 26 of the shortened connection layer 20 are adhered to the chip pads 17 on the semiconductor chip 15 by the adhesive 27.
An electric path between the chip pad 17 and the chip pad 17 is formed. And the shortened connection layer 20 is thermocompression-bonded on the active region of the semiconductor chip 15 by the adhesive film 24;
The space inside the groove 11 a of the package body 11 in which the semiconductor chip 15 and the shortened connection layer 20 are accommodated is sealed with a molding resin 16.

【００１６】[0016]

【発明の効果】以上説明したように本発明に係るＢＧＡ
半導体パッケージ及びその製造方法においては、半導体
チップの活性領域上にチップパッドと電気的接続する短
縮接続手段が形成されているため、信号のアクセス時間
を短縮させて、高速素子に適用するようになるという効
果がある。As described above, the BGA according to the present invention
In a semiconductor package and a method of manufacturing the same , since a shortening connection means for electrically connecting to a chip pad is formed on an active region of a semiconductor chip, a signal access time is shortened and the present invention is applied to a high-speed element. This has the effect.

【００１７】かつ、前記短縮接続層の接着剤とチップパ
ッドとが直接接続されるため、半導体チップの設計時に
チップパッドのピッチを現在の１６０μｍから３０〜４
０μｍまでに短縮し、２００ピン以上の多ピン構造の半
導体パッケージにおける半導体チップの大きさを減らし
得るという効果がある。また、半導体チップのチップパ
ッドと短縮接続層とが直接接続されるため、製造工程が
簡単になって生産性が向上されるという効果がある。In addition, since the adhesive of the shortened connection layer is directly connected to the chip pad, the pitch of the chip pad is changed from 160 μm to 30 to 4 when the semiconductor chip is designed.
There is an effect that the size can be reduced to 0 μm and the size of a semiconductor chip in a semiconductor package having a multi-pin structure of 200 pins or more can be reduced. Further, since the chip pad of the semiconductor chip and the shortened connection layer are directly connected, there is an effect that the manufacturing process is simplified and the productivity is improved.

【００１８】更に、短縮接続層の製造工程中ソルダボー
ルを予め製造し得るようになるため、製造原価が節減さ
れるという効果がある。そして、短縮接続層上面に出力
端子を直接形成されるためパッケージの大きさが縮小さ
れ、薄型のＢＧＡ半導体パッケージの薄型化を図り得る
という効果がある。Furthermore, since the solder balls can be manufactured in advance during the manufacturing process of the shortened connection layer, the manufacturing cost can be reduced. Further, since the output terminals are formed directly on the upper surface of the shortened connection layer, the size of the package is reduced, and the thin BGA semiconductor package can be made thinner.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る短縮接続層を有するＢＧＡ半導体
パッケージの縦断面図である。FIG. 1 is a longitudinal sectional view of a BGA semiconductor package having a shortened connection layer according to the present invention.

【図２】図１の短縮接続層を有するＢＧＡ半導体パッケ
ージのＡ部分拡大図である。FIG. 2 is an enlarged view of a portion A of the BGA semiconductor package having the shortened connection layer of FIG. 1;

【図３】本発明に係る短縮接続層の縦断面図である。FIG. 3 is a longitudinal sectional view of a shortened connection layer according to the present invention.

【図４】従来のＢＧＡ半導体パッケージの縦断面図であ
る。FIG. 4 is a longitudinal sectional view of a conventional BGA semiconductor package.

【符号の説明】[Explanation of symbols]

１１：パッケージ本体 １１ａ：溝 １５：半導体チップ １６：モールディング樹脂 ２０：短縮接続層 ２１：回路器 ２２：導電パッド ２３：銅膜金属配線 ２４：接着フィルム ２５：出力端子（ソルダボール） ２６：接続パッド ２７：接着剤 ２８：電導ボール 11: Package body 11a: Groove 15: Semiconductor chip 16: Molding resin 20: Shortened connection layer 21: Circuit device 22: Conductive pad 23: Copper film metal wiring 24: Adhesive film 25: Output terminal (solder ball) 26: Connection pad 27: adhesive 28: conductive ball

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−94438（ＪＰ，Ａ) 特開 昭59−44849（ＪＰ，Ａ) 特開 平７−321157（ＪＰ，Ａ) 特開 平３−274739（ＪＰ，Ａ) 特開 平６−188548（ＪＰ，Ａ) 特開 平７−202064（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/12 H01L 21/60 311 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-94438 (JP, A) JP-A-59-44849 (JP, A) JP-A-7-321157 (JP, A) 274739 (JP, A) JP-A-6-188548 (JP, A) JP-A-7-202064 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 23/12 H01L 21 / 60 311

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】所定深さを有する溝の形成されたパッケー
ジ本体と、 上面にチップパッドが形成され、前記溝内に接着された
半導体チップと、 別途に製作されて、内部には銅膜配線が形成され、上下
面には前記銅膜配線と電気的接続された接続パッドが夫
々形成され、前記上面の接続パッドには出力端子の形成
された短縮接続手段と、 該短縮接続手段の下面の接続パッドと前記半導体チップ
のチップパッドとを接着させる異方性接着剤と、を備え
て構成され、 前記溝の内部は樹脂で密封された ことを特徴とするＢＧ
Ａ半導体パッケージ。1. A package having a groove having a predetermined depth.
The chip body was formed on the upper surface and the chip pad was adhered in the groove.
Semiconductor chip and separately manufactured, copper film wiring is formed inside,
On the surface, connection pads electrically connected to the copper film wiring are provided.
Output terminals are formed on the connection pads on the upper surface.
Shortening connection means is, the lower surface of the connection pads of the shortened connection means semiconductor chip
An anisotropic adhesive for adhering to the chip pad of
Configured Te, the interior of the groove, characterized in that it is sealed with a resin BG
A semiconductor package. 【請求項２】 所定深さを有する溝の形成されたパッケー
ジ本体を準備する工程と、 前記溝内に、形成されたチップパッドが上向きになるよ
うにして半導体チップを接着する工程と、 内部には銅膜配線が形成され、上下面には前記銅膜配線
と電気的接続された接続パッドが夫々接続され、前記上
面の接続パッドには出力端子の形成された短縮接続手段
を準備する工程と、 前記半導体チップの上面のチップパッドと前記短縮接続
手段の下面の接続パッドとが整列されるように、異方性
接着剤を利用して前記半導体チップと前記短縮接続手段
とを熱圧着させて接着させる工程と、 前記溝内に樹脂を密封する工程と、 を順次行うことを特徴とするＢＧＡ半導体パッケージの
製造方法。 2. A step of preparing a package body in which a groove having a predetermined depth is formed; a step of bonding a semiconductor chip in the groove such that a formed chip pad faces upward; A copper film wiring is formed, connection pads electrically connected to the copper film wiring are respectively connected to upper and lower surfaces, and a shortening connection means having an output terminal formed on the connection pad on the upper surface; Thermo-compressing the semiconductor chip and the shortened connection means using an anisotropic adhesive so that the chip pads on the upper surface of the semiconductor chip and the connection pads on the lower surface of the shortened connection means are aligned. A method of manufacturing a BGA semiconductor package, comprising sequentially performing a step of bonding and a step of sealing a resin in the groove.
JP34808096A 1995-12-29 1996-12-26 BGA semiconductor package and manufacturing method thereof Expired - Lifetime JP2893522B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR67334/1995 1995-12-29
KR1019950067334A KR0179802B1 (en) 1995-12-29 1995-12-29 Semiconductor package

Publications (2)

Publication Number Publication Date
JPH09186267A JPH09186267A (en) 1997-07-15
JP2893522B2 true JP2893522B2 (en) 1999-05-24

Family

ID=19447661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34808096A Expired - Lifetime JP2893522B2 (en) 1995-12-29 1996-12-26 BGA semiconductor package and manufacturing method thereof

Country Status (5)

Country Link
US (1) US5990563A (en)
JP (1) JP2893522B2 (en)
KR (1) KR0179802B1 (en)
CN (1) CN1076873C (en)
TW (1) TW425642B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791194B1 (en) * 1996-05-30 2004-09-14 Hitachi, Ltd. Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
JP3695893B2 (en) * 1996-12-03 2005-09-14 沖電気工業株式会社 Semiconductor device, manufacturing method and mounting method thereof
JP3639088B2 (en) * 1997-06-06 2005-04-13 株式会社ルネサステクノロジ Semiconductor device and wiring tape
KR100246366B1 (en) * 1997-12-04 2000-03-15 김영환 Area array type semiconductor package and fabrication method of the same
US6150730A (en) * 1999-07-08 2000-11-21 Advanced Semiconductor Engineering, Inc. Chip-scale semiconductor package
US6239489B1 (en) * 1999-07-30 2001-05-29 Micron Technology, Inc. Reinforcement of lead bonding in microelectronics packages
US6291884B1 (en) * 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages
US6386890B1 (en) 2001-03-12 2002-05-14 International Business Machines Corporation Printed circuit board to module mounting and interconnecting structure and method
US6695623B2 (en) 2001-05-31 2004-02-24 International Business Machines Corporation Enhanced electrical/mechanical connection for electronic devices
WO2007074652A1 (en) * 2005-12-26 2007-07-05 Hitachi Chemical Company, Ltd. Adhesive composition, circuit connecting material and connecting structure of circuit member

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811081A (en) * 1987-03-23 1989-03-07 Motorola, Inc. Semiconductor die bonding with conductive adhesive
US5656862A (en) * 1990-03-14 1997-08-12 International Business Machines Corporation Solder interconnection structure
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5258330A (en) * 1990-09-24 1993-11-02 Tessera, Inc. Semiconductor chip assemblies with fan-in leads
WO1993003989A1 (en) * 1991-08-13 1993-03-04 Rite-Hite Corporation A releasable locking device
US5319242A (en) * 1992-03-18 1994-06-07 Motorola, Inc. Semiconductor package having an exposed die surface
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5381599A (en) * 1993-04-12 1995-01-17 Delco Electronics Corp. Liquid crystal polymer encapsulated electronic devices and methods of making the same
JP3258764B2 (en) * 1993-06-01 2002-02-18 三菱電機株式会社 Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5583370A (en) * 1994-03-04 1996-12-10 Motorola Inc. Tab semiconductor device having die edge protection and method for making the same
JPH07302858A (en) * 1994-04-28 1995-11-14 Toshiba Corp Semiconductor package
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
JP2546192B2 (en) * 1994-09-30 1996-10-23 日本電気株式会社 Film carrier semiconductor device
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die

Also Published As

Publication number Publication date
US5990563A (en) 1999-11-23
CN1153999A (en) 1997-07-09
CN1076873C (en) 2001-12-26
JPH09186267A (en) 1997-07-15
KR0179802B1 (en) 1999-03-20
TW425642B (en) 2001-03-11
KR970053678A (en) 1997-07-31

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