JP2879773B2 - IMAGE DEVICE AND ITS MANUFACTURING METHOD - Google Patents

IMAGE DEVICE AND ITS MANUFACTURING METHOD

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Publication number
JP2879773B2
JP2879773B2 JP5154187A JP15418793A JP2879773B2 JP 2879773 B2 JP2879773 B2 JP 2879773B2 JP 5154187 A JP5154187 A JP 5154187A JP 15418793 A JP15418793 A JP 15418793A JP 2879773 B2 JP2879773 B2 JP 2879773B2
Authority
JP
Japan
Prior art keywords
substrate
wiring
image
array
monocular lens
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5154187A
Other languages
Japanese (ja)
Other versions
JPH06340118A (en
Inventor
俊次 村野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP5154187A priority Critical patent/JP2879773B2/en
Publication of JPH06340118A publication Critical patent/JPH06340118A/en
Application granted granted Critical
Publication of JP2879773B2 publication Critical patent/JP2879773B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の利用分野】この発明は、ＬＥＤヘッドや密着型
イメージセンサ、液晶シャッタアレイヘッド等の、画像
アレイを用いた画像装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image device using an image array, such as an LED head, a contact type image sensor, and a liquid crystal shutter array head.

【０００２】[0002]

【従来技術】ＬＥＤヘッドや液晶シャッタアレイヘッ
ド、密着型イメージセンサ等の画像装置では、ＬＥＤア
レイや液晶シャッタアレイ等の画像アレイを基板に搭載
し、基板配線に接続する。基板配線には通常Ａｌの蒸着
膜等が用いられ、基板には表面の平滑性に優れたガラス
基板が用いられる。2. Description of the Related Art In an image device such as an LED head, a liquid crystal shutter array head, and a contact image sensor, an image array such as an LED array or a liquid crystal shutter array is mounted on a substrate and connected to substrate wiring. For the substrate wiring, a deposited film of Al or the like is usually used, and for the substrate, a glass substrate having excellent surface smoothness is used.

【０００３】しかし蒸着膜では基板への付着強度が低
く、かつ成膜に時間を要し量産性に乏しい。例えば蒸着
では成膜毎に真空引きをして真空度を得、次いで基板配
線を蒸着して取り出すことになる。これでは１回の成膜
に時間を要し、蒸着装置も大がかりなものが必要とな
る。However, a vapor-deposited film has low adhesion strength to a substrate, requires a long time for film formation, and is poor in mass productivity. For example, in vapor deposition, the degree of vacuum is obtained by evacuation for each film formation, and then the substrate wiring is vapor-deposited and taken out. This requires a long time for one film formation, and requires a large-scale vapor deposition apparatus.

【０００４】画像装置では単眼レンズを用いることが検
討されているが、この場合単眼レンズと基板との位置合
わせが決定的に重要となる。位置合わせの精度が低い
と、あるいは熱膨張等により位置合わせが狂うと、印画
像や読み取り画像に白筋や黒筋が発生する。そこで安価
にかつ確実に基板と単眼レンズとの位置合わせを行い、
しかも熱膨張などにより位置合わせが狂わないようにす
る必要がある。The use of a monocular lens in an image apparatus has been studied, but in this case, the alignment between the monocular lens and the substrate is crucial. If the accuracy of the alignment is low, or if the alignment is incorrect due to thermal expansion or the like, white streaks or black streaks are generated in the stamp image or the read image. Therefore, the alignment between the substrate and the monocular lens is performed inexpensively and reliably.
In addition, it is necessary to prevent misalignment due to thermal expansion or the like.

【０００５】さらに画像装置では画像アレイを基板配線
にフリップチップ接続することも公知であるが、Ａｌ配
線では半田付けができず、アレイに設けた電極バンプと
Ａｌ配線とを熱圧着することになる。熱圧着には大きな
加圧力を必要とし、脆弱な画像アレイを損傷することが
ある。Further, in an image apparatus, it is also known that an image array is flip-chip connected to substrate wiring. However, soldering cannot be performed with Al wiring, and the electrode bumps provided on the array and the Al wiring are thermocompression bonded. . Thermocompression requires high pressure and can damage fragile image arrays.

【０００６】[0006]

【発明の課題】この発明の基本的課題は、 １）基板と単眼レンズアレイとを安価に設け、 ２）基板と単眼レンズとを正確に位置決めし、かつ熱膨
張などによる位置決めの狂いをなくし、 ３）画像アレイと基板配線とのフリップチップ接続を容
易にし、 ４）基板に対する基板配線の被着強度と、画像アレイの
フリップチップ接続強度とを改善し、 ５）不要光を遮断して、画像品位を向上させる、ことに
ある（請求項１）。請求項２での課題はさらに、基板配
線の密度を低下させることにある。The basic objects of the present invention are: 1) to provide a substrate and a monocular lens array at a low cost; 2) to accurately position the substrate and the monocular lens, and to eliminate misalignment due to thermal expansion and the like. 3) Flip chip connection between the image array and the substrate wiring is facilitated. 4) Improving the adhesion strength of the substrate wiring to the substrate and the flip chip connection strength of the image array. This is to improve the quality (claim 1). Another object of the present invention is to reduce the density of substrate wiring.

【０００７】[0007]

【発明の構成と作用】この発明の画像装置は、透明プラ
スチック基板の第１の主面に、多数の受発光素子を設け
た画像アレイを列状に配置するとともに、他方の主面に
は基板と一体的に単眼レンズをアレイ状に設け、前記第
１の主面では受発光素子に対向した部分を平滑面とし、
これ以外の領域を粗面化した粗面化領域上に設けた基板
配線に対して前記画像アレイの電極バンプをフリップチ
ップ接続したことを特徴とする。According to the image apparatus of the present invention, an image array provided with a large number of light receiving / emitting elements is arranged in rows on a first main surface of a transparent plastic substrate, and a substrate is provided on the other main surface. A monocular lens is provided in an array integrally with the first main surface, and a portion facing the light receiving and emitting element is made a smooth surface on the first main surface;
An electrode bump of the image array is flip-chip connected to a substrate wiring provided on a roughened area in which the other area is roughened.

【０００８】基板を透明プラスチック基板とし単眼レン
ズを一体成型すれば、安価に単眼レンズと基板とを構成
できる。しかも単眼レンズは最初から基板と一体なの
で、両者の位置合わせの必要がなく、また熱膨張などに
より位置合わせが狂うこともない。この結果、白筋や黒
筋の発生などの問題を最初から解消することができる。
基板配線との密着性を高めるためにサンドブラストやエ
ッチング等により基板を粗面化する。粗面化する領域
は、画像アレイの受発光素子を除いた部分で、この領域
を全面的にあるいは部分的に粗面化する。この結果、基
板配線をプラスチック基板の粗面化領域に強固に被着さ
せることができる。基板の裏面に単眼レンズがあるので
画像アレイはフリップチップ接続に限られ、また基板配
線に銅メッキ膜や半田メッキ膜などを用いれば容易にフ
リップチップ接続できる。ここで受発光素子に対向した
部分は平滑面としてあるので、受発光素子への光路が確
保され、これ以外の面は粗面なので不要光は粗面で散乱
されて、画像品位が向上する。さらに粗面を用いること
により、基板配線の基板への付着力やフリップチップ接
続の強度が向上する。If the substrate is a transparent plastic substrate and the monocular lens is integrally formed, the monocular lens and the substrate can be formed at low cost. In addition, since the monocular lens is integrated with the substrate from the beginning, there is no need to align the two, and there is no misalignment due to thermal expansion or the like. As a result, problems such as generation of white streaks and black streaks can be solved from the beginning.
The substrate is roughened by sandblasting, etching, or the like in order to increase the adhesion to the substrate wiring. The region to be roughened is a portion of the image array other than the light emitting and receiving elements, and this region is entirely or partially roughened. As a result, the substrate wiring can be firmly adhered to the roughened area of the plastic substrate. Since there is a monocular lens on the back surface of the substrate, the image array is limited to flip-chip connection, and flip-chip connection can be easily made by using a copper plating film or a solder plating film for the substrate wiring. Here, since the portion facing the light emitting and receiving element is a smooth surface, an optical path to the light emitting and receiving element is secured, and since the other surface is rough, unnecessary light is scattered by the rough surface and the image quality is improved. Further, by using the rough surface, the adhesive force of the substrate wiring to the substrate and the strength of flip-chip connection are improved.

【０００９】好ましくは基板配線を金属下地のメッキ膜
上に導電体のメッキ膜を積層したものとし、金属下地膜
により基板との付着力を確保し、導電体膜により導電性
を確保する。金属下地膜には例えばＮｉ，Ｃｒ，Ｔｉ等
の無電解メッキ膜を用い、導電体のメッキ膜には例えば
銅膜や半田膜を用いる。さてフリップチップ接続部で基
板配線に半田メッキがあれば、画像アレイの電極バンプ
とのフリップチップ接続を半田付けで実現できる。この
結果、熱圧着時の圧力による画像アレイの損傷という問
題は解消し、かつ加圧しながら電気炉中で熱圧着するの
に比べて短時間で容易にフリップチップ接続できる。半
田メッキ膜は銅メッキ膜からなる導電体膜上にフリップ
チップ接続部のみをメッキして部分的に設けても良い
が、導電体膜全体を半田メッキ膜とすると工程数が減少
する。Preferably, the wiring of the substrate is formed by laminating a plating film of a conductor on a plating film of a metal underlayer, and the metal underlayer secures adhesion to the substrate and the conductive film secures the conductivity. For example, an electroless plating film of Ni, Cr, Ti or the like is used as the metal base film, and a copper film or a solder film is used as the conductor plating film. Now, if there is solder plating on the substrate wiring at the flip chip connection part, flip chip connection with the electrode bumps of the image array can be realized by soldering. As a result, the problem of damage to the image array due to the pressure during thermocompression is eliminated, and flip-chip connection can be easily performed in a shorter time as compared with thermocompression in an electric furnace while applying pressure. The solder plating film may be partially provided by plating only the flip chip connection portion on the conductor film made of a copper plating film. However, if the entire conductor film is made of a solder plating film, the number of steps is reduced.

【００１０】好ましくは、基板配線を、画像アレイの列
の一方の側に設けた第１の基板配線と前記列の他方の側
に設けた第２の基板配線とで構成し、各基板配線を画像
アレイ２個毎にほぼＵ字状に折り返して分断された配線
として、該分断された配線内で、２個の画像アレイの対
応する受発光素子同士を電気的に接続し、基板の裏面に
は、単眼レンズを設けた領域の両外側に、第１の裏面配
線と第２の裏面配線とを設けて、第１の基板配線と第１
の裏面配線とをスルーホールで接続することにより、分
断された第１の基板配線を所定の順序で相互に電気的に
接続し、かつ第２の基板配線と第２の裏面配線とをスル
ーホールで接続することにより、分断された第２の基板
配線を所定の順序で相互に電気的に接続する。このよう
にすれば基板配線の密度は１／２に低下し、メッキで多
数の個別配線からなる基板配線を設けるのが容易にな
る。メッキによる成膜では高密度配線には限界がある
が、基板配線を２つに分けると問題も解消する。Preferably, the substrate wiring comprises a first substrate wiring provided on one side of a column of the image array and a second substrate wiring provided on the other side of the column. As a wiring that is folded and folded in a substantially U shape for every two image arrays, the corresponding light receiving and emitting elements of the two image arrays are electrically connected to each other within the divided wiring, Is provided with a first back surface wiring and a second back surface wiring on both outer sides of a region where a monocular lens is provided, and a first substrate wiring and a first back surface wiring are provided.
Are connected to each other in a predetermined order, and the second substrate wiring and the second rear surface wiring are connected to each other by through holes. , The divided second substrate wirings are electrically connected to each other in a predetermined order. In this case, the density of the substrate wiring is reduced to half, and it becomes easy to provide the substrate wiring composed of a large number of individual wirings by plating. Although there is a limit in high-density wiring in film formation by plating, the problem can be solved by dividing the substrate wiring into two.

【００１１】例えば個別配線の総数が６４本の場合、例
えば３２本ずつの２つの基板配線を画像アレイの列の両
側に設ける。基板配線はほぼＵ字状の形状とし、その両
端を画像アレイの電極バンプにフリップチップ接続する
ので、両端が他の部分に接続されず孤立してしまう。そ
こでプラスチック基板にスルーホールを設け、スルーホ
ール，基板の裏面配線，次のＵ字状の基板配線の順に接
続せ、分断した基板配線を相互に接続する。基板の加工
上で最も大きな面積を占め、実装の限界となるのはスル
ーホールである。そして請求項４の発明では、画像アレ
イの両側に基板配線を施し、アレイ２個単位で裏面配線
を行うので、画像アレイの列の片側のみに基板配線を設
けて裏面配線とマトリックス接続する場合と比べ、スル
ーホール密度を１／４にできる。このためスルーホール
加工が極めて容易になる。For example, when the total number of individual wirings is 64, two substrate wirings, for example, 32 wirings are provided on both sides of the columns of the image array. Since the substrate wiring has a substantially U-shape and both ends are flip-chip connected to the electrode bumps of the image array, both ends are isolated without being connected to other parts. Therefore, a through hole is provided in the plastic substrate, the through hole, the backside wiring of the substrate, the next U-shaped substrate wiring are connected in this order, and the divided substrate wirings are connected to each other. The through-hole occupies the largest area in processing the substrate and is the limit of mounting. According to the fourth aspect of the present invention, the substrate wiring is provided on both sides of the image array, and the back wiring is performed in units of two arrays. Therefore, the substrate wiring is provided only on one side of the column of the image array and the back wiring is connected to the matrix. In comparison, the through hole density can be reduced to 1/4. For this reason, through hole processing becomes extremely easy.

【００１２】このような画像装置は例えば、プラスチッ
クで基板と単眼レンズとを一体成型する工程と、基板の
単眼レンズを設けた側の反対側の主面を部分的に粗面化
する工程と、粗面化した基板の主面上に金属下地膜をメ
ッキする工程と、金属下地膜土に導電体膜をメッキする
工程と、導電体膜上に画像アレイをフリップチップ接続
する工程とで製造する。ここで好ましくはフリップチッ
プ接続部で導電体膜を半田メッキ膜とし、レンズ側から
レーザー光や赤外線等で電極バンプの付近を局所的に加
熱し半田付けする。このようにすれば例えばレーザーで
走査するだけで、あるいは赤外線で加熱するだけで、フ
リップチップ接続ができる。Such an image apparatus includes, for example, a step of integrally molding a substrate and a monocular lens with plastic, a step of partially roughening a main surface of the substrate opposite to the side on which the monocular lens is provided, It is manufactured by a step of plating a metal base film on a main surface of a roughened substrate, a step of plating a conductor film on a metal base film soil, and a step of flip-chip connecting an image array on the conductor film. . Here, preferably, the conductor film is formed as a solder plating film at the flip chip connection portion, and the vicinity of the electrode bump is locally heated and soldered from the lens side with laser light or infrared light. In this way, flip-chip connection can be achieved, for example, only by scanning with a laser or by heating with infrared rays.

【００１３】[0013]

【実施例】図１〜図５に実施例を示す。図１において、
２はプラスチック基板で、エポキシやアクリルあるいは
ポリカーボネイト等の透明プラスチック基板を用いる。
４は単眼レンズでアレイ状に形成し、例えばＬＥＤアレ
イ６の１個毎に設ける。単眼レンズ４はプラスチック基
板２と一体成型する。６はＬＥＤアレイで、基板２の第
１の主面に沿って例えば直線状に４０個程度配置し、Ｌ
ＥＤアレイ６の他にＭＯＳＣＣＤアレイ等を用いても良
い。基板２の第１の主面には基板配線８を施し、ＬＥＤ
アレイ６の電極に接続した電極バンプ１０とフリップチ
ップ接続する。１２はクリップ端子で、ＬＥＤアレイ６
の共通電極に接続し、例えば基板２の反対側の主面へ接
続する。ＬＥＤアレイ６の共通電極の接続方法は、クリ
ップ端子１２を用いるものの他、任意のものを用いるこ
とができる。1 to 5 show an embodiment. In FIG.
Reference numeral 2 denotes a plastic substrate, which uses a transparent plastic substrate such as epoxy, acrylic, or polycarbonate.
Reference numeral 4 denotes a monocular lens which is formed in an array, and is provided, for example, for each LED array 6. The monocular lens 4 is formed integrally with the plastic substrate 2. Reference numeral 6 denotes an LED array in which, for example, about 40 LED arrays are arranged in a straight line along the first main surface of the substrate 2.
In addition to the ED array 6, a MOSCCD array or the like may be used. A substrate wiring 8 is provided on the first main surface of the substrate 2 and an LED is provided.
The electrode bumps 10 connected to the electrodes of the array 6 are flip-chip connected. Reference numeral 12 denotes a clip terminal.
And to, for example, the main surface on the opposite side of the substrate 2. As a method of connecting the common electrode of the LED array 6, any method other than the method using the clip terminal 12 can be used.

【００１４】図２に、単眼レンズ４の側から見た基板２
の配置を示す。ＬＥＤアレイ６の発光体の数を６４個と
すると、基板配線８は６４本の個別配線８−１〜８−６
４からなり、個別配線８−１〜８−３２は図での上側
に、個別配線８−３３〜８−６４は図での下側に配置す
る。各個別配線８−１〜８−６４はほぼＵ字状をなし、
ＬＥＤアレイ６の２個毎に分断して設ける。基板配線８
は個別配線８−１〜８−３２からなる第１の基板配線
と、個別配線８−３３〜８−６４からなる第２の基板配
線とに分割して配置し、ＬＥＤアレイ６の列の両方に設
ける。個別配線８−１〜８−６４は２つの電極バンプ１
０，１０の間をＵ字状に折り返して第１の主面では他に
はつながらないので、スルーホール１４を設けて基板２
の裏面を介して相互に接続する。１６はスルーホール１
４の列で、スルーホール１４の配列ピッチには０．８ｍ
ｍ程度が必要なので、スルーホールの列１６は２列にし
かも基板２の長手方向に対して斜めに配置する。プラス
チック基板２の裏面（単眼レンズ４側の主面）には裏面
配線２０を設け、スルーホール１４を介して基板配線８
と接続する。このようにＬＥＤアレイ６の２個毎に分断
した基板配線８を、スルーホールの列１６と裏面配線２
０並びに次のスルーホールの列１６を通じて相互に接続
する。FIG. 2 shows the substrate 2 viewed from the monocular lens 4 side.
The following shows the arrangement. Assuming that the number of light emitters of the LED array 6 is 64, the substrate wiring 8 has 64 individual wirings 8-1 to 8-6.
The individual wirings 8-1 to 8-32 are arranged on the upper side in the figure, and the individual wirings 8-33 to 8-64 are arranged on the lower side in the figure. Each of the individual wirings 8-1 to 8-64 is substantially U-shaped,
The LED array 6 is divided and provided for every two. Board wiring 8
Is divided into a first substrate wiring composed of individual wirings 8-1 to 8-32 and a second substrate wiring composed of individual wirings 8-33 to 8-64. To be provided. The individual wirings 8-1 to 8-64 are two electrode bumps 1
Since the portion between 0 and 10 is folded in a U-shape and is not connected to the other on the first main surface, a through hole 14 is provided to
Are connected to each other via the back surface. 16 is through hole 1
In the row of 4, the arrangement pitch of the through holes 14 is 0.8 m.
Since about m is required, the rows of through holes 16 are arranged in two rows and obliquely to the longitudinal direction of the substrate 2. A back surface wiring 20 is provided on the back surface (main surface on the side of the monocular lens 4) of the plastic substrate 2, and the substrate wiring 8 is provided through a through hole 14.
Connect with In this manner, the substrate wiring 8 divided for every two LED arrays 6 is divided into a row of through holes 16 and a rear wiring 2.
Interconnected through a row of 0 and next through holes 16.

【００１５】図３にフリップチップ接続部を示し、図４
に接続直前の状態を側面から見て示す。ＬＥＤアレイ６
はＧａＡｓ等の半導体基板からなり、図の２２は個別の
発光体でＬＥＤアレイ６に例えば６４個設ける。２４は
ＬＥＤアレイ６の電極で例えばＡｌ膜をエッチングして
設け、フリップチップ接続部ではＡｌ電極２４の上に電
極バンプ１０を積層する。図４に移ると、電極バンプ１
０はＮｉやＣｒあるいはＴｉ等の金属下地膜上にＡｕや
Ａｕ−Ｐｄ，Ｐｄ等の膜を積層したもので、ここでは金
属下地膜としてＮｉメッキ層２６を用い、その土部にＡ
ｕメッキ層２８を積層した。FIG. 3 shows a flip chip connection portion, and FIG.
Shows the state immediately before connection as viewed from the side. LED array 6
Is composed of a semiconductor substrate such as GaAs. Reference numeral 22 in FIG. Reference numeral 24 denotes an electrode of the LED array 6 provided by etching, for example, an Al film, and the electrode bump 10 is laminated on the Al electrode 24 in the flip chip connection portion. Turning to FIG. 4, the electrode bump 1
Numeral 0 is a film in which a film of Au, Au-Pd, Pd or the like is laminated on a metal base film of Ni, Cr or Ti, etc. Here, a Ni plating layer 26 is used as the metal base film, and A
The u plating layer 28 was laminated.

【００１６】プラスチック基板２側ではＮｉやＣｒ，Ｔ
ｉ等の金属下地膜３０上に、半田メッキ層３２を積層
し、個別配線８−１〜８−６４とした。金属下地膜３０
は例えばＮｉの無電解メッキにより形成し、不要部をエ
ッチングやリフトオフ等により除去する。金属下地膜３
０の膜厚は例えば２〜３μｍ程度が好ましい。半田メッ
キ層３２は基板２を半田浴に浸すことで形成し、膜厚は
例えば１〜１００μｍ、好ましくは５〜２０μｍ程度と
する。膜厚がこれよりも大きいと基板２への付着力が低
下し、薄すぎると電極バンプ１０との半田付けが難しく
なる。３４は粗面化部で、発光体２２に向き合った部分
と単眼レンズ４の表面部とを除いて、基板２の表裏をサ
ンドブラストやエッチング等により粗面化して形成す
る。粗面化の程度は表面粗さ計で測定した平均表面粗さ
として例えば０．１〜５μｍ程度、好ましくは０．３〜
３μｍ程度とし、粗さをこれ以上大きくするとＬＥＤア
レイ６の搭載精度に影響し、これ以下では金属下地膜３
０の付着強度が低下する。図４には特に示さなかった
が、裏面配線２０も基板２の表面を粗面化した上に金属
下地膜３０と半田メッキ層３２とを積層して形成する。
半田メッキ層３２を用いる理由は、電極バンプ１０との
半田付けを容易にすることである。そこで半田メッキ層
３２に替えて例えば銅メッキ層を用い、電極バンプ１０
とフリップチップ接続する部分に、クリーム半田等を塗
布しても良い。しかし実施例のようにすればクリーム半
田の塗布が不要になるし、また塗布したクリーム半田に
よって個別配線８−１〜８−６４がショートする危険性
もなくなる。On the plastic substrate 2 side, Ni, Cr, T
A solder plating layer 32 was laminated on the metal base film 30 of i or the like to form individual wirings 8-1 to 8-64. Metal underlayer 30
Is formed by, for example, electroless plating of Ni, and unnecessary portions are removed by etching or lift-off. Metal underlayer 3
The thickness of 0 is preferably, for example, about 2 to 3 μm. The solder plating layer 32 is formed by immersing the substrate 2 in a solder bath, and has a thickness of, for example, 1 to 100 μm, and preferably about 5 to 20 μm. If the film thickness is larger than this, the adhesive force to the substrate 2 decreases, and if it is too thin, soldering to the electrode bumps 10 becomes difficult. Numeral 34 denotes a roughened portion, which is formed by roughening the front and back surfaces of the substrate 2 by sandblasting, etching or the like, except for a portion facing the light emitting body 22 and a surface portion of the monocular lens 4. The degree of roughening is, for example, about 0.1 to 5 μm, preferably 0.3 to 5 μm as an average surface roughness measured by a surface roughness meter.
If the roughness is made larger than about 3 μm, the mounting accuracy of the LED array 6 is affected.
The adhesive strength of 0 decreases. Although not particularly shown in FIG. 4, the back wiring 20 is also formed by laminating a metal base film 30 and a solder plating layer 32 after roughening the surface of the substrate 2.
The reason for using the solder plating layer 32 is to facilitate soldering with the electrode bumps 10. Therefore, for example, a copper plating layer is used instead of the solder plating layer 32, and the electrode bump 10
Cream solder or the like may be applied to a portion to be connected with the flip chip. However, according to the embodiment, the application of the cream solder becomes unnecessary, and the danger that the individual wirings 8-1 to 8-64 are short-circuited by the applied cream solder is eliminated.

【００１７】図５に、ＬＥＤアレイ６のフリップチップ
接続までの工程を示す。ポリカーボネイトやエポキシあ
るいはアクリル等のプラスチックを用いて、基板２と単
眼レンズ４を一体成型する。次に発光体２２に向き合う
ことになる部分と単眼レンズ４の表面とをマスクして、
サンドブラストやエッチング等により基板を粗面化す
る。これによって粗面化領域３４を形成する。粗面化領
域３４を形成する前後に基板２に穴開け加工を施し、次
いでＮｉのメッキ液中に基板２を浸して、無電解メッキ
によりＮｉメッキを行う。続いて不要部をエッチング
し、金属下地膜３０を形成する。この後基板２を溶融半
田に浸して半田を金属下地膜３０の上にのみ付着させ、
特にパターンニングを行わずに半田メッキ層３２を得
る。これらの後にスルーホール加工を施し、裏面配線２
０と基板配線８とを接続する。FIG. 5 shows the steps up to the flip chip connection of the LED array 6. The substrate 2 and the monocular lens 4 are integrally molded using a plastic such as polycarbonate, epoxy or acrylic. Next, the portion facing the light emitter 22 and the surface of the monocular lens 4 are masked,
The substrate is roughened by sandblasting or etching. Thus, a roughened region 34 is formed. Before and after the formation of the roughened region 34, the substrate 2 is perforated, then the substrate 2 is immersed in a Ni plating solution, and Ni plating is performed by electroless plating. Subsequently, unnecessary portions are etched to form a metal base film 30. Thereafter, the substrate 2 is immersed in the molten solder so that the solder is deposited only on the metal base film 30,
In particular, the solder plating layer 32 is obtained without performing patterning. After these, through-hole processing is performed,
0 and the substrate wiring 8 are connected.

【００１８】配線８，２０の形成後にＬＥＤアレイ６を
搭載し、クリップ端子１２を用いて仮止めする。クリッ
プ端子１２には仮止めができる程度の弾性があるものが
好ましい。次に図５の半導体レーザー４０，４０等を用
い、単眼レンズ４の側から可視光や赤外線等を照射し
て、半田メッキ層３２を溶かし、電極バンプ１０に半田
付けする。半田はプラスチック基板２の表面には直接付
着せず、金属下地膜３０がある部分にのみ付着するの
で、半田メッキ層３２を溶融させても個別配線８−１〜
８−６４がショートする恐れはない。After the wirings 8 and 20 are formed, the LED array 6 is mounted and temporarily fixed using the clip terminals 12. It is preferable that the clip terminal 12 has such an elasticity that it can be temporarily fixed. Next, using the semiconductor lasers 40, 40 and the like in FIG. 5, visible light and infrared light are irradiated from the side of the monocular lens 4 to melt the solder plating layer 32 and solder it to the electrode bumps 10. Since the solder does not directly adhere to the surface of the plastic substrate 2 but only to the portion where the metal base film 30 is present, even if the solder plating layer 32 is melted, the individual wirings 8-1 to 8-1
There is no danger of 8-64 shorting.

【００１９】このようにすればフリップチップ接続を半
田付けで行うことができ、レーザー４０，４０で基板２
の裏面を走査するだけでフリップチップ接続を行うこと
ができる。また半田付けはＡｌの基板配線への熱圧着と
異なりクリップ端子１２からの小さな圧力で位置決めす
るだけでよく、ＬＥＤアレイ６の脆弱なＧａＡｓ基板を
破壊する恐れがない。さらに光による局所的な加熱なの
でプラスチック基板２や単眼レンズ４を変形させたり、
フリップチップ接続部以外の半田メッキ層３２を溶かし
たりすることもない。このため耐熱性の低いプラスチッ
ク基板２や融点の低い半田メッキ層３２でも問題は生じ
ず、リフロー炉を通す必要がないので半田付けに必要な
時間も短く、半田中のフラックスがリフロー炉でＬＥＤ
アレイ６に付着する等の問題もない。In this way, the flip chip connection can be performed by soldering, and the lasers 40, 40
Flip-chip connection can be performed only by scanning the back surface of the substrate. Unlike the thermocompression bonding of Al to the substrate wiring, the soldering only needs to be performed with a small pressure from the clip terminal 12, and there is no possibility that the fragile GaAs substrate of the LED array 6 is broken. Furthermore, since it is locally heated by light, the plastic substrate 2 and the monocular lens 4 are deformed,
There is no melting of the solder plating layer 32 other than the flip chip connection part. Therefore, there is no problem even with the plastic substrate 2 having low heat resistance or the solder plating layer 32 having low melting point, and it is not necessary to pass through the reflow furnace, so that the time required for soldering is short, and the flux in the solder is reduced by the LED in the reflow furnace.
There is no problem such as attachment to the array 6.

【００２０】フリップチップ接続部のみを局所的に加熱
するためレーザー４０を用いることが好ましいが、リフ
ロー炉による全体的加熱やフラックスによる汚染を避け
るだけであれば通常の光源を用いた赤外線加熱でも良
い。このような例を図６に示す。図の４２は赤外線ラン
プで、４４は断面が放物線形の反射鏡であり、赤外線ラ
ンプ４２からの光を反射鏡４４で平行光線に変え、ＬＥ
Ｄアレイ６の裏面のみを局所的に加熱する。Although it is preferable to use the laser 40 to locally heat only the flip chip connection portion, infrared heating using a normal light source may be used as long as the entire heating by the reflow furnace or the contamination by the flux is only avoided. . FIG. 6 shows such an example. In the figure, reference numeral 42 denotes an infrared lamp, and 44 denotes a parabolic reflector having a cross section. The light from the infrared lamp 42 is converted into parallel rays by the reflector 44, and LE
Only the back surface of the D array 6 is locally heated.

【００２１】実施例の作用を示す。実施例の基本的概念
は基板２と単眼レンズ４とを一体にすることである。こ
れはプラスチック基板２を用い一体成型を行うことで達
成される。この結果、基板２と単眼レンズ４との位置合
わせは成型時に行われ、周囲温度の変動による熱膨張等
で位置合わせが狂うとの問題も解消する。ＬＥＤアレイ
６は基板配線８に位置合わせされており、単眼レンズ４
が基板２と一体なので、ＬＥＤアレイ６は基板配線８を
介して単眼レンズ４に位置合わせされる。The operation of the embodiment will be described. The basic concept of the embodiment is that the substrate 2 and the monocular lens 4 are integrated. This is achieved by performing integral molding using the plastic substrate 2. As a result, the alignment between the substrate 2 and the monocular lens 4 is performed at the time of molding, and the problem of misalignment due to thermal expansion or the like due to a change in ambient temperature is also solved. The LED array 6 is aligned with the substrate wiring 8 and the monocular lens 4
Is integrated with the substrate 2, the LED array 6 is aligned with the monocular lens 4 via the substrate wiring 8.

【００２２】実施例の次の概念は、基板配線８にメッキ
膜を用い、Ａｌの真空蒸着等を不要にすることである。
そしてこれによって画像装置の量産性が大幅に向上す
る。プラスチック基板２はガラス基板よりも金属下地膜
３０との馴染みが良く、基板配線８や裏面配線２０を設
ける部分を粗面化することにより配線８，２０と基板２
との付着力をさらに向上させる。半田メッキ層３２は単
独では基板２に付着しないが、中間に金属下地膜３０を
設けることにより半田メッキ層３２を容易に形成するこ
とができる。The next concept of the embodiment is that a plating film is used for the substrate wiring 8 to eliminate the need for vacuum deposition of Al or the like.
As a result, mass productivity of the image device is greatly improved. The plastic substrate 2 has a better affinity with the metal base film 30 than the glass substrate, and the portions where the substrate wiring 8 and the rear surface wiring 20 are provided are roughened so that the wirings 8 and 20 and the substrate 2 are roughened.
To further improve the adhesion. Although the solder plating layer 32 alone does not adhere to the substrate 2, the solder plating layer 32 can be easily formed by providing the metal base film 30 in the middle.

【００２３】メッキによる基板配線８は真空蒸着による
Ａｌ配線に比べて、高密度化には適していない。そこで
基板配線８をＬＥＤアレイ６の上側に設けた個別配線８
−１〜８−３２からなる第１の基板配線と下側に設けた
個別配線８−３３〜８−６４からなる第２の基板配線と
に分割し、配線の密度を１／２に低下させる。個別配線
８−１〜８−６４をほぼＵ字状の形状とし、両端をＬＥ
Ｄアレイ６の電極バンプ１０にフリップチップ接続し
た。これはフリップチップ接続に適した形状である。こ
のようにすると各個別配線８−１〜８−６４はＬＥＤア
レイ６の２個毎に孤立するので、スルーホール１４と裏
面配線２０とを用いて相互に接続した。そしてプラスチ
ック基板２ではスルーホール１４を設けるのが容易で、
裏面配線２０は基板配線８と同じプロセスにより同時に
形成することができる。The substrate wiring 8 formed by plating is not suitable for increasing the density as compared with the Al wiring formed by vacuum evaporation. Therefore, the individual wiring 8 provided with the substrate wiring 8 above the LED array 6
-1 to 8-32 and a second substrate wiring provided below the individual wirings 8-33 to 8-64, and the wiring density is reduced to half. . The individual wirings 8-1 to 8-64 have a substantially U-shaped shape, and both ends are LE
Flip chip connection was made to the electrode bumps 10 of the D array 6. This is a shape suitable for flip chip connection. In this case, the individual wirings 8-1 to 8-64 are isolated for every two LED arrays 6, so that the individual wirings 8-1 to 8-64 are connected to each other using the through holes 14 and the back wirings 20. And it is easy to provide the through hole 14 in the plastic substrate 2,
The back wiring 20 can be formed simultaneously with the substrate wiring 8 by the same process.

【００２４】実施例ではＬＥＤヘッドを示したが、これ
に限らず例えばイメージセンサ等でも同様に画像装置を
構成することができる。In the embodiment, the LED head is shown. However, the present invention is not limited to this. For example, an image sensor can be used to constitute an image device.

【００２５】[0025]

【発明の効果】請求項１の発明では、 １）基板と単眼レンズアレイとをプラスチックで安価に
設け、 ２）一体成型により、基板と単眼レンズとを正確に位置
決めし、かつ熱膨張などによる位置決めの狂いをなく
し、 ３）画像アレイと基板配線とのフリップチップ接続を容
易にし、 ４）基板に対する基板配線の被着強度と、画像アレイの
フリップチップ接続強度とを改善し、 ５）不要光を遮断して、画像品位を向上させる。請求項
２の発明ではさらに、 ６）基板配線の密度を低下させて基板配線の形成を容易
にし、高解像度の画像装置への対応を容易にする。また
プラスチック基板を用いるためスルーホールを設けるの
が容易で、裏面配線を用いて分断した基板配線を接続す
る。According to the first aspect of the present invention, 1) the substrate and the monocular lens array are made of plastic at low cost, and 2) the substrate and the monocular lens are accurately positioned by integral molding, and are positioned by thermal expansion or the like. 3) Flip-chip connection between the image array and the board wiring is facilitated. 4) Improving the adhesion strength of the board wiring to the board and the flip-chip connection strength of the image array. 5) Reducing unnecessary light. Cut off to improve image quality. Further, 6) the density of the substrate wiring is reduced, the formation of the substrate wiring is facilitated, and the application to a high-resolution image device is facilitated. Further, since a plastic substrate is used, it is easy to provide a through-hole, and the substrate wiring divided using the back wiring is connected.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 実施例の画像装置の要部断面図FIG. 1 is a sectional view of a main part of an image apparatus according to an embodiment.

【図２】 実施例の画像装置の要部背面図FIG. 2 is a rear view of a main part of the image apparatus according to the embodiment.

【図３】 実施例で画像装置のフリップチップ接続部
を示す図FIG. 3 is a diagram showing a flip-chip connecting portion of the image device in the embodiment.

【図４】 実施例で画像装置のフリップチップ接続部
を示す要部断面図FIG. 4 is an essential part cross-sectional view showing a flip chip connection part of the image device in the embodiment.

【図５】 実施例の画像装置でのレーザー光によるフ
リップチップ接続を示す要部断面図FIG. 5 is a cross-sectional view of a main part showing flip-chip connection by laser light in the image device of the embodiment.

【図６】 変形例での赤外線光源を示す図FIG. 6 is a diagram showing an infrared light source according to a modification.

【符号の説明】[Explanation of symbols]

２ プラスチック基板 ４ 単眼レンズ ６ ＬＥＤアレイ ８ 基板配線 ８−１〜８−６４ 個別配線 １０ 電極バンプ １２ クリップ端子 １４ スルーホール １６ スルーホールの列 ２０ 裏面配線 ２２ 発光体 ２４ 電極 ２６ Ｎｉメッキ層 ２８ Ａｕメッキ層 ３０ 金属下地膜 ３２ 半田メッキ層 ３４ 粗面化領域 ４０ 半導体レーザー ４２ 赤外線ランプ ４４ 反射鏡 Reference Signs List 2 plastic substrate 4 monocular lens 6 LED array 8 substrate wiring 8-1 to 8-64 individual wiring 10 electrode bump 12 clip terminal 14 through hole 16 through hole row 20 back wiring 22 light emitter 24 electrode 26 Ni plating layer 28 Au plating Layer 30 Metal base film 32 Solder plating layer 34 Roughened area 40 Semiconductor laser 42 Infrared lamp 44 Reflector

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 33/00 Ｈ０４Ｎ 5/335 (58)調査した分野(Int.Cl.6，ＤＢ名) B41J 2/44 B41J 2/45 B41J 2/455 G02B 27/00 H01L 33/00 H04N 5/335 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 identification code FI H01L 33/00 H04N 5/335 (58) Fields investigated (Int.Cl. 6 , DB name) B41J 2/44 B41J 2/45 B41J 2/455 G02B 27/00 H01L 33/00 H04N 5/335

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 透明プラスチック基板の第１の主面に、
多数の受発光素子を設けた画像アレイを列状に配置する
とともに、他方の主面には基板と一体的に単眼レンズを
アレイ状に設け、 前記第１の主面では受発光素子に対向した部分を平滑面
とし、これ以外の領域を粗面化した粗面化領域上に設け
た基板配線に対して前記画像アレイに設けた電極バンプ
をフリップチップ接続したことを特徴とする、画像装
置。A first main surface of the transparent plastic substrate,
An image array provided with a large number of light emitting and receiving elements is arranged in a row, and a monocular lens is provided in an array with the substrate on the other main surface, and the first main surface is opposed to the light receiving and emitting element. An image device, characterized in that an electrode bump provided on the image array is flip-chip connected to a substrate wiring provided on a roughened region in which a portion is a smooth surface and the other region is roughened. 【請求項２】 前記基板配線を、画像アレイの列の一方
の側に設けた第１の基板配線と前記列の他方の側に設け
た第２の基板配線とで構成し、 各基板配線を画像アレイ２個毎にほぼＵ字状に折り返し
て分断された配線として、該分断された配線内で、２個
の画像アレイの対応する受発光素子同士を電気的に接続
し、 基板の裏面には、単眼レンズを設けた領域の両外側に、
第１の裏面配線と第２の裏面配線とを設けて、 第１の基板配線と第１の裏面配線とをスルーホールで接
続することにより、分断された第１の基板配線を所定の
順序で相互に電気的に接続し、かつ第２の基板配線と第
２の裏面配線とをスルーホールで接続することにより、
分断された第２の基板配線を所定の順序で相互に電気的
に接続したことを特徴とする、請求項１の画像装置。2. The substrate wiring comprises a first substrate wiring provided on one side of a column of the image array and a second substrate wiring provided on the other side of the column. As a divided wiring that is folded back in a substantially U-shape every two image arrays, the corresponding light receiving and emitting elements of the two image arrays are electrically connected to each other within the divided wiring. Is on both sides of the area where the monocular lens is provided,
By providing a first backside wiring and a second backside wiring and connecting the first substrate wiring and the first backside wiring with through holes, the divided first substrate wirings can be arranged in a predetermined order. By electrically connecting each other and connecting the second substrate wiring and the second back wiring with through holes,
The image apparatus according to claim 1, wherein the divided second substrate wirings are electrically connected to each other in a predetermined order.
JP5154187A 1993-05-31 1993-05-31 IMAGE DEVICE AND ITS MANUFACTURING METHOD Expired - Fee Related JP2879773B2 (en)

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JP5154187A JP2879773B2 (en) 1993-05-31 1993-05-31 IMAGE DEVICE AND ITS MANUFACTURING METHOD

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Application Number Priority Date Filing Date Title
JP5154187A JP2879773B2 (en) 1993-05-31 1993-05-31 IMAGE DEVICE AND ITS MANUFACTURING METHOD

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JPH06340118A JPH06340118A (en) 1994-12-13
JP2879773B2 true JP2879773B2 (en) 1999-04-05

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TW347596B (en) * 1995-11-13 1998-12-11 Motorola Inc Integrated electro-optical package
DE10034865B4 (en) * 2000-07-18 2006-06-01 Infineon Technologies Ag Opto-electronic surface-mountable module
US6759687B1 (en) * 2000-10-13 2004-07-06 Agilent Technologies, Inc. Aligning an optical device system with an optical lens system
JP2004031508A (en) 2002-06-24 2004-01-29 Nec Corp Optoelectric composite module and light inputting/outputting device with its module as configuring element
JP4492219B2 (en) * 2004-06-11 2010-06-30 日亜化学工業株式会社 Support substrate, method of forming semiconductor device using the support substrate, and semiconductor device
JP2007035881A (en) * 2005-07-26 2007-02-08 Matsushita Electric Works Ltd Mounting structure of surface-mounting electronic component and illumination instrument
WO2008004302A1 (en) * 2006-07-07 2008-01-10 Fujitsu Microelectronics Limited Solid-state imaging device and method of controlling the same
JP4718504B2 (en) 2007-03-07 2011-07-06 株式会社沖データ Display device
KR101616027B1 (en) * 2009-10-07 2016-04-27 삼성전자주식회사 Light emitting diode array integrated with lens, line printer head, and method of fabricating the light emitting diode array
EP3490015A1 (en) * 2010-03-23 2019-05-29 Asahi Rubber Inc. Silicone resin reflective substrate, manufacturing method for same, and base material composition used in reflective substrate
US8952402B2 (en) * 2011-08-26 2015-02-10 Micron Technology, Inc. Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and associated systems and methods
US8987892B2 (en) * 2013-05-10 2015-03-24 Raytheon Company Method for creating a selective solder seal interface for an integrated circuit cooling system
EP3235347B1 (en) * 2014-12-19 2020-05-13 Glo Ab Method of making a light emitting diode array on a backplane
JP2017059742A (en) * 2015-09-18 2017-03-23 株式会社デンソー Light-emitting device
JP2019511838A (en) 2016-04-04 2019-04-25 グロ アーベーＧｌｏ Ａｂ Backplane passing laser irradiation for die transfer

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