JP2871329B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2871329B2 JP2871329B2 JP22909592A JP22909592A JP2871329B2 JP 2871329 B2 JP2871329 B2 JP 2871329B2 JP 22909592 A JP22909592 A JP 22909592A JP 22909592 A JP22909592 A JP 22909592A JP 2871329 B2 JP2871329 B2 JP 2871329B2
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- signal input
- semiconductor integrated
- integrated circuit
- potential point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に外部回路と接続する信号入出力端子に対する静電破
壊防止用の回路を備えた半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit provided with a circuit for preventing electrostatic breakdown of a signal input / output terminal connected to an external circuit.
【０００２】[0002]
【従来の技術】近年、ＭＯＳ型の半導体集積回路におい
ては、高集積化実現の為の素子微細化により、静電破壊
対策が重要度を高めている。2. Description of the Related Art In recent years, in a MOS type semiconductor integrated circuit, measures against electrostatic destruction have become more important due to miniaturization of elements for realizing high integration.
【０００３】図３は静電破壊対策が施された従来の半導
体集積回路の一例を示す回路図である。FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit in which countermeasures against electrostatic breakdown are taken.
【０００４】この回路は、ドレインを電源電圧Ｖｃｃの
電源供給端子と接続しソースを信号入力端子ＴＭＩと接
続しゲートを基準電位点（接地電位点）と接続するＮ型
の第１のＭＯＳトランジスタＴ１、ドレインを信号入力
端子ＴＭＩと接続しソース及びゲートを接地電位点と接
続するＮ型の第２のＭＯＳトランジスタＴ２、並びに一
端を信号入力端子ＴＭＩと接続する抵抗Ｒ１を備えた静
電破壊防止回路１ｂと、入力端を抵抗Ｒ１の他端と接続
し抵抗Ｒ１を介して入力される信号ＩＮに対して所定の
処理を行う内部回路２とを有する構成となっている。In this circuit, an N-type first MOS transistor T1 having a drain connected to a power supply terminal of a power supply voltage Vcc, a source connected to a signal input terminal TMI, and a gate connected to a reference potential point (ground potential point). , An N-type second MOS transistor T2 having a drain connected to the signal input terminal TMI and a source and a gate connected to the ground potential point, and a resistor R1 having one end connected to the signal input terminal TMI. 1b, and an internal circuit 2 having an input terminal connected to the other end of the resistor R1 and performing a predetermined process on a signal IN input via the resistor R1.
【０００５】次にこの回路の動作について説明する。Next, the operation of this circuit will be described.
【０００６】信号入力端子ＴＭＩにＭＯＳトランジスタ
Ｔ１，Ｔ２のブレークダウン電圧を越える静電気による
パルス電圧が印加されると、ＭＯＳトランジスタＴ１，
Ｔ２はスナップバック状態となり、信号入力端子ＴＭＩ
は低抵抗で電源供給端子及び接地電位点に接続された状
態となり、前述のパルス電圧を電源供給端子及び接地電
位点に放電する。したがって、このパルス電圧による内
部回路２の入力端の電位は十分低い電位となり、静電気
による内部回路２等の破壊を防止することができる。When a pulse voltage due to static electricity exceeding the breakdown voltage of the MOS transistors T1, T2 is applied to the signal input terminal TMI, the MOS transistors T1, T2
T2 is in a snapback state, and the signal input terminal TMI
Is connected to the power supply terminal and the ground potential point with a low resistance, and discharges the pulse voltage to the power supply terminal and the ground potential point. Therefore, the potential of the input terminal of the internal circuit 2 due to the pulse voltage becomes sufficiently low, and it is possible to prevent the internal circuit 2 and the like from being damaged by static electricity.
【０００７】信号入力端子ＴＭＩに通常の入力信号（Ｉ
Ｎ）が印加される場合には、ＭＯＳトランジスタＴ１，
Ｔ２にブレークダウン電圧以下の電圧しか加わらない為
非導通状態であり、内部回路２の入力端の電位は信号入
力端子ＴＭＩとほぼ同電位となる。[0007] A normal input signal (I
N) is applied, the MOS transistors T1,
Since only a voltage equal to or lower than the breakdown voltage is applied to T2, it is in a non-conductive state, and the potential at the input terminal of the internal circuit 2 is substantially the same as the signal input terminal TMI.
【０００８】なお、ＭＯＳトランジスタＴ１，Ｔ２の基
板は、通常、負電位にバイアスされている。The substrates of the MOS transistors T1 and T2 are normally biased to a negative potential.
【０００９】[0009]
【発明が解決しようとする課題】この従来の半導体集積
回路では、信号入力端子ＴＭＩと接続する静電破壊防止
回路１ｂのＭＯＳトランジスタＴ１，Ｔ２の基板が通常
負電位にバイアスされているので、通常の動作状態で、
入力信号ＩＮにＭＯＳトランジスタＴ１のしきい値を越
える負電位のアンダーシュート等が発生すると、ＭＯＳ
トランジスタＴ１にインパクトイオン化電流が流れ、内
部回路２に１トランジスタ・１キャパシタ型のメモリセ
ルが含まれる場合、このメモリセルの記憶データを破壊
するという問題点があった。In this conventional semiconductor integrated circuit, the substrates of the MOS transistors T1 and T2 of the electrostatic discharge protection circuit 1b connected to the signal input terminal TMI are normally biased to a negative potential. In the operating state of
When an undershoot of a negative potential exceeding the threshold value of the MOS transistor T1 occurs in the input signal IN, the MOS
When an impact ionization current flows through the transistor T1 and the internal circuit 2 includes a one-transistor / one-capacitor type memory cell, there is a problem that data stored in the memory cell is destroyed.
【００１０】本発明の目的は、入力信号がＭＯＳトラン
ジスタのしきい地を越える負電位となっても、ＭＯＳト
ランジスタにインパクトイオン化電流が流れず、内部回
路のメモリセルの記憶データを破壊することのない半導
体集積回路を提供することにある。An object of the present invention is to prevent the impact ionization current from flowing through the MOS transistor even if the input signal has a negative potential exceeding the threshold of the MOS transistor, thereby destroying the data stored in the memory cell of the internal circuit. There is no need to provide a semiconductor integrated circuit.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体集積回路
は、ドレインを電源供給端子と接続しソースを信号入出
力端子と接続する第１のＭＯＳトランジスタ、ドレイン
を前記信号入出力端子と接続しソース及びゲートを基準
電位点と接続する第２のＭＯＳトランジスタ、ドレイン
を前記第１のＭＯＳトランジスタのゲートと接続しソー
スを前記信号入出力端子と接続しゲートを前記基準電位
点と接続する第３のＭＯＳトランジスタ、並びに前記第
３のＭＯＳトランジスタのドレインと前記基準電位点と
の間に接続された抵抗素子を備えた静電破壊防止回路
と、前記信号入出力端子と接続する内部回路とを有して
いる。A semiconductor integrated circuit according to the present invention has a first MOS transistor having a drain connected to a power supply terminal and a source connected to a signal input / output terminal, and a drain connected to the signal input / output terminal. A second MOS transistor having a source and a gate connected to the reference potential point, a third MOS transistor having a drain connected to the gate of the first MOS transistor, a source connected to the signal input / output terminal, and a gate connected to the reference potential point; MOS transistor, an electrostatic discharge protection circuit including a resistance element connected between the drain of the third MOS transistor and the reference potential point, and an internal circuit connected to the signal input / output terminal. doing.
【００１２】[0012]
【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【００１３】図１は本発明の第１の実施例を示す回路図
である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【００１４】この実施例は、ドレインを電源電圧Ｖｃｃ
の電源供給端子と接続しソースを信号入力端子ＴＭＩと
接続するＮ型の第１のＭＯＳトランジスタＴ１、ドレイ
ンを信号入力端子ＴＭＩと接続しソース及びゲートを基
準電位点（接地電位点）と接続するＮ型の第２のＭＯＳ
トランジスタＴ２３ドレインを第１のＭＯＳトランジス
タＴ１のゲートと接続しソースを信号入力端子ＴＭＩと
接続しゲートを接地電位点と接続するＮ型の第３のＭＯ
ＳトランジスタＴ３、一端を信号入力端子ＴＭＩと接続
する抵抗Ｒ１、並びに第３のＭＯＳトランジスタＴ３の
ドレインと接地電位点との間に接続された抵抗Ｒ２を備
えた静電破壊防止回路１と、抵抗Ｒ１を介して信号入力
端子ＴＭＩと接続する内部回路２とを有する構成となっ
ている。In this embodiment, the drain is connected to the power supply voltage Vcc.
, A source connected to the signal input terminal TMI, an N-type first MOS transistor T1, a drain connected to the signal input terminal TMI, and a source and a gate connected to a reference potential point (ground potential point). N-type second MOS
An N-type third MOS transistor having a transistor T23 drain connected to the gate of the first MOS transistor T1, a source connected to the signal input terminal TMI, and a gate connected to the ground potential point.
An electrostatic discharge protection circuit 1 including an S transistor T3, a resistor R1 having one end connected to the signal input terminal TMI, and a resistor R2 connected between the drain of the third MOS transistor T3 and a ground potential point; It has an internal circuit 2 connected to the signal input terminal TMI via R1.
【００１５】次にこの実施例の動作について説明する。Next, the operation of this embodiment will be described.
【００１６】信号入力端子ＴＭＩに、ＭＯＳトランジス
タＴ１，Ｔ２のブレークダウン電圧を越える静電気によ
るパルス電圧が印加されるとき、及び通常の入力信号Ｉ
Ｎが印加されるときの動作は図３に示された従来例と同
様であり、同様の効果を有する。When a pulse voltage due to static electricity exceeding the breakdown voltage of the MOS transistors T1 and T2 is applied to the signal input terminal TMI, and when the normal input signal I
The operation when N is applied is similar to that of the conventional example shown in FIG. 3, and has the same effect.
【００１７】ここで通常の動作状態で、入力信号ＩＮに
ＭＯＳトランジスタＴ１，Ｔ３のしきい値を越える負電
位のアンダーシュートが発生すると、ＭＯＳトランジス
タＴ３がオン状態となるので、ＭＯＳトランジスタＴ１
のゲート・ソース間の電圧はほぼ０Ｖとなり、ＭＯＳト
ランジスタＴ１はオフ状態のままとなっている。すなわ
ちインパクトイオン化電流が発生しない。従って、内部
回路２に１トランジスタ・１キャパシタ型のメモリセル
が含まれていても、このメモリセルの記憶データを破壊
することはない。Here, in a normal operation state, when an undershoot of a negative potential exceeding the threshold value of the MOS transistors T1 and T3 occurs in the input signal IN, the MOS transistor T3 is turned on, so that the MOS transistor T1 is turned on.
Is almost 0 V, and the MOS transistor T1 remains off. That is, no impact ionization current is generated. Therefore, even if the internal circuit 2 includes a one-transistor, one-capacitor type memory cell, the data stored in the memory cell is not destroyed.
【００１８】図２は本発明の第２の実施例を示す回路図
である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【００１９】この実施例は、静電破壊防止回路１ａを内
部回路２の信号出力端子ＴＭＯ側に設けたものであり、
基本的な動作及び効果は第１の実施例と同様であるの
で、これ以上の説明は省略する。In this embodiment, an electrostatic discharge protection circuit 1a is provided on the signal output terminal TMO side of the internal circuit 2.
The basic operation and effects are the same as those of the first embodiment, and further description will be omitted.
【００２０】なお、これら実施例において、抵抗Ｒ２を
トランジスタで置換えることもできる。In these embodiments, the resistor R2 can be replaced by a transistor.
【００２１】[0021]
【発明の効果】以上説明したように本発明は、第１のＭ
ＯＳトランジスタのゲート・ソース間に、ゲートを基準
電位点を接続する第３のＭＯＳトランジスタを設け、第
１のＭＯＳトランジスタのゲート・基準電位点との間に
抵抗素子を設けた構成とすることにより、通常の動作状
態で入力信号にこれらＭＯＳトランジスタのしきい値を
越える負電位のアンダーシュートが発生しても、第３の
ＭＯＳトランジスタが導通して第１のＭＯＳトランジス
タをオフ状態とするので、この第１のＭＯＳトランジス
タにインパクトイオン化電流が流れるのを防止し、内部
回路のメモリセルの記憶データの破壊を防止することが
できる効果がある。As described above, the present invention provides the first M
A third MOS transistor having a gate connected to a reference potential point is provided between the gate and source of the OS transistor, and a resistance element is provided between the gate and the reference potential point of the first MOS transistor. Even if an undershoot of a negative potential exceeding the threshold value of these MOS transistors occurs in the input signal in a normal operation state, the third MOS transistor is turned on and the first MOS transistor is turned off. There is an effect that an impact ionization current can be prevented from flowing through the first MOS transistor, and destruction of data stored in a memory cell of the internal circuit can be prevented.
【図１】本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【図３】従来の半導体集積回路の一例を示す回路図であ
る。FIG. 3 is a circuit diagram illustrating an example of a conventional semiconductor integrated circuit.
１，１ａ，１ｂ 静電破壊防止回路 ２ 内部回路 Ｒ１，Ｒ２ 抵抗 Ｔ１〜Ｔ３ ＭＯＳトランジスタ ＴＭＩ 信号入力端子 ＴＭＯ 信号出力端子 1, 1a, 1b Electrostatic discharge prevention circuit 2 Internal circuit R1, R2 Resistance T1 to T3 MOS transistor TMI signal input terminal TMO signal output terminal
Claims (2)
を信号入出力端子と接続する第１のＭＯＳトランジス
タ、ドレインを前記信号入出力端子と接続しソース及び
ゲートを基準電位点と接続する第２のＭＯＳトランジス
タ、ドレインを前記第１のＭＯＳトランジスタのゲート
と接続しソースを前記信号入出力端子と接続しゲートを
前記基準電位点と接続する第３のＭＯＳトランジスタ、
並びに前記第３のＭＯＳトランジスタのドレインと前記
基準電位点との間に接続された抵抗素子を備えた静電破
壊防止回路と、前記信号入出力端子と接続する内部回路
とを有することを特徴とする半導体集積回路。1. A first MOS transistor having a drain connected to a power supply terminal and a source connected to a signal input / output terminal, a second MOS transistor having a drain connected to the signal input / output terminal, and a source and a gate connected to a reference potential point. A third MOS transistor having a drain connected to the gate of the first MOS transistor, a source connected to the signal input / output terminal, and a gate connected to the reference potential point;
An electrostatic discharge protection circuit including a resistance element connected between the drain of the third MOS transistor and the reference potential point; and an internal circuit connected to the signal input / output terminal. Semiconductor integrated circuit.
求項１記載の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein the resistance element is formed by a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22909592A JP2871329B2 (en) | 1992-08-28 | 1992-08-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22909592A JP2871329B2 (en) | 1992-08-28 | 1992-08-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677413A JPH0677413A (en) | 1994-03-18 |
| JP2871329B2 true JP2871329B2 (en) | 1999-03-17 |
Family
ID=16886680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22909592A Expired - Lifetime JP2871329B2 (en) | 1992-08-28 | 1992-08-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2871329B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100323454B1 (en) * | 1999-12-31 | 2002-02-06 | 박종섭 | Elector static discharge protection circuit |
-
1992
- 1992-08-28 JP JP22909592A patent/JP2871329B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0677413A (en) | 1994-03-18 |
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