JP2869176B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2869176B2 JP2869176B2 JP29011290A JP29011290A JP2869176B2 JP 2869176 B2 JP2869176 B2 JP 2869176B2 JP 29011290 A JP29011290 A JP 29011290A JP 29011290 A JP29011290 A JP 29011290A JP 2869176 B2 JP2869176 B2 JP 2869176B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium
- semiconductor device
- contact hole
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は半導体装置の製造方法に係り、特に、配線構
造に関する （ロ）従来の技術 半導体装置が微細化されるにつれて、半導体装置の製
造に当って重要視されているものとして、配線技術があ
る。半導体装置が微細化され、素子との配線経路に設け
られる素子上のコンタクトホールのアスペクト比（コン
タクトホール深さ／コンタクトホールサイズ）が大きく
なると、従来のアルミニウム（A1）のスパッタによる配
線形成方法では、微細なコンタクトホール内に十分に配
線が埋め込まれず、接続不良となってしまう。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wiring structure. (B) Conventional technology As a semiconductor device is miniaturized, the semiconductor device is manufactured. In connection with this, there is a wiring technology that is regarded as important. As the semiconductor device is miniaturized and the aspect ratio (contact hole depth / contact hole size) of the contact hole on the element provided in the wiring path to the element increases, the conventional method of forming a wiring by sputtering of aluminum (A1) has become difficult. In addition, the wiring is not sufficiently buried in the fine contact hole, resulting in poor connection.
そこで、これを解決するべく、コンタクトホール内に
選択的にタングステン（Ｗ）膜を設け、このＷ膜を介し
て配線層を形成する方法や、配線層をバイアススパッタ
法を用いて形成する方法等が、検討されている（日経BP
社発行のVLSI製造技術に詳しい）。In order to solve this problem, a method of selectively providing a tungsten (W) film in a contact hole and forming a wiring layer through the W film, a method of forming the wiring layer by using a bias sputtering method, and the like. Is being considered (Nikkei BP
Familiar with VLSI manufacturing technology issued by the company)
その中で、Ｗ膜の選択形成方法は、他の方法に比べて
工程が簡単で、微細なコンタクトホール内への埋め込み
も十分に行うことができるため、盛んに検討されてい
る。Among them, the selective formation method of the W film is being actively studied because the process is simpler than the other methods and the W film can be sufficiently buried in a fine contact hole.
（ハ）発明が解決しようとする課題 ところで、配線を行う素子の表面、即ち、配線の下地
材料は、ｎ型Si、ｐ型Si、多結晶SiやWSix等、様々であ
る。従って、上述のような様々な下地材料に対してＷ膜
の選択形成法を用いて配線を行うと、配線の形成に先だ
って形成するＷ膜の成長速度が下地材料によって異な
り、その結果、Ｗ膜の膜厚がばらついてしまう。また、
下地材料が異なると、Ｗ膜の表面モフォロジーが変化
し、コンタクト抵抗等の電気的特性に影響を与える。(C) Problems to be Solved by the Invention By the way, the surface of the element for wiring, that is, the underlying material of the wiring, is various such as n-type Si, p-type Si, polycrystalline Si and WSix. Therefore, when wiring is performed on the various base materials as described above by using the selective formation method of the W film, the growth rate of the W film formed prior to the formation of the wiring differs depending on the base material. Will vary in thickness. Also,
If the base material is different, the surface morphology of the W film changes, which affects electrical characteristics such as contact resistance.
更に、PN接合上、例えば、シリコン基板表面のMOSト
ランジスタのソース／ドレイン領域上にＷ膜を形成した
場合には、ＷがPN接合中に拡散してこれを破壊するウォ
ームホール現象や、LOCOS酸化膜に近いコンタクトホー
ル内のＷがLOCOS酸化膜とシリコン基板との界面に進入
するエンクローチメント現象が発生し、PN接合の逆バイ
アス時のリーク電流が問題となる。Further, when a W film is formed on the PN junction, for example, on the source / drain region of the MOS transistor on the surface of the silicon substrate, the warm hole phenomenon in which W diffuses into the PN junction and destroys it, or the LOCOS oxidation occurs. An encroachment phenomenon occurs in which W in the contact hole close to the film enters the interface between the LOCOS oxide film and the silicon substrate, and the leakage current at the time of reverse bias of the PN junction becomes a problem.
（ニ）課題を解決するための手段 本発明の半導体装置の製造方法は、シリコン材からな
る第１導電部に通じるコンタクトホールの底部にチタン
膜を存在させる工程と、前記チタン膜を熱処理して、前
記第１導電部との接触部に、チタンシリサイド膜を形成
する工程と、前記チタン膜における実質的にシリサイド
化されていない表面側領域を窒化処理して、窒化チタン
膜を形成する工程と、前記コンタクトホール内にタング
ステン膜を形成する工程と、前記タングステン膜に電気
的に接続される第２導電部を形成する工程と、を含むこ
とをその要旨とする。(D) Means for Solving the Problems According to a method of manufacturing a semiconductor device of the present invention, there is provided a step of providing a titanium film at the bottom of a contact hole communicating with a first conductive portion made of a silicon material; Forming a titanium silicide film at a contact portion with the first conductive portion, and nitriding a substantially silicided surface-side region of the titanium film to form a titanium nitride film; The gist of the present invention includes a step of forming a tungsten film in the contact hole and a step of forming a second conductive portion electrically connected to the tungsten film.
（ホ）作用 すなわち、コンタクトホール内に積層されたチタンシ
リサイド膜や窒化チタン膜が、タングステン膜形成時の
下地材料依存性を解消する。(E) Function That is, the titanium silicide film or the titanium nitride film stacked in the contact hole eliminates the dependency on the underlying material when the tungsten film is formed.
また、チタンシリサイド膜や窒化チタン膜は、タング
ステン膜に対する拡散バリヤとなる。The titanium silicide film and the titanium nitride film serve as diffusion barriers for the tungsten film.
（ヘ）実施例 第１図Ａ乃至Ｄは、本発明の一実施例としてのMOSト
ランジスタである半導体装置を製造工程順に示す断面図
である。(F) Example FIGS. 1A to 1D are cross-sectional views showing a semiconductor device as a MOS transistor according to an example of the present invention in the order of manufacturing steps.
第１図Ａにおいて、ｐ型のシリコン基板１表面に、n+
型のソース／ドレイン領域２、２及びその間のゲート電
極３から成るMOSトランジスタ４と、MOSトランジスタ４
を電気的に分離するLOCOS構造の素子分離領域５、５
と、一方のソース／ドレイン領域２に接続されるように
素子分離領域５上方に横たわる多結晶シリコンの第１配
線層６と、シリコン基板１表面を覆う絶縁膜７とが形成
される。そして、他方のソース／ドレイン領域２及び第
１配線層６の一部を露出するように、絶縁膜７にコンタ
クトホール８、８が穿たれる。In FIG. 1A, n +
MOS transistor 4 comprising source / drain regions 2 and 2 of gate type and gate electrode 3 between them, and MOS transistor 4
LOCOS structure element isolation regions 5 and 5 for electrically isolating
Then, a first wiring layer 6 of polycrystalline silicon lying above the element isolation region 5 so as to be connected to one of the source / drain regions 2 and an insulating film 7 covering the surface of the silicon substrate 1 are formed. Then, contact holes 8, 8 are formed in insulating film 7 so as to expose the other source / drain region 2 and part of first wiring layer 6.
第１図Ｂにおいて、絶縁膜７表面及びコンタクトホー
ル８、８内周面全面に、DCマグネトロンスパッタ装置を
用い、基板温度200℃、真空度8mTorrの条件で、膜厚約5
00ÅのTi膜９が形成される。In FIG. 1B, a DC magnetron sputtering device is used to cover the surface of the insulating film 7 and the entire inner peripheral surface of the contact holes 8 and 8 at a substrate temperature of 200 ° C. and a degree of vacuum of 8 mTorr, and a film thickness of about 5 mm.
A 00 ° Ti film 9 is formed.
第１図Ｃにおいて、N2雰囲気、600℃の温度及び処理
時間30秒間の条件で、急速熱アニール処理（Rapid Ther
mal Anneal）を行い、Ti膜９とSiとが接触している箇
所、即ち、コンタクトホール８、８底面において他方の
ソース／ドレイン領域２及び第１配線層６と接触するTi
膜９の接触側領域が、TiSi2膜10とされる。その後、コ
ンタクトホール８、８底面以外のTi膜９がエッチング除
去される。In FIG. 1C, rapid thermal annealing (Rapid Ther) was performed under the conditions of an N 2 atmosphere, a temperature of 600 ° C., and a processing time of 30 seconds.
(Mal Anneal), and the contact between the Ti film 9 and the Si, that is, the contact with the other source / drain region 2 and the first wiring layer 6 at the bottom of the contact holes 8, 8.
The contact side region of the film 9 is a TiSi 2 film 10. Thereafter, the Ti film 9 other than the contact holes 8 and 8 is etched away.
更に、N2雰囲気、900℃の温度及び処理時間30秒間の
条件で、急速熱アニール処理を行い、Ti膜９のTiSi2膜1
0となっていない表面側領域が、TiN膜11に変化される。Further, rapid thermal annealing is performed under the conditions of an N 2 atmosphere, a temperature of 900 ° C., and a processing time of 30 seconds, and the TiSi 2 film 1
The surface side region that is not 0 is changed to the TiN film 11.
こうして、コンタクトホール８、８内に、TiSi2膜10/
TiN膜11の積層体が形成される。Thus, the TiSi 2 film 10 /
A laminate of the TiN film 11 is formed.
第１図Ｄにおいて、コンタクトホール８、８内のTiN
膜11上に、減圧CVD法により、基板温度260℃、ガス流量
比SiH4/WF6＝0.7及び真空度60mTorrの条件で、膜厚5000
ÅのＷ膜12が選択的に形成される。更に、スパッタ法を
用いて、Al合金から成る第２配線層13が、コンタクトホ
ール８、８内のTiSi2膜10/TiN膜11/W膜12の積層体を介
して、他方のソース／ドレイン領域２と第１配線層６と
を接続するように絶縁膜７上に形成される。In FIG. 1D, TiN in contact holes 8
On the film 11, by a low pressure CVD method, the substrate temperature 260 ° C., under the conditions of gas flow ratio SiH 4 / WF 6 = 0.7 and vacuum 60 mTorr, the film thickness 5000
The W film 12 is selectively formed. Further, by using a sputtering method, the second wiring layer 13 made of an Al alloy is connected to the other source / drain through the laminate of the TiSi 2 film 10 / TiN film 11 / W film 12 in the contact holes 8 and 8. It is formed on insulating film 7 so as to connect region 2 and first wiring layer 6.
以上のように、Ｗ膜12はTiSi2膜10/TiN膜11の積層体
上に形成されるため、従来のように、Ｗ膜12は、下地材
料に影響されて、その膜厚にばらつきが生じることもな
く、その膜厚の均一性は、±５％の範囲に収まる。As described above, since the W film 12 is formed on the stacked body of the TiSi 2 film 10 / TiN film 11, the W film 12 is affected by the base material and the thickness thereof varies as in the related art. Without any occurrence, the uniformity of the film thickness falls within a range of ± 5%.
（ト）発明の効果 本発明にあっては、コンタクトホール内に積層された
チタンシリサイド膜や窒化チタン膜が、タングステン膜
形成時の下地材料依存性を解消してタングステン膜の膜
厚のばらつきを抑制することができる。(G) Effects of the Invention In the present invention, the titanium silicide film or the titanium nitride film laminated in the contact hole eliminates the dependency of the base material when forming the tungsten film, thereby reducing the variation in the thickness of the tungsten film. Can be suppressed.
また、チタンシリサイド膜や窒化チタン膜が、タング
ステン膜に対する拡散バリヤとなり、PN接合のリーク電
流を抑えることができる。Further, the titanium silicide film or the titanium nitride film serves as a diffusion barrier for the tungsten film, and can suppress the leakage current of the PN junction.
第１図Ａ乃至Ｄは本発明の半導体装置を製造工程順に示
す断面図である。1A to 1D are sectional views showing a semiconductor device of the present invention in the order of manufacturing steps.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/28 - 21/288 H01L 21/3205 H01L 21/3213 H01L 21/44 - 21/445 H01L 21/768 H01L 29/40 - 29/51 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. 6 , DB name) H01L 21/28-21/288 H01L 21/3205 H01L 21/3213 H01L 21/44-21/445 H01L 21 / 768 H01L 29/40-29/51
Claims (1)
ンタクトホールの底部にチタン膜を存在させる工程と、 前記チタン膜を熱処理して、前記第１導電部との接触部
に、チタンシリサイド膜を形成する工程と、 前記チタン膜における実質的にシリサイド化されていな
い表面側領域を窒化処理して、窒化チタン膜を形成する
工程と、 前記コンタクトホール内にタングステン膜を形成する工
程と、 前記タングステン膜に電気的に接続される第２導電部を
形成する工程と、 を含むことを特徴とした半導体装置の製造方法。A step of providing a titanium film at a bottom of a contact hole communicating with a first conductive portion made of a silicon material; a heat treatment of the titanium film to form a titanium silicide film at a contact portion with the first conductive portion. Forming a titanium nitride film by nitriding a substantially non-silicided surface side region of the titanium film; forming a tungsten film in the contact hole; Forming a second conductive portion electrically connected to the tungsten film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29011290A JP2869176B2 (en) | 1990-10-25 | 1990-10-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29011290A JP2869176B2 (en) | 1990-10-25 | 1990-10-25 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04162674A JPH04162674A (en) | 1992-06-08 |
| JP2869176B2 true JP2869176B2 (en) | 1999-03-10 |
Family
ID=17751956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29011290A Expired - Lifetime JP2869176B2 (en) | 1990-10-25 | 1990-10-25 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2869176B2 (en) |
-
1990
- 1990-10-25 JP JP29011290A patent/JP2869176B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04162674A (en) | 1992-06-08 |
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