JP2847890B2 - Method of manufacturing semiconductor substrate for three-dimensional mounting - Google Patents
Method of manufacturing semiconductor substrate for three-dimensional mountingInfo
- Publication number
- JP2847890B2 JP2847890B2 JP11344690A JP11344690A JP2847890B2 JP 2847890 B2 JP2847890 B2 JP 2847890B2 JP 11344690 A JP11344690 A JP 11344690A JP 11344690 A JP11344690 A JP 11344690A JP 2847890 B2 JP2847890 B2 JP 2847890B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- hole
- electrode pad
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は３次元高密度実装用の半導体回路基板の製造
方法に関する。The present invention relates to a method for manufacturing a semiconductor circuit board for three-dimensional high-density mounting.
＜従来の技術＞ 高密度３次元ICを得るためには、回路が形成された半
導体基板を多層に積層して、相互に電気的に接続する必
要がある。<Prior Art> In order to obtain a high-density three-dimensional IC, it is necessary to laminate semiconductor substrates on which circuits are formed in multiple layers and to electrically connect them.
従来、３次元ICを得る技術としては、各ICの入出力間
における張り合わせ方式、また素子レベルでの張り合わ
せ方式、あるいはモノリシック方式などがある。これら
の方式のうち、入出力間における張り合わせ方式は、技
術上の問題が少なく生産が容易で、かつ歩留りが高い
点、さらには種々の機能をもつICを積層できるなどの利
点がある。Conventionally, as a technique for obtaining a three-dimensional IC, there are a bonding method between input and output of each IC, a bonding method at an element level, a monolithic method, and the like. Among these methods, the bonding method between the input and the output has advantages that there are few technical problems, the production is easy, the yield is high, and ICs having various functions can be stacked.
＜発明が解決しようとする課題＞ ところで、上述の入出力間での張り合わせ方式におい
ては、パッド電極の面積を大きくとる必要があり、集積
度の高度化は困難で、しかも、各ICチップ間に隙間があ
るため、チップの冷却効果が低いといった問題が残され
ている。<Problems to be Solved by the Invention> In the above-described bonding method between the input and output, it is necessary to increase the area of the pad electrode, and it is difficult to increase the degree of integration. Since there is a gap, a problem that the cooling effect of the chip is low remains.
＜課題を解決するための手段＞ 上記の従来の問題点を解決するために、本発明では、
実施例に対応する第１図に示すように、一面に回路1aお
よび電極パッド1bが形成された半導体基板１に、その電
極パッド1bの形成位置に貫通孔２を開孔した後、半導体
基板１に絶縁物３を積層して貫通孔２を充填し、次い
で、貫通孔２に充填した絶縁物３に貫通孔２よりも小さ
なスルーホール４を穿って、上記電極パッド1bを上記半
導体基板１の他面側に露呈させた後、その半導体基板１
の他面に、スルーホール４を通して電極パッド1bに導通
する接続パッド５を形成することを特徴とするものであ
る。<Means for Solving the Problems> In order to solve the above conventional problems, the present invention provides:
As shown in FIG. 1 corresponding to the embodiment, a semiconductor substrate 1 having a circuit 1a and an electrode pad 1b formed on one surface is provided with a through hole 2 at a position where the electrode pad 1b is formed. A through hole 2 is filled by laminating an insulator 3 on the semiconductor substrate 1, and a through hole 4 smaller than the through hole 2 is formed in the insulator 3 filled in the through hole 2, and the electrode pad 1 b is After exposing to the other side, the semiconductor substrate 1
On the other surface, a connection pad 5 which is electrically connected to the electrode pad 1b through the through hole 4 is formed.
＜作用＞ 半導体基板１の両面にスルーホール４を通して互いに
導通するパッド1bおよび接続パッド５を形成することに
より、半導体基板１を多層に積層するにあたり、各基板
１を直接的に張り合わせることが可能となる。この場
合、スルーホール４は、絶縁物３によって半導体基板１
に対して電気的に絶縁されているため、スルーホール４
を通して信号入出力が行われても、半導体基板１にその
影響が波及することを防止することができる。<Operation> By forming the pads 1b and the connection pads 5 which are electrically connected to each other through the through holes 4 on both surfaces of the semiconductor substrate 1, the respective substrates 1 can be directly bonded to each other when the semiconductor substrates 1 are stacked in multiple layers. Becomes In this case, the through-hole 4 is formed by the insulator 3 on the semiconductor substrate 1.
Is electrically insulated from the
Even if signal input / output is performed through the semiconductor substrate, it is possible to prevent the influence from being transmitted to the semiconductor substrate 1.
＜実施例＞ 以下、本発明の実施例を図面に基づいて説明する。<Example> Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明実施例の工程説明図である。 FIG. 1 is a process explanatory view of an embodiment of the present invention.
まず、（ａ）に示すように、一面に回路1aおよび電極
パッド1bを形成したSi基板１の回路1aの側の一面を、支
持基板としてのSiO2基板11に接着し、この状態で、Si基
板１を研磨して数μｍ程度の厚さにする（ｂ）。First, as shown in (a), one surface of the Si substrate 1 on which the circuit 1a and the electrode pad 1b are formed on one side of the circuit 1a is adhered to an SiO 2 substrate 11 as a support substrate. The substrate 1 is polished to a thickness of about several μm (b).
次に、RIE（リアクティブイオンエッチング）法など
により、電極パッド1bの形成位置に貫通孔２を開孔した
後（ｃ）、CVD法により、SiO2などの絶縁物３を貫通孔
２に充填するとともに、Si基板１の研磨面に積層する
（ｄ）。Then, due to RIE (reactive ion etching) method, after opening the through-holes 2 in the forming positions of the electrode pads 1b (c), by a CVD method, filled with an insulating material 3 such as SiO 2 in the through holes 2 At the same time, it is laminated on the polished surface of the Si substrate 1 (d).
次に、RIE法などにより貫通孔２に充填した絶縁物３
の窓明けを行って、その貫通孔２よりも小さなスルーホ
ール４を形成する（ｅ）。そして、スタッパもしくは蒸
着法などによって、Alなどの導電性物質を成膜した後、
その膜のパターニングを行うことによって、（ｆ）に示
すように、電極パッド1bにスルーホール４を通して導通
する接続パッド５を得る。以上の手順により、厚さが数
μｍ程度で、かつ両面にパッド1aおよび接続パッド５が
形成されたSi半導体回路基板を得ることができる。Next, the insulator 3 filled in the through hole 2 by RIE or the like is used.
(E) to form a through hole 4 smaller than the through hole 2. Then, after forming a conductive material such as Al by a stacker or an evaporation method,
By patterning the film, a connection pad 5 that is electrically connected to the electrode pad 1b through the through hole 4 is obtained as shown in FIG. According to the above procedure, a Si semiconductor circuit substrate having a thickness of about several μm and having the pads 1a and the connection pads 5 formed on both surfaces can be obtained.
以上のような半導体回路基板を、一般に用いられてい
るICの張り合わせ法によって、３次元化するわけである
が、その方法を以下に述べる。第２図はその手順を説明
する図である。The above-described semiconductor circuit board is made three-dimensional by a commonly used IC bonding method. The method will be described below. FIG. 2 is a diagram for explaining the procedure.
まず、第１図の工程で得られた半導体回路基板の接続
パッド５上に、張り合わせのための垂直配線６を形成す
る（ａ）。なお、７は絶縁膜である。次いで、（ｂ）に
示すように、ポリイミド８により表面の平坦化を行って
おく。First, a vertical wiring 6 for bonding is formed on the connection pad 5 of the semiconductor circuit board obtained in the step of FIG. 1 (a). Reference numeral 7 denotes an insulating film. Next, as shown in (b), the surface is flattened with polyimide 8.
次に、上記の（ａ），（ｂ）工程において得られた回
路基板を二つ用意しておき、この二つの回路基板を
（ｃ）に示すように、相互に対向させ、かつ、その垂直
配線６を互いに接続させた状態で、その両者を熱圧着に
より接続する。次いで、支持基板としてのSiO2基板11の
いずれか一方を剥がすことによって、（ｄ）に示すよう
な積層構造を得る。そして以上の（ａ）〜（ｄ）工程を
順次繰り返すことによって、半導体回路が多層に積層さ
れた構造、つまり３次元ICを実現することができる。こ
のような３次元ICで例えばセンサ用の増幅回路などを作
成することによって、センサチップと一体化したコンパ
クトなセンサユニットを構築することができる。Next, two circuit boards obtained in the above steps (a) and (b) are prepared, and these two circuit boards are opposed to each other as shown in FIG. With the wires 6 connected to each other, the two are connected by thermocompression bonding. Next, one of the SiO 2 substrates 11 as a supporting substrate is peeled off, thereby obtaining a laminated structure as shown in FIG. By sequentially repeating the above steps (a) to (d), a structure in which semiconductor circuits are stacked in multiple layers, that is, a three-dimensional IC can be realized. By creating, for example, an amplifier circuit for a sensor using such a three-dimensional IC, a compact sensor unit integrated with a sensor chip can be constructed.
なお、以上の本発明実施例によると、半導体基板１に
穿った貫通孔２に絶縁物３を充填した後、その絶縁物３
に、貫通孔２よりも小さいスルーホール４を形成するの
で、後の工程においてそのスルーホール４の内部に充填
される導電材は、半導体基板１に対して電気的に絶縁さ
れ、これにより信号入出力による影響が半導体基板１に
波及することなどを防止することができる。According to the above embodiment of the present invention, after the insulator 3 is filled in the through hole 2 formed in the semiconductor substrate 1, the insulator 3 is filled.
Since the through hole 4 smaller than the through hole 2 is formed, the conductive material filled in the through hole 4 in a later step is electrically insulated from the semiconductor substrate 1 so that the signal input can be performed. It is possible to prevent the influence of the output from spreading to the semiconductor substrate 1.
＜発明の効果＞ 以上説明したように、本発明によれば、半導体基板の
両面に、その基板そのものに形成したスルーホールを通
して互いに導電するパッドを形成したことにより、任意
複数枚の半導体基板を多層化することが可能となり、大
規模の３次元ICを容易に実現することができる。しか
も、各半導体基板を直接的に張り合わせることができる
ことから、そのパッド面積を狭くすることが可能とな
り、高密度の３次元ICを得ることができるとともに、半
導体基板の冷却効果も向上する。また、スルーホール内
に充填される導電材は、絶縁物によって半導体基板に対
して電気的に絶縁されていることから、信号入出力によ
る影響が半導体基板に波及することなどを防止すること
ができる。<Effects of the Invention> As described above, according to the present invention, by forming pads that are mutually conductive through the through holes formed in the substrate itself on both surfaces of the semiconductor substrate, an arbitrary plurality of semiconductor substrates can be multilayered. And a large-scale three-dimensional IC can be easily realized. In addition, since the semiconductor substrates can be directly bonded, the pad area can be reduced, and a high-density three-dimensional IC can be obtained, and the cooling effect of the semiconductor substrate can be improved. In addition, since the conductive material filled in the through hole is electrically insulated from the semiconductor substrate by the insulator, it is possible to prevent the influence of the signal input / output from spreading to the semiconductor substrate. .
第１図は本発明実施例の工程説明図、第２図は本発明実
施例によって得られた半導体回路基板を用いて、３次元
ICを構築する手順の例を説明する図である。 １……Si基板 1a……回路 1b……電極パッド ２……貫通孔 ３……絶縁物 ４……スルーホール ５……接続パッド ６……垂直配線 ７……絶縁膜 ８……ポリイミドFIG. 1 is an explanatory view of a process of an embodiment of the present invention, and FIG. 2 is a three-dimensional view using a semiconductor circuit board obtained by the embodiment of the present invention.
FIG. 9 is a diagram illustrating an example of a procedure for constructing an IC. DESCRIPTION OF SYMBOLS 1 ... Si board | substrate 1a ... Circuit 1b ... Electrode pad 2 ... Through-hole 3 ... Insulator 4 ... Through-hole 5 ... Connection pad 6 ... Vertical wiring 7 ... Insulating film 8 ... Polyimide
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 27/00 301 H01L 21/337 - 21/338 H01L 29/80 - 29/812Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 27/00 301 H01L 21/337-21/338 H01L 29/80-29/812
Claims (1)
半導体基板に、その電極パッドの形成位置に貫通孔を開
孔した後、半導体基板に絶縁物を積層して貫通孔を充填
し、次いで、貫通孔に充填した絶縁物に貫通孔よりも小
さなスルーホールを穿って上記電極パッドを上記半導体
基板の他面側に露呈させた後、その半導体基板の他面
に、上記スルーホールを通して上記電極パッドに導通す
る接続パッドを形成することを特徴とする３次元実装用
半導体基板の製造方法。1. A semiconductor substrate having a circuit and an electrode pad formed on one surface, a through hole is formed at a position where the electrode pad is formed, an insulator is laminated on the semiconductor substrate to fill the through hole, and After drilling a through hole smaller than the through hole in the insulator filled in the through hole and exposing the electrode pad to the other surface of the semiconductor substrate, the electrode pad is passed through the through hole to the other surface of the semiconductor substrate. A method of manufacturing a three-dimensional mounting semiconductor substrate, comprising forming a connection pad that is electrically connected to a pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11344690A JP2847890B2 (en) | 1990-04-27 | 1990-04-27 | Method of manufacturing semiconductor substrate for three-dimensional mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11344690A JP2847890B2 (en) | 1990-04-27 | 1990-04-27 | Method of manufacturing semiconductor substrate for three-dimensional mounting |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0410649A JPH0410649A (en) | 1992-01-14 |
| JP2847890B2 true JP2847890B2 (en) | 1999-01-20 |
Family
ID=14612439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11344690A Expired - Lifetime JP2847890B2 (en) | 1990-04-27 | 1990-04-27 | Method of manufacturing semiconductor substrate for three-dimensional mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2847890B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9401183B2 (en) | 1997-04-04 | 2016-07-26 | Glenn J. Leedy | Stacked integrated memory device |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5915167A (en) * | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
| JP2003289073A (en) | 2002-01-22 | 2003-10-10 | Canon Inc | Semiconductor device and method of manufacturing semiconductor device |
| US7402897B2 (en) | 2002-08-08 | 2008-07-22 | Elm Technology Corporation | Vertical system integration |
| JP2012178520A (en) * | 2011-02-28 | 2012-09-13 | Elpida Memory Inc | Semiconductor apparatus and manufacturing method thereof |
-
1990
- 1990-04-27 JP JP11344690A patent/JP2847890B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9401183B2 (en) | 1997-04-04 | 2016-07-26 | Glenn J. Leedy | Stacked integrated memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0410649A (en) | 1992-01-14 |
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