JP2834878B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP2834878B2 JP2834878B2 JP2262495A JP26249590A JP2834878B2 JP 2834878 B2 JP2834878 B2 JP 2834878B2 JP 2262495 A JP2262495 A JP 2262495A JP 26249590 A JP26249590 A JP 26249590A JP 2834878 B2 JP2834878 B2 JP 2834878B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- plating layer
- integrated circuit
- heat
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は高周波高出力に適した混成集積回路に関す
る。The present invention relates to a hybrid integrated circuit suitable for high frequency and high output.
（ロ）従来の技術 TV,HDTV等のビデオ出力回路を集積化したビデオバッ
ク（商品名）となる混成集積回路が本願出願人において
商品化されている。このような回路は高周波高出力が求
められるため、回路基板としてセラミックの如き低誘電
率素材を用い、この表面に回路導体とチップ素子を固着
した構成を採っている（例えば、特開昭62−224951号公
報参照）。(B) Conventional technology A hybrid integrated circuit serving as a video back (product name) in which video output circuits such as TV and HDTV are integrated has been commercialized by the applicant of the present application. Since such a circuit is required to have a high output at a high frequency, a low dielectric constant material such as ceramic is used as a circuit board, and a circuit conductor and a chip element are fixed to the surface of the circuit (for example, see Japanese Patent Application Laid-Open No. Sho 62-62). 224951).
具体的な構成を第４図に示す。（１）は銅やアルミダ
イキャスト等の熱伝導性良好なる放熱基板、（２）は放
熱基板（１）の上に半田を介して固着したセラミック基
板、（３）はセラミック基板（２）の上に描画した導電
薄膜から成る回路導体、（４）は回路導体（３）に半田
又はワイヤにより電気接続される抵抗、コンデンサ、コ
イル等のチップ素子、（５）はセラミック基板（２）上
にヒートスプレッダ（６）を介して固着され且つ回路導
体（３）とワイヤ（８）と接続されるNPN、PNPトランジ
スタ等の半導体チップである。セラミック基板（２）に
は外部接続用のリード端子（図示せず）が半田付けさ
れ、凹状の上蓋（７）を放熱基板（１）と対向接着する
ことによりパッケージングする。ヒートスプレッダ
（６）は熱伝導率に優れた素材から成り、セラミック基
板（２）との接触面積を増大することによって半導体チ
ップ（５）の放熱性を向上させる。また、ヒートスプレ
ッダ（６）の表裏面には半田付のための金メッキ層が全
面に処されている。FIG. 4 shows a specific configuration. (1) is a heat dissipation board having good thermal conductivity such as copper or aluminum die-cast, (2) is a ceramic board fixed on the heat dissipation board (1) via solder, and (3) is a ceramic board (2). A circuit conductor composed of a conductive thin film drawn above, (4) a chip element such as a resistor, a capacitor or a coil electrically connected to the circuit conductor (3) by soldering or a wire, and (5) a ceramic substrate (2) It is a semiconductor chip such as an NPN or PNP transistor which is fixed via a heat spreader (6) and is connected to the circuit conductor (3) and the wire (8). Lead terminals (not shown) for external connection are soldered to the ceramic substrate (2), and the concave upper lid (7) is bonded to the heat radiation substrate (1) by opposing bonding to package. The heat spreader (6) is made of a material having excellent thermal conductivity, and improves the heat dissipation of the semiconductor chip (5) by increasing the contact area with the ceramic substrate (2). Further, a gold plating layer for soldering is entirely applied to the front and back surfaces of the heat spreader (6).
（ハ）発明が解決しようとする課題 しかしながら、前記ビデオ出力回路のように扱う信号
が高周波であると各部の浮遊容量が高周波特性劣化の要
因となる。従来のヒートスプレッダ（６）は表裏全面に
金メッキ層を処してあるので、ヒートスプレッダ（６）
自身の容量が大きく、これが半導体チップ（５）の対GN
D間容量として働く他、表面側の金メッキ層とワイヤ
（８）間等で浮遊容量を形成し半導体チップ（５）上に
形成した回路素子の高周波特性を劣化させる欠点があっ
た。(C) Problems to be Solved by the Invention However, if a signal handled like the video output circuit has a high frequency, the stray capacitance of each part causes a deterioration in high-frequency characteristics. Since the conventional heat spreader (6) has a gold plating layer on the entire front and back surfaces, the heat spreader (6)
Its own capacity is large, and this is the GN of the semiconductor chip (5).
In addition to acting as an inter-D capacitance, there is a drawback that a stray capacitance is formed between the gold plating layer on the surface side and the wire (8) or the like, thereby deteriorating the high frequency characteristics of the circuit element formed on the semiconductor chip (5).
特にコストダウンを目的として樹脂モールドタイプに
すると、樹脂の誘電率が空気中より高い（εｒ≒4.0）
ためにこの様な問題が顕著となる。Especially when resin mold type is used for cost reduction, the dielectric constant of resin is higher than that in air (εr （4.0)
Therefore, such a problem becomes remarkable.
（ニ）課題を解決するための手段 本発明は上記従来の欠点に鑑み成されたもので、表裏
面に金メッキ層（20a）（20b）を処したヒートスプレッ
ダ（13）において、半導体チップ（14）を固着する側の
金メッキ層（20a）を前記半導体チップ（14）を載置す
るに足りる面積まで縮小することによって、浮遊容量の
小さい混成集積回路を提供するものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and has a heat spreader (13) in which gold plating layers (20a) and (20b) are processed on the front and back surfaces, and a semiconductor chip (14). The present invention provides a hybrid integrated circuit having a small floating capacitance by reducing the gold plating layer (20a) on the side to which the semiconductor chip (14) is fixed to an area sufficient for mounting the semiconductor chip (14).
（ホ）作用 本発明によれば、半導体チップ（14）を固着する側の
金メッキ層（20a）の面積を小さくしたことによって、
ヒートスプレッダ（13）の裏面の金メッキ層（20a）と
の対向面積を小さくできるので、金メッキ層（20a）（2
0b）間で形成される容量を小さくできる。また、ワイヤ
（21）等との対向面積も減らせるので、浮遊容量を小さ
くできる。(E) Function According to the present invention, by reducing the area of the gold plating layer (20a) on the side to which the semiconductor chip (14) is fixed,
Since the area facing the gold plating layer (20a) on the back of the heat spreader (13) can be reduced, the gold plating layer (20a) (2
The capacitance formed between 0b) can be reduced. Further, since the area facing the wire (21) and the like can be reduced, the stray capacitance can be reduced.
（ヘ）実施例 以下に本発明の一実施例を図面を参照しながら詳細に
説明する。(F) Embodiment One embodiment of the present invention will be described below in detail with reference to the drawings.
第１図は本発明による混成集積回路のチップ取付部を
示す斜視断面図、第２図は平面図、第３図は断面図であ
る。これらの図において、（11）は放熱基板、（12）は
セラミック基板、（13）はヒートスプレッダ、（14）は
半導体チップである。FIG. 1 is a perspective sectional view showing a chip mounting portion of a hybrid integrated circuit according to the present invention, FIG. 2 is a plan view, and FIG. 3 is a sectional view. In these figures, (11) is a heat dissipation substrate, (12) is a ceramic substrate, (13) is a heat spreader, and (14) is a semiconductor chip.
放熱基板（11）は板厚0.2〜1.0mmの銅系素材から成る
平板状材料であり、表面には半田濡れ性向上と銅系素材
の酸化防止のためのNiメッキを処し、放熱基板（11）の
両端にはパッケージを放熱部材に取付けるビスを挿通す
るためのＵ字型の切欠き（15）を有する。Ｕ字型の他は
円型の貫通孔等が考えられる。The heat dissipating substrate (11) is a flat plate material made of a copper-based material having a thickness of 0.2 to 1.0 mm, and the surface thereof is plated with Ni for improving solder wettability and preventing oxidation of the copper-based material. Each of the two ends has a U-shaped notch (15) for inserting a screw for attaching the package to the heat dissipation member. In addition to the U-shape, a circular through-hole or the like is conceivable.
セラミック基板（12）は板厚0.2〜1.0mmのアルミナ
（Al2O3）素材から成り、裏面に半田濡れ性のための例
えば銀パラジウム層を設け、表面側には回路網を構成す
るための導電薄膜から成る回路導体（16）を設ける。回
路導体（16）は例えば銅ペーストのスクリーン印刷手法
によって描画し、この回路導体（16）にコンデンサやコ
イル等のチップ部品（17）を半田付け固着する。チップ
部品（17）を組立てたセラミック基板（12）は、放熱基
板（11）の略中央付近に半田付け固着し、銀メッキした
外部接続リード（18）とセラミック基板（12）の接続パ
ッドとをワイヤボンドすることで電気接続する。The ceramic substrate (12) is made of an alumina (Al 2 O 3 ) material having a thickness of 0.2 to 1.0 mm, and is provided with, for example, a silver palladium layer on the back surface for solder wettability, and a circuit network on the front surface side. A circuit conductor (16) made of a conductive thin film is provided. The circuit conductor (16) is drawn by, for example, a screen printing method using copper paste, and a chip component (17) such as a capacitor or a coil is fixed to the circuit conductor (16) by soldering. The ceramic substrate (12) on which the chip parts (17) are assembled is soldered and fixed near the center of the heat radiation substrate (11). Electrical connection is made by wire bonding.
セラミック基板（12）には搭載する能動素子の数に対
応する数の貫通孔（19）を形成し、この貫通孔（19）内
に発熱を伴う個別半導体を形成した半導体チップ（14）
を配置する。貫通孔（19）はセラミック基板（12）の金
型成形で作成し、セラミック基板（12）の略中央付近に
熱分散を考慮して配置した。A semiconductor chip (14) in which through holes (19) corresponding to the number of active elements to be mounted are formed in a ceramic substrate (12), and individual semiconductors that generate heat are formed in the through holes (19).
Place. The through hole (19) was formed by molding a ceramic substrate (12), and was arranged near the center of the ceramic substrate (12) in consideration of heat dispersion.
半導体チップ（14）はシリコン基板の表面にホトリソ
グラフィー技術と拡散技術を駆使してNPN、PNPトランジ
スタやMOSFET等を形成したもので、前記シリコン基板の
裏面を１つの電極取出しとする。The semiconductor chip (14) is formed by forming an NPN, PNP transistor, MOSFET, or the like on the surface of a silicon substrate by using photolithography and diffusion techniques, and the back surface of the silicon substrate is taken out as one electrode.
ヒートスプレッダ（13）は、ベリリア（B2O3）や窒化
アルミニウム（AlN）等の熱伝導率に優れた絶縁材料か
ら成る板厚0.5〜0.7mmの板状材料であり、外形は大体2.
0×2.0mmの如き正方形を成す。その表裏両面には半田濡
れ性向上のために金メッキ層（20a）を形成し、半導体
チップ（14）を載置する側の金メッキ層（20a）は一部
分に、反対側の金メッキ層（20b）は全面に形成する。Heat spreader (13) is a plate-like material thickness 0.5~0.7mm consisting beryllia (B 2 O 3) or aluminum nitride (AlN) excellent insulating material thermal conductivity, such as, the outer shape is roughly 2.
Form a square such as 0x2.0mm. A gold plating layer (20a) is formed on both front and back surfaces to improve solder wettability. The gold plating layer (20a) on the side on which the semiconductor chip (14) is mounted is partially formed, and the gold plating layer (20b) on the opposite side is formed. Formed over the entire surface.
そして第１図に示す通り、セラミック基板（12）の貫
通孔（19）内に先ずヒートスプレッダ（13）を放熱基板
（11）表面に半田付固着し、次いでヒートスプレッダ
（13）表面の金メッキ層（20a）上に銀ロー等で半導体
チップ（14）をダイボンドし、さらに半導体チップ（1
4）表面に形成した図示せぬ電極と回路導体（16）とを
ワイヤ（21）とをワイヤボンドする。半導体チップ（1
4）の基板電位は金メッキ層（20a）を介して取出す。Then, as shown in FIG. 1, a heat spreader (13) is first soldered and fixed to the surface of the heat radiating substrate (11) in the through hole (19) of the ceramic substrate (12), and then a gold plating layer (20a) on the surface of the heat spreader (13) is formed. The semiconductor chip (14) is die-bonded with a silver solder or the like, and the semiconductor chip (1
4) The electrode (not shown) formed on the surface and the circuit conductor (16) are wire-bonded to the wire (21). Semiconductor chip (1
The substrate potential in 4) is extracted through the gold plating layer (20a).
半導体チップ（14）を固着する側の金メッキ層（20
a）は、半導体チップ（14）の大きさ（0.3×0.3mm〜0.6
×0.6mm）にダイボンド時の位置合わせ精度とワイヤ（2
1）を打てるだけの余裕を持たせた大きさまで縮小す
る。ワイヤ（21）を打つ部分を部分的に突出させた形状
でも良い。具体的には0.8×0.8mmの大きさを有していれ
ば満足できる。The gold plating layer (20
a) is the size of the semiconductor chip (14) (0.3 x 0.3 mm to 0.6
× 0.6mm) and the positioning accuracy and wire (2
1) Reduce the size to allow enough room to hit. A shape in which a portion where the wire (21) is struck may be partially protruded may be used. Specifically, it is satisfactory if it has a size of 0.8 × 0.8 mm.
そして、セラミック基板（12）と半導体チップ（14）
を固着した放熱基板（11）はワイヤボンドされた後、放
熱基板（11）の裏面を露出するようにして樹脂（22）に
てモールドする。チップ部品（17）はセラミック基板
（12）上に固着された状態で提供され、そしてセラミッ
ク基板（12）と半導体チップ（14）とは別個に組立てを
行うので、半導体チップ（14）をチップ部品（17）固着
時の雰囲気から保護するボッティングやキャップ技術は
不要である。尚、リード（18）はリードフレームの状態
で供給され、放熱基板（11）は前記リードフレームにカ
シメにより一体化され供給される。And a ceramic substrate (12) and a semiconductor chip (14)
After the heat radiating substrate (11) to which is fixed is wire-bonded, it is molded with a resin (22) so that the back surface of the heat radiating substrate (11) is exposed. The chip component (17) is provided fixed on the ceramic substrate (12), and is assembled separately from the ceramic substrate (12) and the semiconductor chip (14). (17) No bottling or cap technology is required to protect against the atmosphere during fixation. The lead (18) is supplied in a state of a lead frame, and the heat radiation board (11) is integrated and supplied to the lead frame by caulking.
以上に説明した本発明の混成集積回路は、ヒートスプ
レッダ（13）の両面に形成した金メッキ層（20a）（20
b）のうち、半導体チップ（14）を固着する側の金メッ
キ層（20a）の面積を必要最小限にまで縮小したので、
表側の金メッキ層（20a）と裏側の金メッキ層（20b）と
の対向面積が減少し両者間の浮遊容量を低減できる。こ
の部分の容量は半導体チップ（14）の対GND間容量とし
て働くので、この容量を低減し回路的な高周波特性を改
善できる。The hybrid integrated circuit according to the present invention described above includes the gold plating layers (20a) (20) formed on both surfaces of the heat spreader (13).
In b), the area of the gold plating layer (20a) on the side where the semiconductor chip (14) is fixed is reduced to the minimum necessary.
The facing area between the gold plating layer (20a) on the front side and the gold plating layer (20b) on the back side is reduced, and the stray capacitance between them can be reduced. Since the capacitance of this portion functions as the capacitance between the semiconductor chip (14) and GND, this capacitance can be reduced and the high-frequency characteristics of the circuit can be improved.
また、面積を減少したことによって表面の金メッキ層
（20a）とワイヤ（21）や回路導体（16）間に発生する
浮遊容量をも低減できる。In addition, since the area is reduced, the stray capacitance generated between the gold plating layer (20a) on the surface and the wire (21) or the circuit conductor (16) can be reduced.
（ト）発明の効果 以上に説明した通り、本発明によれば半導体チップ
（14）を固着する側の金メッキ層（20a）の面積を減じ
ることによって、半導体チップ（14）の対GND間容量が
浮遊容量を低減できる利点を有する。そのため、高周波
特性を改善できる他、誘電率の高い樹脂モールドタイプ
でも優れた高周波特性を確保できる利点を有する。(G) Effects of the Invention As described above, according to the present invention, by reducing the area of the gold plating layer (20a) on the side to which the semiconductor chip (14) is fixed, the capacitance between the semiconductor chip (14) and GND is reduced. It has the advantage that stray capacitance can be reduced. Therefore, in addition to being able to improve high-frequency characteristics, there is an advantage that excellent high-frequency characteristics can be ensured even with a resin mold type having a high dielectric constant.
また、貴金属である金の使用量を減じることができる
ので、コストダウンにも寄与できる利点をも有する。In addition, since the amount of gold, which is a noble metal, can be reduced, there is an advantage that cost can be reduced.
第１図は本発明を説明するための斜視断面図、第２図は
本発明を説明するための平面図、第３図は本発明を説明
するための断面図、第４図は従来例を説明するための断
面図である。1 is a perspective cross-sectional view for explaining the present invention, FIG. 2 is a plan view for explaining the present invention, FIG. 3 is a cross-sectional view for explaining the present invention, and FIG. It is sectional drawing for demonstrating.
フロントページの続き (72)発明者 柳瀬 芳彦 大阪府守口市京阪本通２丁目18番地 三 洋電機株式会社内 (56)参考文献 特開 昭57−164541（ＪＰ，Ａ) 特開 昭64−44054（ＪＰ，Ａ) 特公 昭42−21969（ＪＰ，Ｂ１) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/52Continuation of the front page (72) Inventor Yoshihiko Yanase 2--18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-57-164541 (JP, A) JP-A-64-44054 (JP, A) JP 42-21969 (JP, B1) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/52
Claims (3)
セラミック基板と、該セラミック基板の表面に形成した
複数の回路導体と、該回路導体に電気接続される半導体
チップと、該半導体チップを載置しその表面と裏面に金
属メッキ層を設けた熱伝導性良好なるヒートスプレッダ
とを具備する混成集積回路において、 前記ヒートスプレッダの前記半導体チップを固着する側
の金属メッキ層を前記半導体チップを固着するに足りる
面積まで縮小したことを特徴とする混成集積回路。1. A ceramic substrate fixed on a heat radiating substrate having good thermal conductivity, a plurality of circuit conductors formed on the surface of the ceramic substrate, a semiconductor chip electrically connected to the circuit conductor, and the semiconductor chip And a heat spreader having good heat conductivity provided with a metal plating layer on the front and back surfaces of the heat spreader, wherein the metal plating layer on the side of the heat spreader to which the semiconductor chip is fixed is fixed to the semiconductor chip. A hybrid integrated circuit characterized in that the area has been reduced to a value sufficient to perform.
を特徴とする請求項第１項記載の混成集積回路。2. The hybrid integrated circuit according to claim 1, wherein said metal plating layer is a gold plating layer.
モールドしたことを特徴とする請求項第１項に記載の混
成集積回路。3. The hybrid integrated circuit according to claim 1, wherein a resin mold is formed so as to expose a back surface of said heat dissipation substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2262495A JP2834878B2 (en) | 1990-09-28 | 1990-09-28 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2262495A JP2834878B2 (en) | 1990-09-28 | 1990-09-28 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04137739A JPH04137739A (en) | 1992-05-12 |
| JP2834878B2 true JP2834878B2 (en) | 1998-12-14 |
Family
ID=17376593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2262495A Expired - Lifetime JP2834878B2 (en) | 1990-09-28 | 1990-09-28 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2834878B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3061102B2 (en) * | 1995-06-14 | 2000-07-10 | サンケン電気株式会社 | Circuit device |
| US6646521B1 (en) | 2000-09-15 | 2003-11-11 | Hei, Inc. | Connection for conducting high frequency signal between a circuit and a discrete electric component |
| TWI437930B (en) * | 2011-05-03 | 2014-05-11 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
-
1990
- 1990-09-28 JP JP2262495A patent/JP2834878B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04137739A (en) | 1992-05-12 |
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