JP2830152B2 - Phase difference control circuit - Google Patents
Phase difference control circuitInfo
- Publication number
- JP2830152B2 JP2830152B2 JP1230819A JP23081989A JP2830152B2 JP 2830152 B2 JP2830152 B2 JP 2830152B2 JP 1230819 A JP1230819 A JP 1230819A JP 23081989 A JP23081989 A JP 23081989A JP 2830152 B2 JP2830152 B2 JP 2830152B2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- phase difference
- data signal
- signal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は位相差制御回路に関し、特に２つの受信信号
の位相差を制御して同相合成する同相合成スペースダイ
バーシティ受信方式における無限移相器を制御する位相
差制御回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference control circuit, and more particularly to an infinite phase shifter in an in-phase combined space diversity receiving system for controlling the phase difference between two received signals to perform in-phase combining. The present invention relates to a phase difference control circuit for controlling.
第３図は従来の位相差制御回路の一例を示すブロック
図である。同図において、受信信号S1及びS2の内、受信
信号S2は無限移相器１によって位相を制御され合成器２
によって受信信号S1と同相合成されて合成信号S3として
復調器へ送出される。また、合成器２へ入力する信号は
それぞれ分岐されて位相差制御回路へ供給され、位相差
制御回路からの制御信号34によって無限移相器１は制御
される。FIG. 3 is a block diagram showing an example of a conventional phase difference control circuit. In the figure, of the received signals S1 and S2, the phase of the received signal S2 is controlled by the infinite phase shifter 1 and the
Thus, the received signal S1 is in-phase-combined with the received signal S1 and transmitted to the demodulator as a combined signal S3. The signals input to the synthesizer 2 are branched and supplied to a phase difference control circuit, and the infinite phase shifter 1 is controlled by a control signal 34 from the phase difference control circuit.
位相差制御回路は位相差検出器３及び制御信号生成部
４からなっている。位相差検出部３は、合成器２へ入力
する信号の分岐された各信号を受け、信号レベルを一定
にする自動利得制御増幅器５及び６をそれぞれ経由させ
た後、一方の信号のみπ/2移相器７によってπ/2だけ位
相推移させて位相比較器８に印加し、２つの信号の位相
差に応じた電圧を得ている。この場合、位相比較器８は
入力した２つの信号が同相のときは出力電圧は０を、ま
た、両信号の位相差の進みあるいは遅れに応じて正ある
いは負の電圧を生成し出力する。制御信号生成部４は、
位相比較器８からの出力電圧を受けて無限移相器１を制
御する制御信号34を生成する。まず、電圧比較器19及び
20は、あらかじめ設定されたしきい値に応じて位相比較
器８からの出力電圧を弁別し、進み検出信号あるいは遅
れ検出信号のいずれかを出力する。アップダウンカウン
タ（U/D）22は、電圧比較器19及び20からの進み検出信
号あるいは遅れ検出信号のいずれかを受け、クロック発
生器21からのクロック信号に応じて所定のステップでカ
ウントアップあるいはカウントダウンを行い、進み検出
信号あるいは遅れ検出信号が印加される時間に比例した
信号を生成しROM17へ出力する。ROM17は、アップダウン
カウンタ22からの信号に対応して無限移相器１を制御す
るあらかじめ設定された制御データを出力する。Ｄ−Ａ
変換器18はROM17からの制御データをアナログ信号に変
換し制御信号34を生成して無限移相器１へ送出する。無
限移相器１はＤ−Ａ変換器18から供給されるアナログ信
号に応じて受信信号S2の位相を制御している。The phase difference control circuit includes a phase difference detector 3 and a control signal generator 4. The phase difference detection unit 3 receives each of the branched signals of the signal input to the combiner 2 and passes the signals through automatic gain control amplifiers 5 and 6 for keeping the signal level constant. The phase is shifted by π / 2 by the phase shifter 7 and applied to the phase comparator 8 to obtain a voltage corresponding to the phase difference between the two signals. In this case, the phase comparator 8 generates and outputs an output voltage of 0 when the two input signals are in phase, and generates a positive or negative voltage according to the advance or delay of the phase difference between the two signals. The control signal generation unit 4
Upon receiving the output voltage from the phase comparator 8, it generates a control signal 34 for controlling the infinite phase shifter 1. First, the voltage comparator 19 and
Reference numeral 20 discriminates the output voltage from the phase comparator 8 according to a preset threshold value, and outputs either a lead detection signal or a delay detection signal. The up / down counter (U / D) 22 receives either the advance detection signal or the delay detection signal from the voltage comparators 19 and 20, and counts up or down at a predetermined step according to the clock signal from the clock generator 21. It counts down, generates a signal proportional to the time during which the advance detection signal or the delay detection signal is applied, and outputs the signal to the ROM 17. The ROM 17 outputs preset control data for controlling the infinite phase shifter 1 according to the signal from the up / down counter 22. DA
The converter 18 converts the control data from the ROM 17 into an analog signal, generates a control signal 34, and sends it to the infinite phase shifter 1. The infinite phase shifter 1 controls the phase of the received signal S2 according to the analog signal supplied from the DA converter 18.
上述した従来の位相差制御回路では、位相比較器８の
出力電圧を２つの電圧比較器19及び20によって弁別し、
進み検出信号あるいは遅れ検出信号を得て制御信号34を
生成している。しかし、無限移相器１による雑音発生及
び誤り率特性の劣化等を防止するために、位相比較器８
の出力電圧が０付近で電圧比較器19及び20が位相比較器
８の出力電圧を検知しない不感帯を設けている。このた
め、２つの受信信号S1及びS2が逆相のときに何らかのき
っかけで不感帯に入ると逆相状態のままで位相制御され
なくなるという欠点がある。また、進み検出信号あるい
は遅れ検出信号をクロック信号に応じて所定のステップ
でカウントアップあるいはカウントダウンを行って無限
移相器１の制御信号を生成しているので、受信信号S1及
びS2の位相差が大きいほど位相制御に要する時間が長く
かかるという欠点がある。In the conventional phase difference control circuit described above, the output voltage of the phase comparator 8 is discriminated by the two voltage comparators 19 and 20,
The control signal 34 is generated by obtaining the advance detection signal or the delay detection signal. However, in order to prevent generation of noise and deterioration of error rate characteristics due to the infinite phase shifter 1, the phase comparator 8
When the output voltage of the phase comparator 8 is near 0, a dead zone in which the voltage comparators 19 and 20 do not detect the output voltage of the phase comparator 8 is provided. Therefore, if the two received signals S1 and S2 enter the dead zone when they are out of phase with each other, there is a disadvantage that the phase is not controlled in the out-of-phase state. Further, since the advance detection signal or the delay detection signal is counted up or down at predetermined steps in accordance with the clock signal to generate the control signal of the infinite phase shifter 1, the phase difference between the received signals S1 and S2 is reduced. There is a disadvantage that the larger the value is, the longer the time required for the phase control is.
本発明の目的は、このような従来の欠点を除く位相差
制御回路を提供することにある。An object of the present invention is to provide a phase difference control circuit which eliminates such a conventional disadvantage.
本発明の位相差制御回路は、２つの受信信号を合成器
によって同相合成するための無限移相器を制御する位相
差制御回路において、前記合成器へ入力する前記２つの
受信信号の位相を比較し位相差に応じて電圧を出力する
第１の位相比較手段と、前記２つの受信信号の内一方の
信号の位相をπ/2移相させて他方の信号と位相を比較し
位相差に応じた電圧を出力する第２の位相比較手段と、
前記第１の位相比較器からの出力電圧の正負を判定して
切替信号を生成し出力する電圧比較手段と、前記第２の
位相比較器からの出力電圧を受け電圧値に対応する位相
差Δθを示すデータ信号に変換し出力する変換手段と、
前記変換手段からの位相差Δθを示すデータ信号を受け
π−Δθの演算を行って位相差π−Δθを示すデータ信
号を出力する演算手段と、前記電圧比較手段からの切替
信号に応じて前記変換手段からのデータ信号または前記
演算手段からのデータ信号のいずれかを切替えて出力す
る切替手段と、前記切替手段からのデータ信号を保持し
所定の周期で保持しているデータ信号値と前記切替手段
からのデータ信号値を加算してデータ信号値を更新する
位相情報保持手段とを有している。The phase difference control circuit of the present invention is a phase difference control circuit that controls an infinite phase shifter for synthesizing two received signals in phase by a combiner, and compares the phases of the two received signals input to the combiner. First phase comparing means for outputting a voltage according to the phase difference; and shifting the phase of one of the two received signals by π / 2 to compare the phase with the other signal, and according to the phase difference. Second phase comparing means for outputting the output voltage,
Voltage comparison means for determining whether the output voltage from the first phase comparator is positive or negative and generating and outputting a switching signal; and a phase difference Δθ corresponding to a voltage value, receiving the output voltage from the second phase comparator. Conversion means for converting and outputting a data signal indicating
A calculating means for receiving a data signal indicating the phase difference Δθ from the converting means and performing a calculation of π-Δθ to output a data signal indicating the phase difference π-Δθ; and A switching means for switching and outputting either the data signal from the conversion means or the data signal from the arithmetic means, and a data signal value holding the data signal from the switching means and holding the data signal at a predetermined cycle, and Phase information holding means for updating the data signal value by adding the data signal value from the means.
次に図面を参照して本発明を説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の位相差制御回路の一実施例を示すブ
ロック図である。同図において、第３図に示した従来の
位相差制御回路の一例を示すブロック図と同様に、受信
信号S1及びS2の内、受信信号S2は無限移相器１によって
位相を制御され合成器２によって受信信号S1と同相合成
されて合成信号S3として復調器へ送出される。また、合
成器２へ入力する信号はそれぞれ分岐されて位相差制御
回路へ供給され、位相差制御回路からの制御信号34によ
って無限移相器１は制御される。FIG. 1 is a block diagram showing one embodiment of the phase difference control circuit of the present invention. In the same drawing, as in the block diagram showing an example of the conventional phase difference control circuit shown in FIG. 3, of the received signals S1 and S2, the received signal S2 is controlled in phase by the infinite phase shifter 1, and 2 and is combined in phase with the received signal S1 and sent to the demodulator as a combined signal S3. The signals input to the synthesizer 2 are branched and supplied to a phase difference control circuit, and the infinite phase shifter 1 is controlled by a control signal 34 from the phase difference control circuit.
位相差制御回路は、位相差検出部３及び制御信号生成
部４からなっている。位相差検出部３は、合成器２へ入
力する信号の分岐された各信号を受け、信号レベルを一
定にする自動利得制御増幅器５及び６をそれぞれ経由さ
せた後、第２の位相比較器９で２つの入力信号の位相を
比較し、位相差に応じた出力電圧32を電圧比較器13へ送
出する。この場合、第２の位相比較器９は入力した２つ
の信号が同相のときは出力電圧は正の最大値となり、両
信号の位相差の進みあるいは遅れに応じて出力電圧は減
少する。電圧比較器13は、第２の位相比較器９からの出
力電圧32が正であるか負であるかを検知して切替信号33
を生成し切替器14へ出力する。また、自動利得制御増幅
器５及び６をそれぞれ経由した２つの信号の内、一方の
信号のみπ/2移相器７によってπ/2だけ位相推移させて
第１の位相比較器８に印加し、２つの信号の位相差に応
じた電圧を得ている。この場合、第１の位相比較器８は
入力した２つの信号が同相のときは出力電圧は０を、ま
た、両信号の位相差の進みあるいは遅れに応じて正ある
いは負の電圧を生成し出力電圧31をＡ−Ｄ変換器10へ出
力する。Ａ−Ｄ変換器10は、第１の位相比較器８からの
出力電圧31をディジタル信号に変換する。The phase difference control circuit includes a phase difference detection unit 3 and a control signal generation unit 4. The phase difference detection unit 3 receives the respective branched signals of the signal input to the combiner 2, passes through the automatic gain control amplifiers 5 and 6 for keeping the signal level constant, and then outputs the signals to the second phase comparator 9. Compares the phases of the two input signals, and sends an output voltage 32 corresponding to the phase difference to the voltage comparator 13. In this case, when the two input signals have the same phase, the output voltage of the second phase comparator 9 has a positive maximum value, and the output voltage decreases according to the advance or delay of the phase difference between the two signals. The voltage comparator 13 detects whether the output voltage 32 from the second phase comparator 9 is positive or negative, and switches the switching signal 33.
Is generated and output to the switch 14. Also, of the two signals respectively passing through the automatic gain control amplifiers 5 and 6, only one of the signals is shifted in phase by π / 2 by the π / 2 phase shifter 7 and is applied to the first phase comparator 8, A voltage corresponding to the phase difference between the two signals is obtained. In this case, the first phase comparator 8 generates an output voltage of 0 when the two input signals are in phase, and generates and outputs a positive or negative voltage according to the advance or delay of the phase difference between the two signals. The voltage 31 is output to the AD converter 10. The A / D converter 10 converts the output voltage 31 from the first phase comparator 8 into a digital signal.
第２図は第１の位相比較器８の出力電圧31,第２位相
比較器９の出力電圧32及び電圧比較器13の切替信号33を
示す説明図である。横軸は２つの信号の位相差を示し、
縦軸は出力電圧を示している。切替信号33は第２の位相
比較器９の出力電圧32の正負に応じて正負に変化し、位
相差が±π/2のところで反転する。第１の位相比較器８
の出力電圧31においては位相差Δθのときの出力電圧値
と位相差π−Δθのときの出力電圧値は同じであるが、
切替信号33によって識別できることがわかる。FIG. 2 is an explanatory diagram showing an output voltage 31 of the first phase comparator 8, an output voltage 32 of the second phase comparator 9, and a switching signal 33 of the voltage comparator 13. The horizontal axis shows the phase difference between the two signals,
The vertical axis indicates the output voltage. The switching signal 33 changes between positive and negative depending on whether the output voltage 32 of the second phase comparator 9 is positive or negative, and is inverted when the phase difference is ± π / 2. First phase comparator 8
Although the output voltage value at the time of the phase difference Δθ is the same as the output voltage value at the time of the phase difference π−Δθ in the output voltage 31 of
It can be seen that it can be identified by the switching signal 33.
さて、Ａ−Ｄ変換器10からのディジタル化された第１
の位相比較器８の出力電圧31はROM11に印加される。ROM
11は電圧値を位相差値に変換するあらかじめ書込まれた
データを有し、出力電圧31に対応する位相差に対応する
データ信号を切替器14及び位相差演算器12へ出力する。
位相差演算部12は、印加された位相差Δθを示すデータ
信号に対してπ−Δθを演算して切替器14へ出力する。
切替器14は、ROM11及び位相差演算器12からのデータ信
号を受け、電圧比較器13らの切替信号33が正のときはRO
M11からの位相差Δθを示すデータ信号を出力し、また
切替信号33が負のときは位相差演算器12からの位相差π
−Δθを示すデータ信号を切替えて出力する。このよう
にして、位相差Δθの位相差π−Δθとを識別する。Now, the first digitized signal from the AD converter 10 is output.
The output voltage 31 of the phase comparator 8 is applied to the ROM 11. ROM
Numeral 11 has data written in advance for converting a voltage value into a phase difference value, and outputs a data signal corresponding to a phase difference corresponding to the output voltage 31 to the switch 14 and the phase difference calculator 12.
The phase difference calculation unit 12 calculates π−Δθ for the data signal indicating the applied phase difference Δθ and outputs the result to the switch 14.
The switch 14 receives data signals from the ROM 11 and the phase difference calculator 12, and when the switch signal 33 from the voltage comparator 13 is positive, RO
A data signal indicating the phase difference Δθ from M11 is output, and when the switching signal 33 is negative, the phase difference π from the phase difference calculator 12 is output.
The data signal indicating -Δθ is switched and output. In this way, the phase difference Δθ is identified as the phase difference π−Δθ.
切替器14からのデータ信号は加算器15を介して位相保
持回路（FF）16に保持される。この保持される信号値と
切替器14からのデータ信号値とが加算器15によって所定
の周期で加算され、保持されるデータ信号値が更新され
る。このデータ信号値はROM17によって無限移相器１を
制御する制御データに変換され、更に、Ｄ−Ａ変換器18
によってアナログ信号に変換されて制御信号34として無
限移相器１へ送出される。The data signal from the switch 14 is held in the phase holding circuit (FF) 16 via the adder 15. The held signal value and the data signal value from the switch 14 are added at a predetermined cycle by the adder 15, and the held data signal value is updated. This data signal value is converted into control data for controlling the infinite phase shifter 1 by the ROM 17, and further converted to a DA converter 18.
Is converted into an analog signal and sent to the infinite phase shifter 1 as a control signal 34.
以上説明したように本発明の位相差制御回路によれ
ば、第２の位相比較器及び電圧比較器によって位相差が
±π/2のところで反転する切替信号を生成し、また、第
１の位相比較器からの出力電圧をROMに印加して位相差
Δθを示す信号に変換し、位相差演算器によってπ−Δ
θの値を算出し、切替信号に応じて位相差Δθを示す信
号あるいは位相差π−Δθを示す信号のいずれかを選択
し、更に、位相情報を更新し保持しながら無限移相器を
制御するので、受信信号S1及びS2が逆相となってもこれ
を識別して正確に制御できるばかりでなく、受信信号S1
及びS2の位相差に無関係に一定時間で制御できるという
効果がある。As described above, according to the phase difference control circuit of the present invention, the second phase comparator and the voltage comparator generate the switching signal in which the phase difference is inverted at ± π / 2, and The output voltage from the comparator is applied to the ROM, converted into a signal indicating a phase difference Δθ, and the phase difference calculator calculates π−Δ
Calculates the value of θ, selects either the signal indicating the phase difference Δθ or the signal indicating the phase difference π-Δθ according to the switching signal, and controls the infinite phase shifter while updating and holding the phase information Therefore, even if the reception signals S1 and S2 have opposite phases, not only can this be identified and accurately controlled, but also the reception signal S1
In addition, there is an effect that control can be performed in a fixed time regardless of the phase difference between S2 and S2.
第１図は本発明の位相差制御回路の一実施例を示すブロ
ック図、第２図は第１の位相比較器の出力電圧21,第２
の位相比較器の出力電圧22及び電圧比較器の切替信号23
を示す説明図、第３図は従来の位相差制御回路の一例を
示すブロック図である。 １……無限移相器、２……合成器、３……位相差検出
部、４……制御信号生成部、5,6……自動利得制御増幅
器、７……π/2移相器、８……第１の位相比較器、９…
…第２の位相比較器、10……Ａ−Ｄ変換器、11……RO
M、12……位相差演算器、13……電圧比較器、14……切
替器、15……加算器、16……位相保持回路（FF）、17…
…ROM、18……Ｄ−Ａ変換器、19,20……電圧比較器、21
……クロック発生器、22……アップダウンカウンタ、31
……第１の位相比較器の出力電圧、32……第２の位相比
較器の出力電圧、33……切替信号、34……制御信号、S
1,S2……受信信号、S3……合成信号。FIG. 1 is a block diagram showing an embodiment of a phase difference control circuit according to the present invention, and FIG. 2 is a block diagram showing an output voltage 21 of a first phase comparator and a second phase comparator.
Output voltage 22 of the phase comparator and the switching signal 23 of the voltage comparator
FIG. 3 is a block diagram showing an example of a conventional phase difference control circuit. 1 ... infinite phase shifter, 2 ... combiner, 3 ... phase difference detector, 4 ... control signal generator, 5,6 ... automatic gain control amplifier, 7 ... π / 2 phase shifter, 8... First phase comparator, 9.
... second phase comparator, 10 ... AD converter, 11 ... RO
M, 12: Phase difference calculator, 13: Voltage comparator, 14: Switcher, 15: Adder, 16: Phase holding circuit (FF), 17 ...
... ROM, 18 ... DA converter, 19, 20 ... voltage comparator, 21
…… Clock generator, 22 …… Up / down counter, 31
... Output voltage of the first phase comparator, 32... Output voltage of the second phase comparator, 33... Switching signal, 34.
1, S2: Received signal, S3: Synthesized signal.
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H04B 7/00 H04B 7/02 - 7/12 H04L 1/02 - 1/06 H03L 1/00 - 7/14 H03L 7/24 - 7/26Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H04B 7/00 H04B 7/02-7/12 H04L 1/02-1/06 H03L 1/00-7/14 H03L 7 / 24-7/26
Claims (1)
するための無限移相器を制御する位相差制御回路におい
て、前記合成器へ入力する前記２つの受信信号の位相を
比較し位相差に応じた電圧を出力する第１の位相比較手
段と、前記２つの受信信号の内一方の信号の位相をπ/2
移相させて他方の信号と位相を比較し位相差に応じた電
圧を出力する第２の位相比較手段と、前記第１の位相比
較器からの出力電圧の正負を判定して切替信号を生成し
出力する電圧比較手段と、前記第２の位相比較器からの
出力電圧を受け電圧値に対応する位相差Δθを示すデー
タ信号に変換し出力する変換手段と、前記変換手段から
の位相差Δθを示すデータ信号を受けπ−Δθの演算を
行って位相差π−Δθを示すデータ信号を出力する演算
手段と、前記電圧比較手段からの切替信号に応じて前記
変換手段からのデータ信号または前記演算手段からのデ
ータ信号のいずれかを切替えて出力する切替手段と、前
記切替手段からのデータ信号を保持し所定の周期で保持
しているデータ信号値と前記切替手段からのデータ信号
値を加算してデータ信号値を更新する位相情報保持手段
とを有することを特徴とする位相差制御回路。A phase difference control circuit for controlling an infinite phase shifter for synthesizing two received signals in phase by a combiner, comparing the phases of the two received signals input to the combiner to obtain a phase difference. First phase comparing means for outputting a corresponding voltage, and a phase of one of the two received signals being π / 2
Second phase comparing means for shifting the phase and comparing the phase with the other signal and outputting a voltage corresponding to the phase difference; and generating a switching signal by determining whether the output voltage from the first phase comparator is positive or negative. Voltage comparing means for converting and outputting the output voltage from the second phase comparator into a data signal indicating a phase difference Δθ corresponding to the voltage value, and a phase difference Δθ from the converting means. A data signal indicating the phase difference π−Δθ by performing a calculation of π−Δθ upon receiving a data signal indicating the data signal indicating the phase difference π−Δθ, or a data signal from the conversion means or the data signal Switching means for switching and outputting any of the data signals from the arithmetic means; holding the data signal from the switching means and adding the data signal value held at a predetermined cycle to the data signal value from the switching means; Data signal Phase difference control circuit; and a phase information holding means for updating the.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230819A JP2830152B2 (en) | 1989-09-05 | 1989-09-05 | Phase difference control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230819A JP2830152B2 (en) | 1989-09-05 | 1989-09-05 | Phase difference control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0393321A JPH0393321A (en) | 1991-04-18 |
| JP2830152B2 true JP2830152B2 (en) | 1998-12-02 |
Family
ID=16913777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1230819A Expired - Fee Related JP2830152B2 (en) | 1989-09-05 | 1989-09-05 | Phase difference control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2830152B2 (en) |
-
1989
- 1989-09-05 JP JP1230819A patent/JP2830152B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0393321A (en) | 1991-04-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |