JP2830092B2 - Electrostatic protection element for semiconductor device - Google Patents
Electrostatic protection element for semiconductor deviceInfo
- Publication number
- JP2830092B2 JP2830092B2 JP17457289A JP17457289A JP2830092B2 JP 2830092 B2 JP2830092 B2 JP 2830092B2 JP 17457289 A JP17457289 A JP 17457289A JP 17457289 A JP17457289 A JP 17457289A JP 2830092 B2 JP2830092 B2 JP 2830092B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- type
- semiconductor device
- region
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Semiconductor Integrated Circuits (AREA)
- Elimination Of Static Electricity (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の静電保護素子に関する。The present invention relates to an electrostatic protection element for a semiconductor device.
従来の半導体装置の静電保護素子は、第２図に示すよ
うに、入出力信号配線11と高電位電源配線12との間およ
び入出力信号配線11と低電位電源配線13との間にダイオ
ードを設けているが、ダイオード間の配置については特
に考慮されておらず、ダイオードの一方の電極となるＮ
型第１埋込層３およびＮ型第２埋込層４とＰ型反転防止
領域２との最小間隔は一般に等しくなっていた。As shown in FIG. 2, the electrostatic protection element of the conventional semiconductor device has a diode between the input / output signal wiring 11 and the high-potential power supply wiring 12 and between the input / output signal wiring 11 and the low-potential power supply wiring 13. However, no consideration is given to the arrangement between the diodes, and N
The minimum distance between the first type buried layer 3 and the second N type buried layer 4 and the P-type inversion prevention region 2 was generally equal.
周知のように、半導体装置の静電保護素子は、外部か
ら静電気が印加された場合に、半導体装置内の素子が応
答して破壊或いは回路動作上問題となる劣化を生じるに
至る前に静電気をバイパスし、放電させることを主目的
としたものである。上述した従来の半導体装置の静電保
護素子は以下の方法で内部素子にかかる電圧を抑制して
いる。As is well known, when a static electricity is applied from the outside, the static electricity protection element of the semiconductor device discharges the static electricity before the element in the semiconductor device responds to cause destruction or deterioration which causes a problem in circuit operation. The main purpose is to bypass and discharge. The above-mentioned conventional electrostatic protection element of the semiconductor device suppresses the voltage applied to the internal element by the following method.
（１）ダイオードの寄生抵抗を低減させる。(1) Reduce the parasitic resistance of the diode.
（２）ダイオードのpn接合を高濃度接合とする。(2) Make the pn junction of the diode a high-concentration junction.
（１）の方法は、主としてダイオードに順方向電圧が印
加された際にダイオードには瞬間的に数百mAの電流が流
れるため、寄生抵抗によりダイオード端子間電圧が高く
なるのを抑えるものである。In the method (1), when a forward voltage is applied to the diode, a current of several hundred mA flows through the diode instantaneously, so that the diode terminal voltage is prevented from increasing due to parasitic resistance. .
（２）の方法は、主としてダイオードに逆電圧が印加
された際に、ダイオードの逆耐圧を低減させるものであ
る。The method (2) mainly reduces the reverse breakdown voltage of the diode when a reverse voltage is applied to the diode.
しかしながら、逆電圧に対し、十分な静電耐圧を得る
方法として従来の（２）の方法は、ダイオードの寄生容
量を増加させるため、入出力端子の負荷を増大させ、そ
の結果、入出力特性を劣化させるという欠点がある。However, as a method of obtaining a sufficient electrostatic withstand voltage against a reverse voltage, the conventional method (2) increases the load on the input / output terminals in order to increase the parasitic capacitance of the diode. As a result, the input / output characteristics are reduced. There is a disadvantage of causing deterioration.
本発明の半導体装置の静電保護素子は、一導電型半導
体基板の一主面に形成され、それぞれ周囲を一導電型反
転防止領域に囲われた二つの逆導電型埋込層を一方の電
極とする第１および第２のダイオードを入出力信号配線
と高電位電源配線間にそれぞれ有しており、前記第１の
ダイオードと第２のダイオードとでそれぞれの逆導電型
埋込層と一導電型反転防止領域との最小間隔を異なるよ
うにしてある。The electrostatic protection element of the semiconductor device according to the present invention is formed on one main surface of a semiconductor substrate of one conductivity type, and has two opposite conductivity type buried layers surrounded by one conductivity type inversion prevention region, each having one electrode. And a second diode between the input / output signal wiring and the high-potential power supply wiring. The first diode and the second diode each have a reverse conductivity type buried layer and one conductive layer. The minimum distance from the mold reversal prevention area is different.
第１図は本発明の一実施例の断面図である。 FIG. 1 is a sectional view of one embodiment of the present invention.
半導体装置の静電保護素子を構成する第１および第２
のダイオードは、それぞれＰ型シリコン基板１内に形成
され、周囲をＰ型反転防止領域２に囲まれたＮ型第１埋
込層３およびＮ型第２の埋込層４と、これらの埋込層3,
4に接する1015〜1016/cm3の濃度のＮ型第１領域と6a,6b
と、1019/cm3以上の濃度のＮ型第２領域8a,8bと、それ
ぞれＮ型第１領域内6a,6bに形成されたＰ型第２領域9a,
9bとからなり、各ダイオード及びシリコン基板１に接続
するＰ型第１領域７は絶縁領域５に囲われ、表面を覆う
絶縁膜10に設けられた開口を介して第１のダイオードの
Ｎ型第２領域8aは高電位電源配線12に接続され、第１の
ダイオードのＰ型第２領域9aと第２のダイオードのＮ型
第２領域8bは入出力信号配線11に接続され、第２のダイ
オードのＰ型第２領域9bとＰ型第１の領域７は低電位電
源配線13に接続される。First and second parts constituting an electrostatic protection element of a semiconductor device
Are formed in a P-type silicon substrate 1 and surrounded by a P-type inversion prevention region 2. The N-type first buried layer 3 and the N-type second buried layer 4, Three layers,
N type first region having a concentration of 10 15 to 10 16 / cm 3 contacting 4 and 6a, 6b
And N-type second regions 8a and 8b having a concentration of 10 19 / cm 3 or more, and P-type second regions 9a and 8b formed in N-type first regions 6a and 6b, respectively.
9b, the P-type first region 7 connected to each diode and the silicon substrate 1 is surrounded by the insulating region 5, and the N-type first region of the first diode is formed through an opening provided in the insulating film 10 covering the surface. The second region 8a is connected to the high-potential power supply line 12, the P-type second region 9a of the first diode and the N-type second region 8b of the second diode are connected to the input / output signal line 11, and the second diode The P-type second region 9b and the P-type first region 7 are connected to a low-potential power supply wiring 13.
本実施例では第１のダイオード周囲のＰ型反転防止領
域２とＮ型第１埋込層３との最小間隔を小さくし、両領
域間の接合の逆耐圧を第２のダイオードの逆耐圧より小
さくする。そうすると、高電位電源配線12側から入出力
信号配線11側へ放電が起きた場合、Ｎ型第１領域6aから
Ｐ型第２領域9aを経由して電流が流れるより低い電圧で
Ｎ型第１埋込層３からＰ型シリコン基板１、Ｎ型第２埋
込層４を経由して電流が流れる。このため、高電位電源
配線12と入出力信号配線11との間の電圧を従来より低く
抑えることができ、内部素子の破壊或いは劣化を抑えら
れる。この結果、入出力端子の寄生容量の増加を伴わ
ず、すなわち従来の入出力信号の応答速度を維持したま
ま静電気耐性を強めた半導体装置とすることができる。In this embodiment, the minimum distance between the P-type inversion prevention region 2 around the first diode and the N-type first buried layer 3 is reduced, and the reverse withstand voltage of the junction between both regions is made smaller than the reverse withstand voltage of the second diode. Make it smaller. Then, when a discharge occurs from the high-potential power supply wiring 12 side to the input / output signal wiring 11 side, the N-type first region is at a lower voltage at which a current flows from the N-type first region 6a through the P-type second region 9a. A current flows from the buried layer 3 via the P-type silicon substrate 1 and the N-type second buried layer 4. For this reason, the voltage between the high-potential power supply wiring 12 and the input / output signal wiring 11 can be suppressed lower than before, and destruction or deterioration of the internal element can be suppressed. As a result, it is possible to provide a semiconductor device with an increased resistance to static electricity without increasing the parasitic capacitance of the input / output terminals, that is, while maintaining the conventional response speed of the input / output signals.
上記実施例では、Ｐ型反転防止領域２がＮ型第１埋込
層３と離れているが、これは接触していても良い。In the above embodiment, the P-type inversion prevention region 2 is separated from the N-type first buried layer 3, but this may be in contact.
また、入出力配線11と低電位電源配線13との間に二つ
の接合が接続されているが、どちらか一方は接続しない
ようにすることもできる。Further, two junctions are connected between the input / output wiring 11 and the low-potential power supply wiring 13, but one of them may not be connected.
以上説明したように本発明は、入出力端子の負荷容量
を増大させることなく十分な静電耐圧を持たせられるた
め、半導体装置の高速性と高信頼性を両立できるという
効果がある。As described above, according to the present invention, a sufficient electrostatic withstand voltage can be provided without increasing the load capacitance of the input / output terminals, so that there is an effect that both high speed and high reliability of the semiconductor device can be achieved.
第１図は本発明の一実施例の断面図、第２図は従来の半
導体装置の静電保護素子の一例の断面図である。 １……Ｐ型シリコン基板、２……Ｐ型反転防止領域、３
……Ｎ型第１埋込層、４……Ｎ型第２埋込層、５……絶
縁領域、6a,6b……Ｎ型第１領域、７……Ｐ型第１領
域、8a,8b……Ｎ型第２領域、9a,9b……Ｐ型第２領域、
10……絶縁膜、11……入出力信号配線、12……高電位電
源配線、13……低電位電源配線。FIG. 1 is a cross-sectional view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view of one example of a conventional electrostatic protection element of a semiconductor device. 1 ... P-type silicon substrate, 2 ... P-type inversion prevention region, 3
... N-type first buried layer, 4 ... N-type second buried layer, 5 ... insulating region, 6a, 6b ... N-type first region, 7 ... P-type first region, 8a, 8b ... N-type second region, 9a, 9b ... P-type second region,
10: insulating film, 11: input / output signal wiring, 12: high-potential power wiring, 13: low-potential power wiring.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 27/04 H01L 21/822 H01L 29/90 H05F 3/02──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 27/04 H01L 21/822 H01L 29/90 H05F 3/02
Claims (1)
それぞれ周囲を一導電型反転防止領域に囲われた二つの
逆導電型埋込層を一方の電極とする第１および第２のダ
イオードを、入出力信号配線と高電位電源配線間および
低電位電源配線間にそれぞれ設けてなる半導体装置の静
電保護素子において、前記逆導電型埋込層と前記一導電
型反転防止領域との最小間隔が前記第１のダイオードと
第２のダイオードで異なることを特徴とする半導体装置
の静電保護素子。A first conductivity type semiconductor substrate formed on one main surface;
A first diode and a second diode each having one electrode of two opposite conductivity type buried layers surrounded by one conductivity type inversion prevention region are provided between an input / output signal wiring and a high potential power supply wiring and a low potential power supply. In an electrostatic protection element of a semiconductor device provided between wirings, a minimum distance between the reverse conductivity type buried layer and the one conductivity type inversion prevention region is different between the first diode and the second diode. An electrostatic protection element for a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17457289A JP2830092B2 (en) | 1989-07-05 | 1989-07-05 | Electrostatic protection element for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17457289A JP2830092B2 (en) | 1989-07-05 | 1989-07-05 | Electrostatic protection element for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0338870A JPH0338870A (en) | 1991-02-19 |
| JP2830092B2 true JP2830092B2 (en) | 1998-12-02 |
Family
ID=15980907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17457289A Expired - Lifetime JP2830092B2 (en) | 1989-07-05 | 1989-07-05 | Electrostatic protection element for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2830092B2 (en) |
-
1989
- 1989-07-05 JP JP17457289A patent/JP2830092B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0338870A (en) | 1991-02-19 |
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