JP2799037B2 - Analog standard cell - Google Patents
Analog standard cellInfo
- Publication number
- JP2799037B2 JP2799037B2 JP2089141A JP8914190A JP2799037B2 JP 2799037 B2 JP2799037 B2 JP 2799037B2 JP 2089141 A JP2089141 A JP 2089141A JP 8914190 A JP8914190 A JP 8914190A JP 2799037 B2 JP2799037 B2 JP 2799037B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- cells
- level
- cell
- standard cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、アナログ信号を扱うアナログスタンダード
セルに関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an analog standard cell that handles analog signals.
（従来の技術） 従来、アナログ回路をブロック的に区分けして集積回
路化しようとする場合、各ブロック間の使用電源電圧
（Vcc）、直流バイアス電圧、扱われる信号レベルはま
ちまちであり、各ブロックを別々の設計者が設計し、各
ブロックを合成することにより、上記アナログ回路を得
ている。(Prior art) Conventionally, when an analog circuit is divided into blocks to form an integrated circuit, a power supply voltage (Vcc), a DC bias voltage, and a signal level to be used between the blocks are different. Are designed by different designers, and the blocks are combined to obtain the analog circuit.
（発明が解決しようとする課題） この場合、各ブロックを合成すると云っても、各電圧
レベルの統一がとれていないし、各ブロックを異なる設
計者が担当するため、簡単にブロックを合成し、良好な
回路システムを得ることが難しくなることは当然である
し、回路設計者は、新たな回路を得ようとする毎に、そ
の回路に合う設計を行なうことが必要とされる。(Problems to be Solved by the Invention) In this case, even though the blocks are combined, the voltage levels are not unified, and each designer is assigned to a different designer. Obviously, it is difficult to obtain a simple circuit system, and every time a circuit designer tries to obtain a new circuit, it is necessary to perform a design suitable for that circuit.
本発明は上記実情に鑑みてなされたもので、簡単な設
計を行なうだけで良好なアナログ回路が得られるように
することが目的である。The present invention has been made in view of the above circumstances, and it is an object of the present invention to obtain a good analog circuit only by performing a simple design.
［発明の構成］ （課題を解決するための手段と作用） 本発明は、 （１）集積回路チップ内を複数のセルに区分し、該セル
は、少くとも入力部及びまたは出力部において電源電
圧、直流バイアスレベル、信号レベルがセル間で共通の
レベルに固定されていることを特徴とするアナログスタ
ンダードセルである。また本発明は、 （２）前記各セルのうちの単セルは、機能回路と、隣接
セルに対するレベル合わせ用のインターフェース回路と
を具備したことを特徴とする前記（１）に記載のアナロ
グスタンダードセルである。[Structure of the Invention] (Means and Actions for Solving the Problems) The present invention is directed to (1) dividing an integrated circuit chip into a plurality of cells, and the cells are connected to a power supply voltage at least in an input section and / or an output section. , A DC bias level and a signal level are fixed to a common level among cells. Further, according to the present invention, (2) the analog standard cell according to (1), wherein the single cell of each of the cells includes a functional circuit and an interface circuit for level adjustment with respect to an adjacent cell. It is.
即ち本発明は、各セルが同じ電源電圧、同じ信号レベ
ルにて処理され、また同じ直流バイアス電圧で入出力が
構成されるため、設計者は、一度セルの回路を設計し
て、機能回路とインターフェースの回路図とパターン図
を計算機に登録しておけば、容易に所要セルを取り出
し、かつセル間を接続することができ、容易に所期のア
ナログ回路を構成できるようになる。That is, in the present invention, since each cell is processed at the same power supply voltage and the same signal level, and the input and output are configured with the same DC bias voltage, the designer once designs the circuit of the cell, and If the circuit diagram and pattern diagram of the interface are registered in the computer, the required cells can be easily taken out and the cells can be connected, and the desired analog circuit can be easily configured.
（実施例） 以下図面を参照して本発明の一実施例を説明する。第
１図は同実施例を示し、本発明を受信機システムに適用
した場合の例である。１はアンテナ、２はアンプであ
る。このアンプ２は、アンプとしての機能回路21とイン
ターフェース回路22を有する。３はミキサ、４は局部発
振器である。ミキサ３は、該ミキサとしての機能回路31
と、アンプ２のインターフェース回路22からの周波数f1
の信号を受けるインターフェース回路32と、発振器４か
らの周波数f2の信号を受けるインターフェース回路3
3と、周波数「f1−f2」の出力信号を送出するインター
フェース回路34を有する。発振器４は、該発振器として
の機能回路41と、周波数f2の出力信号を送出するインタ
ーフェース回路42を有する。５はバッファであり、これ
は該バッファとしての機能回路51と、ミキサ３からの信
号を受けるインターフェース回路52と、バッファ出力SO
を送出するインターフェース回路53を有する。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the embodiment and shows an example in which the present invention is applied to a receiver system. 1 is an antenna and 2 is an amplifier. The amplifier 2 has a function circuit 2 1 and the interface circuit 2 2 as an amplifier. 3 is a mixer and 4 is a local oscillator. The mixer 3, functional circuit 3 1 as the mixer
When the frequency f 1 from the interface circuit 2 2 of the amplifier 2
An interface circuit 3 2 for receiving a signal, the interface circuit 3 for receiving a signal of a frequency f 2 from an oscillator 4
3, an interface circuit 3 4 for transmitting the output signal of the frequency "f 1 -f 2". Oscillator 4 has a function circuit 4 1 as the generator, an interface circuit 4 2 for transmitting the output signal of the frequency f 2. 5 is a buffer, which is a functional circuit 5 1 as the buffer, an interface circuit 5 2 for receiving a signal from the mixer 3, the buffer output S O
An interface circuit 3 for delivering.
第２図は、第１図の各機能回路のうちのいずれかの機
能回路111と、その出力側のインターフェース回路112の
詳細回路例である。このインターフェース回路112は、
共通電源Vccをトランジスタ21のコレクタに接続し、ト
ランジスタ21のベースを機能回路111の出力部に接続
し、エミッタを、ダイオード22,23、定電流24を介して
接地に接続し、ダイオード23と定電流源24間から出力Ou
tを得るようにしている。FIG. 2 is a detailed circuit example of any one of the functional circuits 111 of FIG. 1 and an interface circuit 112 on the output side thereof. The interface circuit 11 2,
Connect the common power supply Vcc to the collector of the transistor 21, to connect the base of transistor 21 to the output of the functional circuit 11 1, the emitter, the diode 22 and 23, connected to ground through a constant current 24, a diode 23 Output Ou from between constant current sources 24
I'm trying to get t.
第３図は複数のセル31を有したICチップ30を示す。こ
の場合１つのセル31が、第１図または第２図のセル２〜
5,11のうちのいずれかと考えればよく、これらセル31が
寄せ集まって第１図の回路が、チップ30に形成されてい
ると考えればよい。FIG. 3 shows an IC chip 30 having a plurality of cells 31. In this case, one cell 31 corresponds to cells 2 to 2 in FIG. 1 or FIG.
It can be considered that these cells 31 are gathered and the circuit of FIG. 1 is formed on the chip 30.
以上の構成において、各セル（それぞれ機能回路とイ
ンターフェース回路よりなる）の共通電源Vccは例えば5
Vに、入出力直流バイアスは例えば2.5Vに、入出力信号
（セル2,3間,3,4間,3,5間，セル５の出力等）レベルの
ピーク・ツー・−ピークは例えば0.5Vにというように、
それぞれ規定のレベルに固定されている。ただセル２で
は、ICとアンテナ１の如き外部回路とのインターフェー
スは、信号レベル、直流電圧共に、IC内でのインターフ
ェースとは異なると考えられるため、別設計が必要であ
ろう。In the above configuration, the common power supply Vcc of each cell (each comprising a functional circuit and an interface circuit) is, for example, 5
V, the input / output DC bias is, for example, 2.5 V, and the peak-to-peak level of the input / output signal (between cells 2, 3, 3, 4, 3, 5, and the output of cell 5, etc.) is 0.5, for example. Like V
Each is fixed to a prescribed level. However, in the cell 2, the interface between the IC and an external circuit such as the antenna 1 is considered to be different from the interface in the IC in terms of both the signal level and the DC voltage, so that another design will be required.
また第２図において、インターフェース回路112の直
流バイアスを規定のレベルに調整するには、ダイオード
22,23（これを抵抗等としても可）の個所で行なえばよ
い。つまりダイオードの順方向Vfは略0.7Vであるから、
その数を増減すればよい。この際定電流源24はインピー
ダンス値が大だから、交流信号に対しては影響を与えな
い。In FIG. 2 , a diode bias is used to adjust the DC bias of the interface circuit 112 to a specified level.
What is necessary is just to carry out at 22,23 (this is also possible as a resistor etc.). That is, the forward direction Vf of the diode is approximately 0.7 V,
The number may be increased or decreased. At this time, since the constant current source 24 has a large impedance value, it does not affect the AC signal.
上記のような実施例の構成であれば、各セル２〜5,11
は、共通の電源（Vcc＝5V），共通の信号レベル（ピー
ク・ツー・−ピークが0.5V）、にて処理され、また共通
の直流バイアス（＝2.5V）で入出力が構成されるため、
設計者は単にシステム構成の接続関係のみを考慮して回
路設計を行なうことができる。With the configuration of the above embodiment, each of the cells 2 to 5, 11
Is processed with a common power supply (Vcc = 5V) and a common signal level (0.5V peak-to-peak), and the input and output are configured with a common DC bias (= 2.5V) ,
The designer can design the circuit simply by considering only the connection relation of the system configuration.
［発明の効果］ 以上説明した如く本発明によれば、回路設計者は、個
々のセルの回路を逐一設計する必要がなく、全体的なシ
ステム設計のみを構成すればよいため、回路設計着手か
らIC量産までの期間を大幅に短縮することができる。[Effects of the Invention] As described above, according to the present invention, a circuit designer does not need to design circuits of individual cells one by one, and only has to configure the entire system design. The time to mass production of ICs can be greatly reduced.
第１図は本発明の一実施例の構成図、第２図は同構成の
一部詳細回路図、第３図は同構成が形成されるICチップ
の平面図である。 １……アンテナ、２〜5,11,31……セル、21〜51,111…
…機能回路、22〜52,33,53,112……インターフェース、
30……ICチップ。FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a partially detailed circuit diagram of the configuration, and FIG. 3 is a plan view of an IC chip on which the configuration is formed. 1 ...... antenna, 2～5,11,31 ...... cell, 2 1-5 1, 11 1 ...
... functional circuit 2 2-5 2, 3 3, 5 3, 11 2 ...... interface,
30 …… IC chip.
Claims (2)
該セルは、少くとも入力部及びまたは出力部において電
源電圧、直流バイアスレベル、入出力信号レベルのピー
ク・ツー・ピークがセル間で共通のレベルに固定されて
いることを特徴とするアナログスタンダードセル。An integrated circuit chip is divided into a plurality of cells,
An analog standard cell, characterized in that a peak-to-peak power supply voltage, a DC bias level, and an input / output signal level are fixed at a common level among cells at least in an input section and / or an output section. .
と、隣接セルに対するレベル合わせ用のインターフェー
ス回路とを具備したことを特徴とする請求項１に記載の
アナログスタンダードセル。2. The analog standard cell according to claim 1, wherein a single cell among said cells includes a functional circuit and an interface circuit for adjusting a level with respect to an adjacent cell.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2089141A JP2799037B2 (en) | 1990-04-05 | 1990-04-05 | Analog standard cell |
| KR1019910005429A KR930008011B1 (en) | 1990-04-05 | 1991-04-04 | Analog standard cell |
| US07/921,360 US5302864A (en) | 1990-04-05 | 1992-07-27 | Analog standard cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2089141A JP2799037B2 (en) | 1990-04-05 | 1990-04-05 | Analog standard cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03288461A JPH03288461A (en) | 1991-12-18 |
| JP2799037B2 true JP2799037B2 (en) | 1998-09-17 |
Family
ID=13962596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2089141A Expired - Fee Related JP2799037B2 (en) | 1990-04-05 | 1990-04-05 | Analog standard cell |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2799037B2 (en) |
| KR (1) | KR930008011B1 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61245610A (en) * | 1985-04-24 | 1986-10-31 | Hitachi Ltd | Analog semiconductor integrated circuit device |
-
1990
- 1990-04-05 JP JP2089141A patent/JP2799037B2/en not_active Expired - Fee Related
-
1991
- 1991-04-04 KR KR1019910005429A patent/KR930008011B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03288461A (en) | 1991-12-18 |
| KR910019206A (en) | 1991-11-30 |
| KR930008011B1 (en) | 1993-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |