JP2797958B2 - Optical semiconductor device bonding structure and bonding method - Google Patents

Optical semiconductor device bonding structure and bonding method

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Publication number
JP2797958B2
JP2797958B2 JP3617194A JP3617194A JP2797958B2 JP 2797958 B2 JP2797958 B2 JP 2797958B2 JP 3617194 A JP3617194 A JP 3617194A JP 3617194 A JP3617194 A JP 3617194A JP 2797958 B2 JP2797958 B2 JP 2797958B2
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Japan
Prior art keywords
layer
optical semiconductor
semiconductor element
bonding
optical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP3617194A
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Japanese (ja)
Other versions
JPH0794786A (en
Inventor
和彦 蔵田
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NEC Corp
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NEC Corp
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は光半導体素子接合構造に
関し、特に光回路基板上に光半導体素子を接合固定する
接合構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device bonding structure, and more particularly to a bonding structure for bonding and fixing an optical semiconductor device on an optical circuit board.

【０００２】[0002]

【従来の技術】従来、光回路基板上への光半導体素子の
接合には、ＡｕＳｎ共晶半田から用いられている。つま
り、ＡｕＳｎ共晶半田の箔片を光回路基板上の接合部に
供給し、その半田材の加熱溶融と同時に光半導体素子を
光回路基板上に搭載して加圧することで、光半導体素子
を光回路基板上に接合している。2. Description of the Related Art Conventionally, AuSn eutectic solder is used for joining an optical semiconductor element onto an optical circuit board. In other words, a foil piece of AuSn eutectic solder is supplied to the joint portion on the optical circuit board, and the optical semiconductor element is mounted on the optical circuit board and pressed simultaneously with the heating and melting of the solder material, whereby the optical semiconductor element is mounted. It is bonded on the optical circuit board.

【０００３】しかしながら、ＡｕＳｎ共晶半田は酸化し
やすいため、窒素雰囲気または窒素に若干の水素を混合
させた還元雰囲気気中で接合させなければならない。ま
たこの場合、光半導体素子の光回路基板上への加圧時
に、ＡｕＳｎ共晶半田上に生成された酸化膜を予め取り
除くため、光半導体素子を加圧振動させるスクラブと呼
ばれる作業が必要となる。However, since AuSn eutectic solder is easily oxidized, it must be joined in a nitrogen atmosphere or a reducing atmosphere in which some hydrogen is mixed with nitrogen. Further, in this case, when the optical semiconductor element is pressed onto the optical circuit board, an operation called scrub for pressurizing and vibrating the optical semiconductor element is required to remove an oxide film formed on the AuSn eutectic solder in advance. .

【０００４】また、他の接合方法としては、光回路基板
の電極あるいは光半導体素子の接合面上にＳｎを蒸着し
ておき、光回路基板及び光半導体素子を加熱、加圧して
接合する方法がある。この方法でも、Ｓｎが酸化しやす
いため、非酸化雰囲気と光半導体素子のスクラブとが要
求される。As another bonding method, there is a method in which Sn is vapor-deposited on an electrode of an optical circuit board or a bonding surface of an optical semiconductor element, and the optical circuit substrate and the optical semiconductor element are bonded by heating and pressing. is there. Also in this method, since Sn is easily oxidized, a non-oxidizing atmosphere and a scrub of the optical semiconductor element are required.

【０００５】さらに、上記以外の方法として、光回路基
板上の接合部にＡｕＳｎ共晶半田の層を形成し、この層
の上に薄くＡｕ層を蒸着して形成しておき、このＡｕ層
に光半導体素子を搭載して接着溶融する方法がある。こ
の方法については、特開平１−１３８７７７号公報に詳
述されている。[0005] Further, as a method other than the above, a layer of AuSn eutectic solder is formed at the joint on the optical circuit board, and a thin Au layer is formed by vapor deposition on this layer. There is a method of mounting and melting an optical semiconductor element. This method is described in detail in JP-A-1-138777.

【発明が解決しようとする課題】従来より、光ファイバ
等への光結合を光軸調整を行わないで組立てる構造が数
多く提案されているが、その実現のためには光半導体素
子を光回路基板上の所定の位置に高精度に接合する必要
がある。A number of structures have been proposed for assembling optical coupling to an optical fiber or the like without adjusting the optical axis, but in order to realize this, an optical semiconductor element is mounted on an optical circuit board. It is necessary to join with high accuracy to a predetermined position above.

【０００６】従来の光半導体素子接合方法を用いて、光
半導体素子をサブミクロンのオーダで高精度に位置決め
して実装することを試みた場合、接合時にスクラブによ
り光半導体素子を振動させるため、接合位置に変動を生
じてしまう。When attempting to position and mount an optical semiconductor element with high precision on the order of submicron using a conventional optical semiconductor element bonding method, the optical semiconductor element is vibrated by scrubbing during bonding. The position will fluctuate.

【０００７】また、一般にＡｕＳｎ共晶半田の箔片の厚
さは薄くても２０〜３０μｍ程度ある。したがって、Ａ
ｕＳｎ共晶半田を溶融させて光半導体素子を接触させた
時、光半導体の電極面が濡れると同時に、ＡｕＳｎ共晶
半田の表面張力によって光半導体素子の接合位置がラン
ダムに動いてしまう。ここで、光半導体素子の電極面が
濡れるとは、溶融したＡｕＳｎ共晶半田が電極面上に薄
く延びることである。In general, the thickness of a foil piece of AuSn eutectic solder is about 20 to 30 μm at least. Therefore, A
When the optical semiconductor element is brought into contact with the uSn eutectic solder by melting the electrode surface of the optical semiconductor, the bonding position of the optical semiconductor element moves randomly due to the surface tension of the AuSn eutectic solder. Here, the term “wet the electrode surface of the optical semiconductor element” means that the molten AuSn eutectic solder extends thinly on the electrode surface.

【０００８】さらに、溶融したＡｕＳｎ共晶半田は加圧
時に光半導体素子が１０〜２０μｍ沈み込むため、光半
導体素子の高さ方向の精度を正確に制御することは困難
である。上述した現象の如く、従来の接合方法ではサブ
ミクロンのオーダでの光半導体素子の位置決め固定が困
難である。Further, since the optical semiconductor element sinks by 10 to 20 μm when the molten AuSn eutectic solder is pressed, it is difficult to accurately control the precision of the optical semiconductor element in the height direction. As described above, it is difficult for the conventional bonding method to position and fix the optical semiconductor element on the order of submicrons.

【０００９】Ｓｎを蒸着した場合にも表面が酸化膜が生
ずるため、上記の処理と同様にスクラブが必要であり、
サブミクロンのオーダでの光半導体素子の位置決め固定
は不可能である。[0009] Even when Sn is deposited, an oxide film is formed on the surface. Therefore, scrubbing is required in the same manner as in the above processing.
It is impossible to position and fix the optical semiconductor device on the order of submicrons.

【００１０】また、光半導体素子の接合時にＳｎ及びＡ
ｕ相互の拡散のみで完全なＡｕＳｎ共晶を生成すること
は困難である。この場合、Ｓｎの重量比が多くなり、脆
い金属化合物が生成されやすいため、接合後の信頼性を
保証することが困難であり、保管条件や接合温度、及び
加熱時間などを厳しく設定することが必要である。In addition, when joining the optical semiconductor element, Sn and A
It is difficult to generate a perfect AuSn eutectic only by diffusion between u. In this case, since the weight ratio of Sn increases and a brittle metal compound is easily generated, it is difficult to guarantee the reliability after joining, and the storage conditions, the joining temperature, the heating time, and the like must be strictly set. is necessary.

【００１１】さらに、光回路基板上に形成されたＡｕＳ
ｎ共晶半田層の上に薄くＡｕ層を蒸着する場合にも、共
晶条件を保つために蒸着するＡｕ層を薄くすれば、この
Ａｕ層のＡｕ及びＡｕＳｎ共晶半田層のＳｎ相互の拡散
によって表面に酸化膜が生ずるので、上記の処理と同様
にスクラブが必要となる。Further, AuS formed on the optical circuit board
Even when a thin Au layer is deposited on the n-eutectic solder layer, if the deposited Au layer is thinned to maintain the eutectic condition, the Au and AuSn eutectic solder layers in the Au layer can diffuse into each other. As a result, an oxide film is formed on the surface, so that scrubbing is required as in the above-described processing.

【００１２】一方、表面に酸化膜が生ずるのを防ぐため
に、蒸着するＡｕ層を厚くすれば、このＡｕ層のＡｕ及
びＡｕＳｎ共晶半田層のＳｎ相互の拡散によって共晶条
件を保つことができなくなるという問題がある。On the other hand, if the thickness of the deposited Au layer is increased to prevent the formation of an oxide film on the surface, the eutectic condition can be maintained by the mutual diffusion of the Au and AuSn eutectic solder layers of the Au layer with Sn. There is a problem of disappearing.

【００１３】さらに、溶融・固着後にあっては逆に共晶
状態であると融点が低いため、接合部の周囲温度の変
化、特に高温状態において安定した固着状態を維持する
ことができなくなる場合がある。[0013] Further, after melting and fixing, the eutectic state has a low melting point, and consequently, it may not be possible to maintain a stable fixed state at a change in the ambient temperature of the joint, especially at a high temperature. is there.

【００１４】そこで、本発明の目的は上記問題点を解消
し、サブミクロンのオーダで光半導体素子を位置決め固
定することができる光半導体素子接合構造を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an optical semiconductor element bonding structure capable of positioning and fixing an optical semiconductor element on the order of submicrons.

【００１５】[0015]

【課題を解決するための手段】本発明による光半導体素
子接合構造は、光半導体素子を光回路基板上に接合固定
する光半導体素子接合構造であって、光半導体素子は光
回路基板との接合面に形成された第１のＡｕ層を含み、
一方、光回路基板は光半導体素子が接合される接合箇所
に第１のＡｕ層と互いに共晶化される第２のＡｕ層とＳ
ｎ層と第３のＡｕ層の３層が積層されて形成された接合
材を有し、接合材の共晶化により光半導体素子の接合面
を光回路基板上の光半導体素子の接合箇所に接合するよ
うにしたことを特徴としている。An optical semiconductor element bonding structure according to the present invention is an optical semiconductor element bonding structure for bonding and fixing an optical semiconductor element on an optical circuit board, and the optical semiconductor element is bonded to the optical circuit board. A first Au layer formed on the surface,
On the other hand, the optical circuit board is a joint where the optical semiconductor element is joined.
A second Au layer eutecticized with the first Au layer and S
a bonding material formed by laminating three layers of an n layer and a third Au layer, and the bonding surface of the optical semiconductor element is formed at the bonding position of the optical semiconductor element on the optical circuit board by eutectic bonding of the bonding material. It is characterized by joining.

【００１６】特に、接合前の光回路基板側のＡｕ／Ｓｎ
の重量比を概ね８０対２０とし、一方で光半導体素子の
裏面にＡｎ薄膜層が形成された構造で、２８０℃以上で
加熱・溶融して固着する。In particular, Au / Sn on the side of the optical circuit board before bonding.
Is about 80:20, and an An thin film layer is formed on the back surface of the optical semiconductor element, and is fixed by heating and melting at 280 ° C. or more.

【００１７】[0017]

【作用】本発明では、光回路基板上に最上層がＡｕとな
るようにＡｕ及びＳｎを層状に形成し、最上層のＡｕを
含むＡｕ及びＳｎの組成比を、Ａｕが８０％、Ｓｎが２
０％の重量比としている。According to the present invention, Au and Sn are formed in layers on the optical circuit board such that the uppermost layer is made of Au. The composition ratio of Au and Sn including Au in the uppermost layer is 80% for Au and Sn is for 80%. 2
The weight ratio is 0%.

【００１８】光半導体素子を接合する場合、光半導体素
子を光回路基板に接触させて加圧し、光回路基板を加熱
する。この加熱時に温度の上昇とともにＡｕとＳｎとが
相互に拡散する。Ａｕ及びＳｎの相互の拡散は、Ｓｎの
溶融温度以上でより活発となる。When the optical semiconductor element is joined, the optical semiconductor element is brought into contact with the optical circuit board and pressed to heat the optical circuit board. During this heating, Au and Sn diffuse with each other as the temperature rises. The mutual diffusion of Au and Sn becomes more active above the melting temperature of Sn.

【００１９】光回路基板温度が２８０℃以上となり、Ａ
ｕとＳｎとの拡散が進み、Ａｕ対Ｓｎの重量比がほぼ８
０％対２０％となった時点で、ＡｕＳｎ共晶が生成さ
れ、光半導体素子の電極面を濡らす。When the temperature of the optical circuit board becomes 280 ° C. or higher,
The diffusion of u and Sn proceeds, and the weight ratio of Au to Sn is approximately 8
At the time of 0% to 20%, AuSn eutectic is generated and wets the electrode surface of the optical semiconductor element.

【００２０】光回路基板の加熱を継続させると、光半導
体素子の電極内にもＳｎが拡散していき、光回路基板と
光半導体素子の電極面との境界が消滅する。この時点
で、光回路基板を冷却することで接合が完了する。接合
後は、Ｓｎに対するＡｕの重量比が少なくとも８０：２
０となり、状態図の上で共晶状態から積極的にＡｕが多
い状態にずらすことになる。これにより、融点も高くな
り安定した接合状態が得られる。特に、共晶状態から重
量比をずらす場合に、Ｓｎがより多い状態にすると合金
部がもろいのに対して、Ａｕが多い状態ではかかる問題
がない。When the heating of the optical circuit board is continued, Sn diffuses into the electrodes of the optical semiconductor element, and the boundary between the optical circuit board and the electrode surface of the optical semiconductor element disappears. At this point, the bonding is completed by cooling the optical circuit board. After bonding, the weight ratio of Au to Sn is at least 80: 2.
0, which is positively shifted from the eutectic state to the Au-rich state on the phase diagram. As a result, the melting point is increased and a stable bonding state is obtained. In particular, when the weight ratio is shifted from the eutectic state, the alloy portion becomes brittle when the Sn content is increased, whereas this problem does not occur when the Au content is large.

【００２１】[0021]

【実施例】次に、本発明の一実施例について図面を参照
して説明する。Next, an embodiment of the present invention will be described with reference to the drawings.

【００２２】図１は本発明の一実施例を示す構成図であ
る。図において、光回路基板１の光半導体素子実装部２
にはＴｉ層６とＰｔ層７とからなるバリア層８が形成さ
れており、このバリア層８の上にＡｕ層３とＳｎ層４と
が層状に形成されている。FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, an optical semiconductor element mounting portion 2 of an optical circuit board 1 is shown.
Is formed with a barrier layer 8 composed of a Ti layer 6 and a Pt layer 7, and an Au layer 3 and a Sn layer 4 are formed in a layer on the barrier layer 8.

【００２３】また、これらのＡｕ層３及びＳｎ層４の上
の最上層には予め設定された所定厚さのＡｕ層５が形成
され、光半導体素子実装部２の接合部が形成される。こ
の所定厚さはＡｕ層５のＡｕ及びＳｎ層４のＳｎ相互の
拡散が生じても表面に酸化膜が生じにくい厚さ、例えば
０．４μｍ程度とする。On the Au layer 3 and the Sn layer 4, an Au layer 5 having a predetermined thickness is formed on the uppermost layer, and a junction of the optical semiconductor element mounting section 2 is formed. The predetermined thickness is set to a thickness that hardly causes an oxide film to be formed on the surface even when the Au of the Au layer 5 and the Sn of the Sn layer 4 diffuse, for example, about 0.4 μm.

【００２４】この接合部の最上層のＡｕ層５上に光半導
体素子９のＡｕからなる電極面１０を接触させて加圧
し、その後に加熱することで、光回路基板１の光半導体
素子実装部２に光半導体素子９を接合することができ
る。The Au electrode surface 10 of the optical semiconductor element 9 is brought into contact with and pressurized on the Au layer 5 at the uppermost layer of the junction, and then heated, so that the optical semiconductor element mounting section of the optical circuit board 1 is heated. 2, the optical semiconductor element 9 can be joined.

【００２５】図２は図１の光半導体素子９の光回路基板
１への接合を示す図である。図２（ａ）は光半導体素子
９の光回路基板１の光半導体素子実装部２への加圧状態
を示す図であり、図２（ｂ）はＡｕ層３，５とＳｎ層４
との拡散状態を示す図である。また、図２（ｃ）はＡｕ
Ｓｎ共晶が生成された状態を示す図であり、図２（ｄ）
は光半導体素子９の電極面１０とＡｕＳｎ共晶との拡散
状態を示す図である。FIG. 2 is a view showing the bonding of the optical semiconductor element 9 of FIG. 1 to the optical circuit board 1. 2A is a diagram showing a state in which the optical semiconductor element 9 is pressed against the optical semiconductor element mounting portion 2 of the optical circuit board 1, and FIG. 2B is a view showing the Au layers 3 and 5 and the Sn layer 4.
FIG. 4 is a diagram showing a diffusion state of the above. FIG. 2C shows Au.
FIG. 2D is a view showing a state in which a Sn eutectic is generated, and FIG.
FIG. 4 is a view showing a diffusion state between the electrode surface 10 of the optical semiconductor element 9 and the AuSn eutectic.

【００２６】これら図１及び図２を用いて本発明の一実
施例の処理について説明する。光半導体素子９を光回路
基板１に接合する場合、まず光半導体素子９の電極面１
０を光回路基板１の光半導体素子実装部２に形成された
接合部の最上層Ａｕ層５上に接触させて加圧する。［図
２（ａ）参照］。The processing of one embodiment of the present invention will be described with reference to FIGS. When joining the optical semiconductor element 9 to the optical circuit board 1, first, the electrode surface 1 of the optical semiconductor element 9 is bonded.
0 is brought into contact with the uppermost Au layer 5 of the bonding portion formed on the optical semiconductor element mounting portion 2 of the optical circuit board 1 and pressurized. [See FIG. 2 (a)].

【００２７】その後に、光回路基板１を２８０℃以下の
温度で加熱すると、温度の上昇とともにＡｕ層３，５と
Ｓｎ層４との界面でＡｕとＳｎとの相互拡散が進行し、
ＡｕとＳｎとの相互拡散層１１が形成される［図２
（ｂ）参照］。Thereafter, when the optical circuit board 1 is heated at a temperature of 280 ° C. or lower, the interdiffusion of Au and Sn proceeds at the interface between the Au layers 3, 5 and the Sn layer 4 with the rise of the temperature.
An interdiffusion layer 11 of Au and Sn is formed (FIG. 2).
(B)].

【００２８】光回路基板１の温度が２８０℃以上になる
と、Ａｕ層３，５のＡｕ及びＳｎ層４のＳｎの拡散が進
行し、Ａｕ対Ｓｎの重量比がほぼ８０％対２０％になる
と、ＡｕＳｎ共晶１２が生成される［図２（ｃ）参
照］。この時点で、光半導体素子９の電極面１０に存在
する凹凸がＡｕＳｎ共晶１２で濡らされる。When the temperature of the optical circuit board 1 rises to 280 ° C. or higher, diffusion of Au in the Au layers 3 and 5 and Sn in the Sn layer 4 progress, and when the weight ratio of Au to Sn becomes approximately 80% to 20%. , AuSn eutectic 12 is generated [see FIG. 2 (c)]. At this point, the irregularities existing on the electrode surface 10 of the optical semiconductor element 9 are wetted by the AuSn eutectic 12.

【００２９】光回路基板１がさらに加熱されると、光半
導体素子９の電極面１０の内部にもＳｎが拡散してい
き、光半導体素子実装部２の接合部と光半導体素子９の
電極面１０との境界が消滅する［図２（ｄ）参照］。こ
の状態で、光回線基板１を冷却することで接合が完了す
る。When the optical circuit board 1 is further heated, Sn diffuses into the electrode surface 10 of the optical semiconductor element 9, and the junction between the optical semiconductor element mounting portion 2 and the electrode surface of the optical semiconductor element 9 is formed. The boundary with 10 disappears (see FIG. 2D). In this state, the optical circuit board 1 is cooled to complete the joining.

【００３０】このように、光回路基板１の光半導体素子
実装部２上に最上層がＡｕとなるようにＡｕ及びＳｎを
層状に形成し、最上層のＡｕを含むＡｕ及びＳｎの組成
比を、Ａｕが８０％、Ｓｎが２０％の重量比とすること
によって、Ａｕ及びＳｎの複数層を蒸着またはスパッタ
等の手段を用いて形成することが可能となるので、この
層の厚さの精度を非常に高くかつこの層の厚さを薄く形
成することが可能となる。As described above, Au and Sn are formed in layers on the optical semiconductor element mounting portion 2 of the optical circuit board 1 so that the uppermost layer becomes Au, and the composition ratio of Au and Sn including Au in the uppermost layer is changed. , Au at a weight ratio of 80% and Sn at a weight ratio of 20%, a plurality of layers of Au and Sn can be formed by means such as vapor deposition or sputtering. Is very high and the thickness of this layer can be reduced.

【００３１】また、光半導体素子実装部２の接合部を上
記の如く形成することで、光半導体素子９を接合すると
きの加圧力の変化に対する光半導体素子９の沈み込みを
非常に少なくすることができ、光半導体素子９の高さ方
向の精度をサブミクロン以下とすることができる。Further, by forming the bonding portion of the optical semiconductor element mounting portion 2 as described above, the sinking of the optical semiconductor element 9 with respect to the change in the pressing force at the time of bonding the optical semiconductor element 9 is extremely reduced. Accordingly, the accuracy in the height direction of the optical semiconductor element 9 can be made to be submicron or less.

【００３２】さらに、ＡｕＳｎ溶融時に光半導体素子９
の電極面１０の面積に比較して接合部の厚さが非常に薄
いため、電極面１０がＡｕＳｎ共晶１２で濡れたときに
生ずるＡｕＳｎ共晶１２の表面張力の影響は無視できる
程度に小さい。Further, when the AuSn is melted,
Since the thickness of the bonding portion is very small as compared with the area of the electrode surface 10, the influence of the surface tension of the AuSn eutectic 12 generated when the electrode surface 10 is wet with the AuSn eutectic 12 is negligibly small. .

【００３３】さらにまた、最も酸化が生じやすい加熱時
においても、ＡｕＳｎ溶融層が生成されるまで接合部の
最上層にＡｕ層５があるため、表面酸化のないＡｕＳｎ
溶融状態を容易に得ることができる。Furthermore, even during heating, where oxidation is most likely to occur, the Au layer 5 is on the uppermost layer of the junction until the AuSn molten layer is formed.
A molten state can be easily obtained.

【００３４】これにより、光半導体素子９の実装時にＡ
ｕＳｎ共晶１２の表面張力の影響による位置変動が生じ
ず、また酸化膜を除去するためのスクラブを不要とする
ので、光半導体素子９を接合前に高精度に位置決めして
おくことで、ザブミクロンの精度での実装が可能とな
る。Thus, when the optical semiconductor element 9 is mounted, A
Since the position does not fluctuate due to the influence of the surface tension of the uSn eutectic 12 and the scrub for removing the oxide film is not required, positioning the optical semiconductor element 9 with high precision before bonding makes it possible to reduce the submicron size. It is possible to implement with a precision of.

【００３５】また、光回路基板１を保管する場合も表面
層がＡｕで覆われており、かつ化学的に安定しているの
で、汚染のないよう保管することで接合前の酸洗浄等の
煩雑な作業が不要となる。When the optical circuit board 1 is stored, the surface layer is covered with Au and is chemically stable. Work is not required.

【００３６】さらに、通常ＡｕＳｎの合金層を蒸着等に
よって形成しようとした場合、蒸着の条件のばらつき等
によって均一な組成比の合金を形成することが困難であ
る。これに対して、本発明ではＡｕ及びＳｎを蒸着また
はスパッタ等の手段で順次形成するので、接合分の厚さ
を管理するだけでＡｕとＳｎとの均一な組成比を得るこ
とが可能である。よって、安価で、かつ歩留まりよく光
回路基板を製造することが可能となる。Further, when an AuSn alloy layer is usually formed by vapor deposition or the like, it is difficult to form an alloy having a uniform composition ratio due to variations in vapor deposition conditions and the like. On the other hand, in the present invention, since Au and Sn are sequentially formed by means such as vapor deposition or sputtering, it is possible to obtain a uniform composition ratio of Au and Sn only by controlling the thickness of the junction. . Therefore, it is possible to manufacture an optical circuit board at low cost and with good yield.

【００３７】なお、本発明の一実施例では光回路基板１
の光半導体素子実装部２に接合部を形成する例を述べた
が、この接合部を光半導体素子９側に形成しても、また
光半導体素子実装部２及び光半導体素子９の両方に形成
してもよく、これに限定されない。これらの場合、光半
導体素子実装部２及び光半導体素子９の表面層を所定厚
さのＡｕで形成しておく必要がある。In one embodiment of the present invention, the optical circuit board 1
Although the example in which the bonding portion is formed in the optical semiconductor element mounting portion 2 has been described, the bonding portion may be formed on the optical semiconductor device 9 side or may be formed on both the optical semiconductor device mounting portion 2 and the optical semiconductor device 9. However, the present invention is not limited to this. In these cases, the surface layers of the optical semiconductor element mounting section 2 and the optical semiconductor element 9 need to be formed of Au having a predetermined thickness.

【００３８】次に、本発明の光半導体素子接合構造にお
いて、膜構成を変えた他の実施例について説明する。Next, another embodiment in which the film configuration is changed in the optical semiconductor element junction structure of the present invention will be described.

【００３９】光半導体素子等の微小なチップを本発明の
接合構造によって接合する場合、接合電極の面積は、例
えば３００μｍ角の半導体素子で２５０μｍ×６０μｍ
２程度と非常に小さいため、接合層の厚さを薄くするこ
とができる。上述の一実施例で用いたＡｕ／Ｓｎ／Ａｕ
層の厚さは１〜２μｍとなっている。層構成としては、
Ａｕ／Ｓｎ／Ａｕ３層の場合、基板側の接合層のそれぞ
れの厚さを０．４、０．６、０．４μｍ、総膜厚１．４
μｍとし、半導体レーザ側のＡｕ電極膜厚を０．４μｍ
とした場合に良好な結果が得られている。When a small chip such as an optical semiconductor device is bonded by the bonding structure of the present invention, the area of the bonding electrode is, for example, 250 μm × 60 μm for a 300 μm square semiconductor device.
Since it is as small as about 2, the thickness of the bonding layer can be reduced. Au / Sn / Au used in the above embodiment
The thickness of the layer is 1-2 μm. As the layer configuration,
In the case of the Au / Sn / Au3 layer, the thickness of each of the bonding layers on the substrate side is 0.4, 0.6, 0.4 μm, and the total film thickness is 1.4.
μm, and the thickness of the Au electrode on the semiconductor laser side is 0.4 μm.
In this case, good results were obtained.

【００４０】ここでは他の膜厚の組合せとして、Ａｕ／
Ｓｎ／Ａｕをそれぞれ０．６、０．６、０．２μｍとし
た場合について説明する。基本的な構造は上述の一実施
例と同様であり、基板上に半導体レーザを２×１０−３
Ｎで加圧した後、窒素雰囲気中で温度３４０℃で３０秒
間加熱する。図３は、加熱前と加熱後における表面層の
合金状態を薄膜Ｘ線回折で観察した結果を示している。
図３より加熱前はＡｕの回折ピークしか認められず、Ａ
ｕ膜により表面酸化が抑制されていることがわかる。こ
れに対して、加熱後はＡｕとＳｎが拡散してＡｕＳｎ合
金層が形成されていることがわかる。Here, as another combination of film thicknesses, Au /
The case where Sn / Au is 0.6, 0.6, and 0.2 μm, respectively, will be described. The basic structure is the same as that of the above-described embodiment, and a semiconductor laser is placed on a substrate at 2 × 10 −3.
After pressurizing with N, it is heated at 340 ° C. for 30 seconds in a nitrogen atmosphere. FIG. 3 shows the results of observing the alloy state of the surface layer before and after heating by thin film X-ray diffraction.
From FIG. 3, before heating, only the Au diffraction peak was observed,
It can be seen that the surface oxidation is suppressed by the u film. On the other hand, it can be seen that after heating, Au and Sn diffuse to form an AuSn alloy layer.

【００４１】上述の加熱による溶融、固着の接合層にお
けるＡｕＳｎの状態変化は、図３に示すＡｕ−Ｓｎの状
態図を用いて説明することができる。すなわち、加熱前
には基板上のＡｕ／Ｓｎ／Ａｕ層は図中のの状態にあ
り、基板上のＡｕ／Ｓｎ重量比（％）は７０：３０の共
晶状態にある。次に、加熱により温度が上昇するにつれ
ての矢印に従ってＡｕＳｎは拡散が進み、の加熱状
態で完全に溶融する。さらに、基板上の接合層は半導体
レーザの電極のＡｕ膜と接触しているため、Ｓｎは半導
体レーザの電極膜内にも拡散する結果、で示される状
態に移行する。この状態で加熱を停止することにより、
冷却され接合が完了する。従って、加熱後はもとの接合
層のＡｕ／Ｓｎの重量比とは異なったものとなる。The change in the state of AuSn in the melted and fixed bonding layer due to the above-described heating can be explained with reference to the state diagram of Au-Sn shown in FIG. That is, before heating, the Au / Sn / Au layer on the substrate is in the state shown in the figure, and the Au / Sn weight ratio (%) on the substrate is in the eutectic state of 70:30. Next, as the temperature rises due to heating, the diffusion of AuSn proceeds in accordance with the arrow, and the AuSn is completely melted in the heated state. Further, since the bonding layer on the substrate is in contact with the Au film of the electrode of the semiconductor laser, Sn also diffuses into the electrode film of the semiconductor laser, so that the state shifts to the state shown by. By stopping the heating in this state,
Cooling completes joining. Therefore, after the heating, the weight ratio of Au / Sn of the original bonding layer is different.

【００４２】以上説明したような本発明の膜構成を採用
することにより、従来行っていたスクラブをすることな
く、完全な接合を行うなうことができるようになる。こ
のため、スクラブにより生じていた接合精度を向上させ
ることができる。By adopting the film configuration of the present invention as described above, it is possible to perform complete bonding without performing scrub which has been conventionally performed. For this reason, the joining accuracy caused by the scrub can be improved.

【００４３】次に、本発明の他の実施例により接合した
光半導体素子の接合精度について説明する。図４は、接
合部の高さ方向のばらつきの測定結果を示しており、ば
らつきはσ＝０．１８μｍと非常に小さいことがわか
る。なお、接合後の接合層は溶融時に加圧することから
わずかに水平方向に広がるため、接合前より約０．４μ
ｍ低くなっている。高さ方向の位置ずれについてはばら
つきさえ小さければ、あらかじめ位置ずれ分をオフセッ
トしておくことにより、結合特性の低下を回避すること
ができる。Next, the joining accuracy of the optical semiconductor device joined according to another embodiment of the present invention will be described. FIG. 4 shows the measurement results of the variation in the height direction of the bonding portion, and it can be seen that the variation is extremely small as σ = 0.18 μm. Since the bonding layer after bonding spreads slightly in the horizontal direction due to pressurization during melting, it is about 0.4 μm more than before bonding.
m lower. If there is only a small variation in the positional deviation in the height direction, a reduction in the coupling characteristics can be avoided by offsetting the positional deviation in advance.

【００４４】また、図５は接合による基板および半導体
レーザにマークを付して、光半導体素子の水平方向の位
置ずれ量を測定した結果を示している。接合層が比較的
薄いために表面張力による影響を抑制でき、しかもスク
ラブが必要ないために、位置ずれ量は平均で０．４６μ
ｍと良好な結果が得られている。FIG. 5 shows the result of measuring the horizontal displacement of the optical semiconductor device by marking the substrate and the semiconductor laser by bonding. Since the bonding layer is relatively thin, the influence of surface tension can be suppressed, and no scrub is required.
m and a good result are obtained.

【００４５】また、初期的な接合強度は、ダイシェア強
度で約８０ｇであり、温度サイクル印加後も劣化傾向は
認められていない。特に、接合前の光回路基板側のＡｕ
とＳｎの重量比を８０：２０として共晶状態からＡｕが
多い方にずらすことによって、共晶状態を維持した接合
よりもより安定した接合が得られている。The initial bonding strength is about 80 g in die shear strength, and no deterioration tendency is observed even after the application of the temperature cycle. In particular, Au on the optical circuit board side before bonding is used.
By shifting the weight ratio of Sn and Sn to 80:20 and shifting from the eutectic state to the one with more Au, more stable bonding is obtained than the bonding maintaining the eutectic state.

【００４６】[0046]

【発明の効果】以上説明したように本発明によれば、光
半導体素子の接合面及び光回路基板上の光半導体素子の
接合箇所のうち少なくとも一方に、他方との接合面に形
成されたＡｕ層を含みかつ互いに共晶化されるＡｕ層及
びＳｎ層が積層されて形成された接合材の共晶化により
光半導体素子の接合面を光回路基板上の光半導体素子の
接合箇所に接合することによって、サブミクロンのオー
ダで光半導体素子を位置決め固定することができるとい
う効果がある。しかも、接合後は共晶状態よりもＡｕの
重量比が多い状態にすることでより高温対してより安定
した接合が得られる。As described above, according to the present invention, Au formed on at least one of the bonding surface of the optical semiconductor device and the bonding portion of the optical semiconductor device on the optical circuit board, and on the bonding surface with the other. The bonding surface of the optical semiconductor element is bonded to the bonding portion of the optical semiconductor element on the optical circuit board by eutectic bonding of a bonding material formed by laminating an Au layer and a Sn layer that include layers and are eutectic with each other. This has the effect that the optical semiconductor element can be positioned and fixed on the order of submicrons. In addition, by setting the weight ratio of Au to be larger than that in the eutectic state after bonding, more stable bonding can be obtained at higher temperatures.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例を示す構成図である。FIG. 1 is a configuration diagram showing one embodiment of the present invention.

【図２】（ａ）は光半導体素子と光回路基板の光半導体
素子実装部への加圧状態を示す図、（ｂ）はＡｕ層とＳ
ｎ層との拡散状態を示す図、（ｃ）はＡｕＳｎ共晶が生
成された状態を示す図、（ｄ）は光半導体素子の電極面
とＡｕＳｎ共晶との拡散状態を示す図である。FIG. 2A is a diagram showing a state in which an optical semiconductor element and an optical circuit board are pressed against an optical semiconductor element mounting portion, and FIG. 2B is a view showing an Au layer and an S layer;
FIG. 3C is a diagram illustrating a diffusion state with an n-layer, FIG. 3C is a diagram illustrating a state in which an AuSn eutectic is generated, and FIG. 3D is a diagram illustrating a diffusion state between an electrode surface of the optical semiconductor element and the AuSn eutectic.

【図３】接合膜の加熱前後の薄膜Ｘ線回折による成分分
析結果FIG. 3 is a result of component analysis by thin-film X-ray diffraction before and after heating of a bonding film.

【図４】本発明で他の実施例で用いた接合膜の接合過程
における状態変化を示すＡｕＳｎ状態図FIG. 4 is an AuSn state diagram showing a state change in a bonding process of a bonding film used in another embodiment of the present invention.

【図５】本発明の光半導体素子接合構造における高さ方
向の位置ずれ量FIG. 5 shows the amount of displacement in the height direction in the optical semiconductor element junction structure of the present invention.

【図６】本発明の光半導体素子接合構造における水平方
向の位置ずれ量FIG. 6 shows the amount of positional deviation in the horizontal direction in the optical semiconductor element junction structure of the present invention.

【図７】本発明の光半導体素子接合構造の接合部の強度
試験結果を示す図FIG. 7 is a diagram showing a strength test result of a bonding portion of the optical semiconductor device bonding structure of the present invention.

【符号の説明】[Explanation of symbols]

１ 光回路基板 ２ 光半導体素子実装部 ３ Ａｕ層 ４ Ｓｎ層 ５ 最上層のＡｕ層 ９ 光半導体素子 １０ 電極面 DESCRIPTION OF SYMBOLS 1 Optical circuit board 2 Optical semiconductor element mounting part 3 Au layer 4 Sn layer 5 Uppermost Au layer 9 Optical semiconductor element 10 Electrode surface

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 光半導体素子を光回路基板上に接合固定
する光半導体素子接合構造であって、 前記光半導体素子は前記光回路基板との接合面に形成さ
れた第１のＡｕ層を含み、前記光回路基板は前記光半導体素子が接合される接合箇
所に前記第１のＡｕ層と互いに共晶化される第２のＡｕ
層とＳｎ層と第３のＡｕ層の３層が 積層されて形成され
た接合材を有し、 前記接合材の共晶化により前記光半導体素子の接合面を
前記光回路基板上の前記光半導体素子の接合箇所に接合
するようにしたことを特徴とする光半導体素子接合構
造。1. An optical semiconductor element bonding structure for bonding and fixing an optical semiconductor element on an optical circuit board, wherein the optical semiconductor element includes a first Au layer formed on a bonding surface with the optical circuit board. The optical circuit board is a joint member to which the optical semiconductor element is joined.
Where the second Au layer is eutecticized with the first Au layer.
And a bonding material formed by laminating three layers of a layer, a Sn layer, and a third Au layer. The bonding surface of the optical semiconductor element is formed on the optical circuit board by eutectic bonding of the bonding material. An optical semiconductor element bonding structure, wherein the optical semiconductor element is bonded to a bonding portion of a semiconductor element. 【請求項２】 前記他方との接合面に形成されたＡｕ層
が予め設定された所定厚さを有し、前記接合材を構成す
るＡｕ層とＳｎ層との重量比が約８０対２０であること
を特徴とする請求項１記載の光半導体素子接合構造。2. An Au layer formed on a bonding surface with the other has a predetermined thickness, and a weight ratio of the Au layer and the Sn layer constituting the bonding material is about 80:20. 2. The optical semiconductor element junction structure according to claim 1 , wherein the optical semiconductor element junction structure is provided. 【請求項３】 前記光半導体素子の接合面及び前記回路
基板上の前記光半導体素子の接合面に夫々前記Ａｕ層が
形成されていることを特徴とする請求項１または請求項
２記載の光半導体素子接合構造。3. A process according to claim 1 or claim, characterized in that each said Au layer on the bonding surface of the optical semiconductor element of the bonding surface and the circuit board of the optical semiconductor element is formed
3. The optical semiconductor element bonding structure according to 2. 【請求項４】 前記Ａｕ、Ｓｎ、Ａｕの３層の総膜厚が
１μｍ以上２μｍ以下であることを特徴とする請求項１
から請求項３までにいずれかの請求項に記載の光半導体
素子接合構造。4. The method of claim 1, wherein said Au, Sn, the total thickness of the three layers of Au is 1μm or more 2μm or less
The optical semiconductor element junction structure according to any one of claims 1 to 3 . 【請求項５】 光半導体素子の実装面側の表面に第１の
Ａｕ層を形成する工程と、 前記光半導体素子が実装される光回路基板の表面に、第
２のＡｕ層、Ｓｎ層、第３のＡｕ層の３層を、前記第２
のＡｕ層及び前記第３のＡｕ層の重量の総和と前記Ｓｎ
層の重量の重量比が約８０対２０になるようにを形成す
る工程と、 前記光半導体素子の実装面と前記光回路基板の表面を接
合させる工程と、 前記光回路基板を２８０℃以上に加熱する工程と、 前記光回路基板を常温に冷却する工程と、 を含むことを特徴とする光半導体素子の接合方法。5. A step of forming a first Au layer on a surface on a mounting surface side of an optical semiconductor element, and forming a first Au layer on an optical circuit board on which the optical semiconductor element is mounted .
The second Au layer, the Sn layer, and the third Au layer were
Of the total weight of the Au layer and the third Au layer and the Sn
Forming a layer so that the weight ratio of the layers is about 80 to 20; bonding the mounting surface of the optical semiconductor element to the surface of the optical circuit board; and keeping the optical circuit board at 280 ° C. or higher. A method for bonding optical semiconductor elements, comprising: a step of heating; and a step of cooling the optical circuit board to room temperature. 【請求項６】 前記第２のＡｕ層と前記Ｓｎ層と前記第
３のＡｕ層の３総の総膜厚が１μｍ以上２μｍ以下であ
ることを特徴とする請求項５記載のを含むことを特徴と
する光半導体素子の接合方法。 6. The second Au layer, the Sn layer, and the second
The total thickness of the three Au layers is 1 μm or more and 2 μm or less.
6. The method according to claim 5, further comprising:
Method for joining optical semiconductor elements.
JP3617194A 1993-04-27 1994-03-07 Optical semiconductor device bonding structure and bonding method Expired - Lifetime JP2797958B2 (en)

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WO2007119571A1 (en) * 2006-04-17 2007-10-25 Dowa Electronics Materials Co., Ltd. Solder layer, substrate for device junction utilizing the same, and process for manufacturing the substrate
JP2009130300A (en) * 2007-11-27 2009-06-11 Panasonic Electric Works Co Ltd Method of manufacturing light-emitting device
US9620478B2 (en) 2011-11-18 2017-04-11 Apple Inc. Method of fabricating a micro device transfer head
US8426227B1 (en) * 2011-11-18 2013-04-23 LuxVue Technology Corporation Method of forming a micro light emitting diode array
US8349116B1 (en) 2011-11-18 2013-01-08 LuxVue Technology Corporation Micro device transfer head heater assembly and method of transferring a micro device
US8573469B2 (en) 2011-11-18 2013-11-05 LuxVue Technology Corporation Method of forming a micro LED structure and array of micro LED structures with an electrically insulating layer
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