JP2782870B2 - Lead frame - Google Patents

Lead frame

Info

Publication number
JP2782870B2
JP2782870B2 JP1332061A JP33206189A JP2782870B2 JP 2782870 B2 JP2782870 B2 JP 2782870B2 JP 1332061 A JP1332061 A JP 1332061A JP 33206189 A JP33206189 A JP 33206189A JP 2782870 B2 JP2782870 B2 JP 2782870B2
Authority
JP
Japan
Prior art keywords
lead frame
insulating film
pattern
lead pattern
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1332061A
Other languages
Japanese (ja)
Other versions
JPH03191541A (en
Inventor
晋 中森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1332061A priority Critical patent/JP2782870B2/en
Publication of JPH03191541A publication Critical patent/JPH03191541A/en
Application granted granted Critical
Publication of JP2782870B2 publication Critical patent/JP2782870B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテープキャリア方式によって製造される半導
体集積回路装置において用いるリードフレームに関す
る。Description: TECHNICAL FIELD The present invention relates to a lead frame used in a semiconductor integrated circuit device manufactured by a tape carrier system.

〔従来の技術〕[Conventional technology]

従来、この種のテープキャリア方式は、ポリイミド樹
脂等の絶縁性のフレキシブルなフィルム上に密着して設
けられた導電性の材料からなるリードを有するリードフ
レームと半導体装置に設けられた突起電極とを直接に熱
圧着する組み立て方式であり、長尺状のフィルムに同一
のリードパターンを連続して形成できるので、半導体装
置をリードフレームに熱圧着した後は、半導体装置の電
気的試験が自動的にできるという長所がある。Conventionally, this type of tape carrier method involves a lead frame having leads made of a conductive material provided in close contact with an insulating flexible film such as a polyimide resin and a projection electrode provided on a semiconductor device. This is an assembly method in which thermocompression bonding is performed directly.The same lead pattern can be continuously formed on a long film, so after the semiconductor device is thermocompression bonded to the lead frame, the electrical test of the semiconductor device is automatically performed. There is an advantage that you can do it.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来のテープキャリア方式用のリードフレー
ムは、第３図の平面図のように、均質のテープ状のポリ
イミド等の絶縁性フィルム１の両側に等間隔のスプロケ
ットホール２を設け、中央部にデバイスホール４を開け
てリードパターン３を金属腐触法および電気鍍金法等に
よって連続的に形成する。In the above-described lead frame for the tape carrier system, as shown in the plan view of FIG. 3, sprocket holes 2 are provided at equal intervals on both sides of an insulating film 1 made of a homogeneous tape-like polyimide or the like. The device hole 4 is opened, and the lead pattern 3 is continuously formed by a metal erosion method, an electroplating method or the like.

リードパターンの一端側は、デバイスホール４に突き
出したものとなっており、リードパターン先端部3aにお
いて半導体装置５の電極に熱圧着され、リードパターン
の他端の電極端子3bに探針等を接触させて半導体装置の
電気的特性を測定したり、スクリーニング時のバイアス
印加をおこなうことができる。One end of the lead pattern protrudes into the device hole 4 and is thermocompression-bonded to the electrode of the semiconductor device 5 at the tip 3a of the lead pattern, and a probe or the like contacts the electrode terminal 3b at the other end of the lead pattern. Thus, the electrical characteristics of the semiconductor device can be measured, and a bias can be applied during screening.

しかし、かかる従来技術のリードフレームは、第４図
（第３図のＡ−Ａ断面図）のように、絶縁性フィルム１
上面にリードパターン３が凸状に形成されているため、
製造工程において、擦れ等によりリードパターンが変形
し、パターンショート等をおこし歩留りを大きく低下さ
せるものとなっていた。However, as shown in FIG. 4 (a cross-sectional view taken along the line AA in FIG. 3), such a conventional lead frame has an insulating film 1.
Since the lead pattern 3 is formed in a convex shape on the upper surface,
In the manufacturing process, the lead pattern is deformed due to rubbing or the like, causing a pattern short circuit or the like, thereby greatly reducing the yield.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の絶縁性フィルムに電極用リードパターンと同
形状の溝を形成し、この溝に導電性材料を埋め込んだ構
造を有している。A groove having the same shape as the electrode lead pattern is formed in the insulating film of the present invention, and a conductive material is embedded in the groove.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第１図は本発明の実施例１の縦断面図である。 FIG. 1 is a longitudinal sectional view of Embodiment 1 of the present invention.

本実施例のリードフレームは、均質のテープ状のポリ
イミド等の絶縁性フィルム１にリードパターンｃが埋め
込まれたものとなっている。リードパターン3cは、絶縁
性フィルム１の表面に対し、例えば20μｍの高低差とす
る。In the lead frame of this embodiment, a lead pattern c is embedded in a homogeneous tape-like insulating film 1 such as polyimide. The lead pattern 3c has a height difference of, for example, 20 μm with respect to the surface of the insulating film 1.

本実施例の製造方法は、絶縁性フィルム１にリードパ
ターンと同じ形状の溝パターンをエッチングにより形成
し、この溝パターンを形成した絶縁性フィルム１の面に
銅箔等の導電性材料を圧着し、溝内に導電性材料を埋め
込んだ後、エッチングにより不要部分を除去することに
よりリードパターン3cを形成する。又、溝パターンの他
の形成方法としては、あらかじめリードパターンと同形
状の抜き穴を形成した絶縁性フィルムと、穴を有しない
絶縁性フィルムを貼り合わせることによっても形成でき
る。In the manufacturing method of this embodiment, a groove pattern having the same shape as the lead pattern is formed on the insulating film 1 by etching, and a conductive material such as a copper foil is pressed on the surface of the insulating film 1 on which the groove pattern is formed. After the conductive material is embedded in the groove, unnecessary portions are removed by etching to form the lead pattern 3c. In addition, as another method of forming the groove pattern, the groove pattern can be formed by laminating an insulating film having holes formed in the same shape as the lead pattern in advance and an insulating film having no holes.

第２図は本発明の実施例２の縦断面図である。本実施
例によるリードパターン3dは、絶縁性フィルムと同一表
面を有するように埋め込まれている。この実施例では、
リードフレームの表面が平坦であるため、ごみ等が溜ま
りにくいという利点がある。FIG. 2 is a longitudinal sectional view of Embodiment 2 of the present invention. The lead pattern 3d according to the present embodiment is embedded so as to have the same surface as the insulating film. In this example,
Since the surface of the lead frame is flat, there is an advantage that dust and the like hardly accumulate.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、リードフレームのリー
ドパターンが絶縁性フィルムの面より飛び出していない
構造にすることにより、半導体集積回路装置の製造工程
において、リードフレームの擦れ等によりリードパター
ンのショートを皆無とする効果がある。これにより、半
導体集積回路装置の歩留りを大幅に向上させることがで
きる。As described above, the present invention employs a structure in which the lead pattern of the lead frame does not protrude from the surface of the insulating film. It has the effect of eliminating everything. Thereby, the yield of the semiconductor integrated circuit device can be significantly improved.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の実施例１の縦断面図、第２図は本発明
の実施例２の縦断面図、第３図は従来のリードフレーム
の平面図、第４図は第３図のＡ−Ａ線断面図である。 １……絶縁性フィルム、２……スプロケットホール、３
……リードパターン、４……デバイスホール、５……半
導体装置、3a……リードパターン先端部、3b……電極端
子、3c……リードパターン、3d……リードパターン。1 is a longitudinal sectional view of Embodiment 1 of the present invention, FIG. 2 is a longitudinal sectional view of Embodiment 2 of the present invention, FIG. 3 is a plan view of a conventional lead frame, and FIG. FIG. 3 is a sectional view taken along line AA. 1 ... insulating film, 2 ... sprocket hole, 3
…… lead pattern, 4 …… device hole, 5 …… semiconductor device, 3a …… lead pattern tip, 3b …… electrode terminal, 3c …… lead pattern, 3d …… lead pattern.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】絶縁性フィルムに密着した電極用リードパ
ターンを有する長尺状のリードフレームにおいて、前記
絶縁性フィルムに前記電極用リードパターンと同形状の
溝を形成し、この溝に導電性材料を埋め込んだことを特
徴とするリードフレーム。In a long lead frame having an electrode lead pattern closely attached to an insulating film, a groove having the same shape as the electrode lead pattern is formed in the insulating film, and a conductive material is formed in the groove. A lead frame having embedded therein.
JP1332061A 1989-12-20 1989-12-20 Lead frame Expired - Lifetime JP2782870B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1332061A JP2782870B2 (en) 1989-12-20 1989-12-20 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1332061A JP2782870B2 (en) 1989-12-20 1989-12-20 Lead frame

Publications (2)

Publication Number Publication Date
JPH03191541A JPH03191541A (en) 1991-08-21
JP2782870B2 true JP2782870B2 (en) 1998-08-06

Family

ID=18250708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1332061A Expired - Lifetime JP2782870B2 (en) 1989-12-20 1989-12-20 Lead frame

Country Status (1)

Country Link
JP (1) JP2782870B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001099344A2 (en) 2000-06-14 2001-12-27 Williams Communications, Llc Route selection within a network with peering connections
JP4146826B2 (en) 2004-09-14 2008-09-10 カシオマイクロニクス株式会社 Wiring substrate and semiconductor device
US9014047B2 (en) 2007-07-10 2015-04-21 Level 3 Communications, Llc System and method for aggregating and reporting network traffic data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197757A (en) * 1982-05-13 1983-11-17 Nec Corp Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197757A (en) * 1982-05-13 1983-11-17 Nec Corp Lead frame

Also Published As

Publication number Publication date
JPH03191541A (en) 1991-08-21

Similar Documents

Publication Publication Date Title
KR100223727B1 (en) Semiconductor device
JP2583597B2 (en) Integrated circuit device package
US6225146B1 (en) Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device
US4984059A (en) Semiconductor device and a method for fabricating the same
JPH02502323A (en) Support assembly for integrated circuits
JP3455685B2 (en) Method for manufacturing semiconductor device
US5382546A (en) Semiconductor device and method of fabricating same, as well as lead frame used therein and method of fabricating same
JP2936769B2 (en) Lead frame for semiconductor device
JP2782870B2 (en) Lead frame
TW419756B (en) Process for producing BGA type semiconductor device, TAB tape for BGA type semiconductor device, and BGA type semiconductor device
JPH05326648A (en) Film carrier and manufacture of semiconductor device employing film carrier
JPH07201928A (en) Film carrier and semiconductor device
JPH03261153A (en) Package for semiconductor device
JP3665609B2 (en) Semiconductor device and semiconductor device unit having a plurality of semiconductor devices mounted thereon
JP3855941B2 (en) Manufacturing method of semiconductor device with convex heat sink
JPH1140728A (en) Lead frame and electronic component using the same, and manufacture thereof
JP3093704B2 (en) Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device
JP2784209B2 (en) Semiconductor device
JP3824076B2 (en) Film carrier tape manufacturing method
JPH11297740A (en) Carrier tape having semiconductor chip mounted thereon, and semiconductor device
JPS63169746A (en) Semiconductor device
JP2555878B2 (en) Method of manufacturing film carrier tape
KR930005495B1 (en) Lead frame and manufacturing thereof
JP3925280B2 (en) Manufacturing method of semiconductor device
JPH01210393A (en) Integrated circuit device