JP2780501B2 - Semiconductor wafer with insulating film and method of manufacturing the same - Google Patents
Semiconductor wafer with insulating film and method of manufacturing the sameInfo
- Publication number
- JP2780501B2 JP2780501B2 JP3019283A JP1928391A JP2780501B2 JP 2780501 B2 JP2780501 B2 JP 2780501B2 JP 3019283 A JP3019283 A JP 3019283A JP 1928391 A JP1928391 A JP 1928391A JP 2780501 B2 JP2780501 B2 JP 2780501B2
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- Japan
- Prior art keywords
- insulating film
- semiconductor wafer
- interface
- gaas
- state density
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Local Oxidation Of Silicon (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はウェハ上に絶縁膜を堆積
させた絶縁膜付き半導体ウェハ及びその製造方法に係
り、特に絶縁膜を安定に形成するものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer with an insulating film formed by depositing an insulating film on a wafer and a method for manufacturing the same, and more particularly to a method for stably forming an insulating film.
【０００２】[0002]
【従来の技術】ＭＩＳＦＥＴ（金属絶縁物半導体電界効
果トランジスタ）は、Ｓｉ基板上に形成するＭＯＳＦＥ
Ｔ（金属酸化物半導体電界効果トランジスタ）を代表例
として、ＬＳＩ等に幅広く使用されている。ＭＩＳＦＥ
Ｔの長所はＭＥＳＦＥＴ（金属半導体電界効果トランジ
スタ）と比較して、論理振幅を大きく取れる。逆方
向の耐電圧が大きい等が挙げられる。2. Description of the Related Art A MISFET (Metal Insulator Semiconductor Field Effect Transistor) is a MOSFE formed on a Si substrate.
T (metal oxide semiconductor field effect transistor) is a typical example and is widely used in LSIs and the like. MISFE
The advantage of T is that the logic amplitude can be larger than that of MESFET (metal semiconductor field effect transistor). The withstand voltage in the reverse direction is large.
【０００３】このＭＩＳＦＥＴを作成するためには、絶
縁物−半導体界面の界面準位が少なく、良好な界面を形
成する必要がある。Ｓｉ、ＩｎＰ等は表面準位（表面欠
陥密度または表面の結晶の乱れ度）が１０10〜１０11ｃ
ｍ~2と小さいため、良好なＭＩＳＦＥＴを作成すること
ができるが、ＧａＡｓでは１０12〜１０13ｃｍ~2と多い
ため、現在までに、良好なＭＩＳＦＥＴは実現されてい
ない。In order to manufacture this MISFET, it is necessary to form a good interface with a small interface state at the insulator-semiconductor interface. Si, InP and the like have a surface state (surface defect density or degree of disorder of the surface crystal) of 10 10 to 10 11 c.
A good MISFET can be produced because it is as small as m ~ 2 , but a good MISFET has not been realized until now because GaAs is as large as 10 12 to 10 13 cm ~ 2 .
【０００４】ＧａＡｓはＳｉと比較すると、電子移動度
は５〜６倍大きく、物性値としてはＳｉより優位なので
あるが、前述したように表面準位が大きいためＭＩＳＦ
ＥＴの開発はあまり活発化していなかった。しかし、下
記の文献が相次いで発表されるに至り、活発化してき
た。[0004] GaAs has an electron mobility 5 to 6 times larger than Si and is superior in physical properties to Si.
ET development was not very active. However, the following publications have been published one after another and have been activated.
【０００５】文献１：C.J.Sandroff et al.,Dramatic e
nhancement in the gain of a GaAs/AlGaAs heterostru
cture bipolar transistor by surface chemical passi
vation,Appl.Phys.Lett.51(1),6 July 1987,pp.33-35. 文献２：E.Yablonovitch et al.,Nearly ideal electro
nic properties of sulfide coated GaAs surfaces,App
l.Phys.Lett.51(6),10 August 1987,pp.439-441. 文献３：J.F.Fan et al.,The effect of （NH4）2 S tr
eatment on the interface characteristics of GaAs M
IS structures,JJAP.27,7 July 1988,pp.L1331-L1333. １９８６年、Ｂｅｌｌ研究所のＳａｎｄｒｏｆｆらが、
ＧａＡｓ−ＡｌＧａＡｓ ＨＢＴ（ヘテロバイポーラト
ランジスタ）をＮａ2 Ｓ・９Ｈ2 Ｏで表面処理すること
により表面再結合中心の密度を大幅に減少することがで
きたと報告し、着目された（文献１）。また、後に（Ｎ
Ｈ4 ）2 Ｓ処理の効果も発表されている（文献２）。Reference 1: CJ Sandroff et al., Dramatic e
nhancement in the gain of a GaAs / AlGaAs heterostru
cture bipolar transistor by surface chemical passi
vation, Appl. Phys. Lett. 51 (1), 6 July 1987, pp. 33-35. Reference 2: E. Yablonovitch et al., Nearly ideal electro
nic properties of sulfide coated GaAs surfaces, App
l.Phys. Lett. 51 (6), 10 August 1987, pp. 439-441. Reference 3: JFFan et al., The effect of (NH 4 ) 2 S tr
eatment on the interface characteristics of GaAs M
IS structures, JJAP.27,7 July 1988, pp.L1331-L1333. In 1986, Sandroff et al.
It was reported that the surface treatment of GaAs-AlGaAs HBTs (hetero bipolar transistors) with Na 2 S.9H 2 O could greatly reduce the density of surface recombination centers (Reference 1). Also, later (N
The effect of the H 4 ) 2 S treatment has also been published (Reference 2).
【０００６】日本では筑波大学の南日教授らが（ＮＨ
4 ）2 ＳX （ｘ＝１〜３）処理による表面準位の低減を
報告している（文献３）。以下、これらの処理効果を簡
単に説明する。In Japan, Professor Nanichi of Tsukuba University (NH)
4) 2 S X (x = 1~3) have reported a reduction in surface states by treatment (Reference 3). Hereinafter, these processing effects will be briefly described.
【０００７】ＧａＡｓは自然酸化膜とよばれるＧａ2 Ｏ
3 ，Ａｓ2 Ｏ3 等の酸化物により覆われている。これら
の酸化物の存在によりＧａＡｓの清浄表面が得られず、
絶縁膜(Insulator）をＧａＡｓ上に形成しても界面準位
が多く、良好なＭＩＳが得られない。（ＮＨ4 ）2 Ｓ処
理等を行なうと、これらの自然酸化膜がエッチングされ
て清浄面ができ、その後、Ｏ原子よりＳ原子がＧａ原子
と強固に結合する。即ち、Ｓ原子でターミネイトされる
ことにより、ＧａＡｓ表面は酸化に対し不活性になり、
表面準位が少なくなるわけである。Ｓ原子層は面密度で
言うと１／２単原子層付着していると報告されている
（文献１）。以上により、Ｎａ2 Ｓ・９Ｈ2 Ｏや、（Ｎ
Ｈ4 ）2 ＳX で処理すれば、表面準位の少ないＧａＡｓ
表面が得られることがわかった。GaAs is Ga 2 O which is called a natural oxide film.
3, are covered with As oxide such as 2 O 3. A clean surface of GaAs cannot be obtained due to the presence of these oxides,
Even if an insulating film (Insulator) is formed on GaAs, there are many interface states, and a good MIS cannot be obtained. When (NH 4 ) 2 S treatment or the like is performed, these natural oxide films are etched to form a clean surface, and thereafter, S atoms are more strongly bonded to Ga atoms than O atoms. That is, by being terminated with S atoms, the GaAs surface becomes inert to oxidation,
The surface level is reduced. It has been reported that the S atomic layer adheres to a 単 monoatomic layer in terms of areal density (Reference 1). As described above, Na 2 S · 9H 2 O and (N
If treated with H 4 ) 2 S X , GaAs with few surface states
It was found that a surface was obtained.
【０００８】[0008]
【発明が解決しようとする課題】Ｎａ2 Ｓ・９Ｈ2 Ｏ処
理の場合は表面再結合中心の密度を大幅に減少の効果
が、水洗で簡単に失われるという報告がある（文献
１）。効果の持続性という意味では（ＮＨ4 ）2 ＳX 処
理の方が優れているが、これも１０~5torr程度で約２５
０℃にするとＳ原子によるターミネイションが分解して
しまい、効果がなくなってしまう。従って、絶縁膜を半
導体基板上に形成するのによく使用される装置であっ
て、装置内１０~5torr、３５０℃程度となるプラズマＣ
ＶＤ装置を用いるとその効果がなくなるため、良好な絶
縁物−半導体界面が得られず、結局、ＭＩＳＦＥＴを作
成することができないという問題点がある。即ち、最初
のＧａＡｓ表面の表面準位が小さくても、絶縁膜を形成
するときに界面準位が発生してしまうのである。There is a report that in the case of Na2 S.9H2 O treatment, the effect of greatly reducing the density of surface recombination centers is easily lost by washing with water (Reference 1). The (NH 4 ) 2 S X treatment is superior in terms of the effect persistence, but is also about 25 at about 10 to 5 torr.
When the temperature is set to 0 ° C., the termination due to S atoms is decomposed, and the effect is lost. Therefore, it is an apparatus which is often used for forming an insulating film on a semiconductor substrate, and a plasma C of about 10 to 5 torr and about 350 ° C.
When a VD device is used, its effect is lost, so that a good insulator-semiconductor interface cannot be obtained, and as a result, there is a problem that a MISFET cannot be formed. That is, even if the surface level of the first GaAs surface is small, an interface level is generated when the insulating film is formed.
【０００９】この絶縁膜形成技術上の問題はＧａＡｓウ
ェハに限られるものではなく、広く表面準位の大きい半
導体ウェハにも共通する。[0009] This problem in the technique of forming an insulating film is not limited to a GaAs wafer, but is also common to a semiconductor wafer having a large surface level.
【００１０】本発明の目的は、表面処理を進めて絶縁膜
内からの処理を行うことによって、前述した従来技術の
欠点を解消し、ＭＩＳＦＥＴが安定して作成できる新規
な絶縁膜付き半導体ウェハ及びその製造方法を提供する
ことにある。An object of the present invention is to solve the above-mentioned drawbacks of the prior art by performing surface treatment to perform processing from within the insulating film, and to provide a novel semiconductor wafer with an insulating film capable of stably forming a MISFET. It is to provide a manufacturing method thereof.
【００１１】[0011]
【課題を解決するための手段】本発明の絶縁膜付き半導
体ウェハは、ＧａＡｓからなる半導体ウェハ上に堆積さ
せた絶縁膜のうち、半導体ウェハとの界面近傍の領域に
のみ、ＳまたはＳｅからなる界面準位密度を減少させる
元素がドーピングされているものである。According to the present invention, there is provided a semiconductor wafer provided with an insulating film , which is formed in a region near an interface with a semiconductor wafer in an insulating film deposited on a GaAs semiconductor wafer.
Only an element which is made of S or Se and is doped with an element for reducing the interface state density is used.
【００１２】また、本発明の絶縁膜付き半導体ウェハの
製造方法は、ＧａＡｓからなる半導体ウェハ上に絶縁膜
を堆積させる際に、ＳまたはＳｅからなる界面準位密度
を減少させる元素を絶縁膜の堆積開始から所定時間ドー
ピングして、絶縁膜のうち半導体ウェハとの界面近傍の
領域にのみ界面準位密度を減少させる元素がドーピング
されている絶縁膜を形成することにあり、これによっ
て、良好な絶縁物−半導体界面を有する絶縁膜付き半導
体ウェハを再現性よく、安定に作成できるようにしたも
のである。Further, according to the method of manufacturing a semiconductor wafer with an insulating film of the present invention, an insulating film is formed on a GaAs semiconductor wafer.
State density of S or Se when depositing
Doping for a specified time from the start of the deposition of the insulating film.
Ping, and the insulating film near the interface with the semiconductor wafer
Doping elements that reduce the interface state density only in the region
It is located to form a has insulating film, thereby, good insulator - semiconductor interface with good reproducibility insulating film-attached semiconductor wafer having, in which to be able to create stable.
【００１３】なお、絶縁膜を堆積する前には、半導体ウ
ェハの表面を（ＮＨ 4 ） 2 Ｓまたは（ＮＨ 4 ） 2 Ｓ X で
表面処理することが望ましい。 Before depositing an insulating film, a semiconductor wafer is deposited.
The surface of the E c (NH 4) 2 S or (NH 4) with 2 S X
Surface treatment is desirable.
【００１４】[0014]
【作用】半導体ウェハ表面を清浄にするために、既に提
案されている（ＮＨ4 ）2 Ｓまたは（ＮＨ4 ）2 ＳX等
による表面処理を行う。表面処理後、半導体ウェハ上に
絶縁膜を堆積させるが、その際に、絶縁膜の堆積開始と
同時に界面準位密度を減少させる元素を絶縁膜中にドー
ピングする。このように絶縁膜内のドーピング処理をす
ると、絶縁膜を形成するときに、ドーピング元素が界面
の半導体元素を、表面処理に引続きターミネイトして酸
化を不活性化する。これにより界面準位密度が減少す
る。[Action] The semiconductor wafer surface to clean, the surface treatment by the previously proposed (NH 4) 2 S or (NH 4) 2 S X, and the like. After the surface treatment, an insulating film is deposited on the semiconductor wafer. At this time, an element that reduces the interface state density is doped into the insulating film simultaneously with the start of the deposition of the insulating film. By performing the doping treatment in the insulating film in this manner, when forming the insulating film, the doping element terminates the semiconductor element at the interface following the surface treatment, thereby inactivating the oxidation. This reduces the interface state density.
【００１５】[0015]
【実施例】以下、ＧａＡｓウェハに適用した本発明の実
施例を図面を用いて説明する。Embodiments of the present invention applied to a GaAs wafer will be described below with reference to the drawings.
【００１６】図６に示すように、本実施例の絶縁膜付き
半導体ウェハは、半導体基板１上に堆積させた絶縁膜２
中に界面準位密度を減少させる元素が含有されているも
のである。As shown in FIG. 6, a semiconductor wafer provided with an insulating film according to the present embodiment comprises an insulating film 2 deposited on a semiconductor substrate 1.
An element that reduces the interface state density is contained therein.
【００１７】半導体基板として、Ｓｉドープ（ｎ型；５
×１０16ｃｍ~3）ＧａＡｓウェハを用いた。前処理とし
てＨ2 ＳＯ4 ：Ｈ2 Ｏ2 ：Ｈ2 Ｏ＝５：１：１液で、６
０℃，１分間エッチングした後、さらに表面を清浄にす
るため（ＮＨ4 ）2 Ｓ液に、６０℃，１０分間浸漬し
た。余分なＳ層を除去するために１０~5torrの真空中に
１０時間放置し、その後、絶縁膜を形成するためにプラ
ズマＣＶＤ装置（アルバック社製ＣＰＤ−１１１４）に
セットした。装置内の真空度は２×１０~5torr、設定温
度は３５０℃である。As a semiconductor substrate, Si-doped (n-type; 5
× 10 16 cm ~ 3 ) A GaAs wafer was used. As a pretreatment, a solution of H 2 SO 4 : H 2 O 2 : H 2 O = 5: 1: 1 and 6
After etching at 0 ° C. for 1 minute, the substrate was immersed in a (NH 4 ) 2 S solution at 60 ° C. for 10 minutes to further clean the surface. It was left in a vacuum of 10 to 5 torr for 10 hours to remove an excess S layer, and then set in a plasma CVD apparatus (CLP-1114 manufactured by ULVAC, Inc.) to form an insulating film. The degree of vacuum in the apparatus is 2 × 10 to 5 torr, and the set temperature is 350 ° C.
【００１８】ＧａＡｓ−ＳｉＯ2 界面に、界面準位密度
を減少させるＳをドーピングするために、図１に示すよ
うなガス流量プログラムで、ＳｉＨ4 、Ｎ2 Ｏ、Ｈ2 Ｓ
ガスを流し、絶縁膜（膜厚約１０００Å）を形成した。
ＳｉＨ4 、Ｎ2 Ｏは絶縁膜用の原料であり、Ｈ2 ＳはＳ
原料である。Ｈ2 Ｓガスは絶縁膜形成開始と同時にステ
ップ状に立上がらせ、極く短時間供給した後その供給を
ステップ状に停止する。この時供給されるＨ2 Ｓガスの
供給量はＮ2 Ｏと等量である。In order to dope the GaAs-SiO 2 interface with S, which reduces the interface state density, SiH 4 , N 2 O, H 2 S are applied by a gas flow program as shown in FIG.
A gas was flowed to form an insulating film (thickness: about 1000 °).
SiH 4 and N 2 O are raw materials for an insulating film, and H 2 S is S
Raw material. The H 2 S gas rises stepwise at the same time as the start of the formation of the insulating film, and is supplied for a very short time and then stopped in a stepwise manner. The supply amount of the H 2 S gas supplied at this time is equal to N 2 O.
【００１９】さて、Ｓのドーピング状況を調べるために
ＳＩＭＳ(Secondary Ion Mass Spectrometry）により絶
縁膜中の不純物の深さ方向分布分析を行なった。その結
果を図２に示す。約２０Åの非常に薄い厚さに渡ってＳ
とＯ原子がほぼ等量のＳｉＯ2 −ＳｉＳ2 層が存在する
ことがわかった。In order to examine the doping state of S, the distribution of impurities in the insulating film in the depth direction was analyzed by SIMS (Secondary Ion Mass Spectrometry). The result is shown in FIG. S over a very thin thickness of about 20 mm
It was found that there was an SiO 2 —SiS 2 layer in which O atoms and O atoms were almost equal.
【００２０】このサンプルのＭＩＳ界面準位密度を測定
するためｑｕａｓｉ−ｓｔａｔｉｃＣＶ測定（準静的容
量電圧測定）を行なった。その結果を図３に示す。図か
らわかるように、反転領域（ｐ層）が明確に現れてお
り、良好なＭＩＳ界面が得られていることがわかる。理
想曲線とのずれから界面準位密度を見積もると５×１０
10ｃｍ~2程度と、ＳｉウェハのＭＯＳ界面準位密度と同
程度であった。A quasi-static CV measurement (quasi-static capacitance voltage measurement) was performed to measure the MIS interface state density of this sample. The result is shown in FIG. As can be seen from the figure, the inversion region (p layer) clearly appears, indicating that a good MIS interface has been obtained. When the interface state density is estimated from the deviation from the ideal curve, 5 × 10
It was about 10 cm 2 , which was about the same as the MOS interface state density of the Si wafer.
【００２１】ところで、この後、ＭＩＳＦＥＴを作成す
るプロセスでは最高４００℃前後の熱処理が行なわれ
る。従って、この熱処理を加えてもＭＩＳ界面の特性が
変らないことが要求される。そこで前記サンプルに４５
０℃、３０分の熱処理を加えた（Ａｒガス雰囲気）。こ
の熱処理後の絶縁膜中の不純物の深さ方向分布のＳＩＭ
Ｓ分析結果は、図２とほぼ同様で、Ｓの熱拡散がほとん
どないことが確認できた。またｑｕａｓｉ−ｓｔａｔｉ
ｃ ＣＶ測定結果も、図３と同様で界面準位密度は５×
１０10ｃｍ~2程度と変らなかった。After that, a heat treatment at a maximum of about 400 ° C. is performed in the process of forming the MISFET. Therefore, it is required that the characteristics of the MIS interface do not change even if this heat treatment is applied. Therefore, 45
Heat treatment was performed at 0 ° C. for 30 minutes (Ar gas atmosphere). SIM of depth distribution of impurities in insulating film after heat treatment
The S analysis result was almost the same as FIG. 2, and it was confirmed that there was almost no thermal diffusion of S. Also, quasi-stati
c The CV measurement results are the same as in FIG.
It was about 10 10 cm ~ 2, which was the same.
【００２２】このように本実施例によれば、絶縁膜を形
成するときに、ＧａＡｓウェハの表面処理に加えて、絶
縁膜中にＳをドープするという絶縁膜内処理を施すこと
により、界面準位の発生を有効に抑えるようにしたの
で、既に提案されている方法で最初のＧａＡｓ表面の表
面準位を少なくすれば、極めて安定した絶縁膜を堆積す
ることができる。従って、絶縁膜を半導体基板上に形成
するのによく使用されるプラズマＣＶＤ装置を用いて
も、良好な絶縁物−半導体界面が得られる。その結果、
本絶縁膜付きＧａＡｓウェハを用いると、良好な電気的
特性を示すＭＩＳＦＥＴの作成が可能となる。As described above, according to the present embodiment, when forming the insulating film, in addition to the surface treatment of the GaAs wafer, the surface of the insulating film is doped with S to perform the treatment in the insulating film. Since the generation of potential is effectively suppressed, an extremely stable insulating film can be deposited by reducing the surface level of the first GaAs surface by the method already proposed. Therefore, a favorable insulator-semiconductor interface can be obtained even by using a plasma CVD apparatus which is often used for forming an insulating film on a semiconductor substrate. as a result,
The use of the GaAs wafer with an insulating film makes it possible to produce a MISFET exhibiting good electrical characteristics.
【００２３】なお、上記実施例の変形例としては、図
４、図５に示すようなプログラムによるドーピング方法
が考えられる。図４に示すガス流量プログラムは、Ｈ2
Ｓガスをステップ状に供給するではなく、供給を徐々に
減少させていき最後にゼロにするものである。図５に示
すプログラムは絶縁膜形成中、コンスタントに供給を継
続するものである。但し、図４、図５に示すような方法
だと、Ｓ供給の継続により絶縁膜の絶縁性及び誘電率の
変化が考えられるため、場合によっては絶縁膜としては
適さない可能性がある。As a modification of the above embodiment, a doping method using a program as shown in FIGS. 4 and 5 can be considered. Gas flow program shown in FIG. 4, H 2
Rather than supplying the S gas stepwise, the supply is gradually reduced to zero at the end. The program shown in FIG. 5 is one in which the supply is constantly continued during the formation of the insulating film. However, according to the methods shown in FIGS. 4 and 5, the insulating property and the dielectric constant of the insulating film may change due to the continuation of the S supply, and thus may not be suitable as the insulating film in some cases.
【００２４】そこで、本発明では、図１、図２で説明し
た通り、界面準位密度を減少させる元素を絶縁膜の堆積
開始から所定時間だけドーピングして、絶縁膜のうち半
導体ウェハとの界面近傍の領域にのみ界面準位密度を減
少させる元素がドーピングされている絶縁膜を形成する
ようにしたのである。 Therefore, the present invention will be described with reference to FIGS.
As described above, an element that reduces the interface state density
Doping for a predetermined time from the start, half of the insulating film
Reduce interface state density only in the area near the interface with the conductor wafer
Form an insulating film doped with a reducing element
I did it.
【００２５】[0025]
【発明の効果】本発明の絶縁膜付き半導体ウェハによれ
ば、ＧａＡｓからなる半導体ウェハ上に堆積させた絶縁
膜のうち、半導体ウェハとの界面近傍の領域にのみ、Ｓ
またはＳｅからなる界面準位密度を減少させる元素がド
ーピングされているので、絶縁膜としての絶縁性及び誘
電体の変化を抑止しながら界面準位密度を少なくでき、
このウェハを用いることにより安定したＭＩＳＦＥＴを
作ることが可能となる。According to the semiconductor wafer with the insulating film of the present invention, the insulating film deposited on the semiconductor wafer made of GaAs can be used.
Only in the region of the film near the interface with the semiconductor wafer, S
Alternatively, an element made of Se that reduces the interface state density is doped.
The insulating properties of the insulating film
The interface state density can be reduced while suppressing the change of the conductor,
By using this wafer, a stable MISFET can be manufactured.
【００２６】また、本発明の絶縁膜付き半導体ウェハの
製造方法によれば、ＧａＡｓからなる半導体ウェハ上に
絶縁膜を堆積させる際に、ＳまたはＳｅからなる界面準
位密度を減少させる元素を絶縁膜の堆積開始から所定時
間だけドーピングして、絶縁膜のうち半導体ウェハとの
界面近傍の領域にのみ界面準位密度を減少させる元素が
ドーピングされている絶縁膜を形成することにより、絶
縁膜としての絶縁性及び誘電体の変化が抑止され、かつ
界面準位密度が少ない良好な絶縁物−半導体界面を有す
るＭＩＳＦＥＴ用ウェハを、安定かつ簡単に作成するこ
とができる。The semiconductor wafer with an insulating film of the present invention
According to the manufacturing method, on a semiconductor wafer made of GaAs,
When depositing an insulating film, an interface state composed of S or Se
At the specified time from the start of insulating film deposition
Doping only during the insulation film
Elements that reduce the interface state density only in the region near the interface
By forming a doped insulating film,
Insulation and dielectric changes as an edge film are suppressed, and
Good interface-semiconductor interface with low interface state density
MISFET wafer can be stably and easily formed.
【図１】本実施例による絶縁膜形成時のガス流量プログ
ラム図。FIG. 1 is a gas flow program diagram when an insulating film is formed according to an embodiment.
【図２】本実施例による絶縁膜−ＧａＡｓ界面部の不純
物深さ方向分布図。FIG. 2 is an impurity depth distribution diagram of an insulating film-GaAs interface according to the present embodiment.
【図３】本実施例によるＭＩＳダイオードのｑｕａｓｉ
−ｓｔａｔｉｃ ＣＶ測定結果を示す容量特性図。FIG. 3 is a quasi view of the MIS diode according to the present embodiment.
FIG. 4 is a capacitance characteristic diagram showing a static CV measurement result.
【図４】他の実施例による絶縁膜形成時のガス流量プロ
グラム図。FIG. 4 is a gas flow program diagram at the time of forming an insulating film according to another embodiment.
【図５】更に他の実施例による絶縁膜形成時のガス流量
プログラム図。FIG. 5 is a gas flow program diagram when forming an insulating film according to still another embodiment.
【図６】本実施例による絶縁膜付き半導体ウェハの断面
図。FIG. 6 is a sectional view of a semiconductor wafer with an insulating film according to the present embodiment.
１ 絶縁膜 ２ 半導体基板 DESCRIPTION OF SYMBOLS 1 Insulating film 2 Semiconductor substrate
フロントページの続き (56)参考文献 特開 昭57−39582（ＪＰ，Ａ) 特開 平２−39534（ＪＰ，Ａ) 特開 昭58−141576（ＪＰ，Ａ) 特開 平４−177765（ＪＰ，Ａ) 特開 平４−56140（ＪＰ，Ａ)Continuation of the front page (56) References JP-A-57-39582 (JP, A) JP-A-2-39534 (JP, A) JP-A-58-141576 (JP, A) JP-A-4-177765 (JP) , A) JP-A-4-56140 (JP, A)
Claims (4)
せた絶縁膜中に、界面準位密度を減少させる元素が含有
されている絶縁膜付き半導体ウェハにおいて、前記界面
準位密度を減少させる元素はＳまたはＳｅであり、前記
絶縁膜のうち前記半導体ウェハとの界面近傍の領域にの
みドーピングされていることを特徴とする絶縁膜付き半
導体ウェハ。To 1. A dielectric film deposited on a semiconductor wafer made of GaAs, the insulating film with the semiconductor wafer to which an element to reduce the interface state density is contained, the interface
The element that reduces the level density is S or Se,
In the region of the insulating film near the interface with the semiconductor wafer,
A semiconductor wafer with an insulating film, which is doped only .
ピングされた領域は、前記絶縁膜を堆積する際に形成さ
れたものである請求項１に記載の絶縁膜付き半導体ウェ
ハ。 2. The method according to claim 1, wherein the element for reducing the interface state density is a dopant.
The pinged region is formed when depositing the insulating film.
2. The semiconductor wafer with an insulating film according to claim 1, wherein
C.
を堆積させる際に、該絶縁膜中に界面準位密度を減少さ
せる元素をドーピングする絶縁膜付き半導体ウェハの製
造方法において、前記界面準位密度を減少させる元素は
ＳまたはＳｅであり、該界面準位密度を減少させる元素
を絶縁膜の堆積開始から所定時間だけドーピングして、
前記絶縁膜のうち前記半導体ウェハとの界面近傍の領域
にのみ前記界面準位密度を減少させる元素がドーピング
されている絶縁膜を形成することを特徴とする絶縁膜付
き半導体ウェハの製造方法。3. An insulating film on a GaAs semiconductor wafer.
Reduces the interface state density in the insulating film.
Of semiconductor wafer with insulating film to dope elements
In the fabrication method, the element for reducing the interface state density is
An element which is S or Se and reduces the interface state density
Doping for a predetermined time from the start of the deposition of the insulating film,
A region of the insulating film near an interface with the semiconductor wafer
Doping only with the element that reduces the interface state density
A method for manufacturing a semiconductor wafer with an insulating film, comprising forming an insulating film as described above.
ェハの表面を（ＮＨ 4 ） 2 Ｓまたは（ＮＨ 4 ） 2 Ｓ X で
表面処理する工程を有する請求項３に記載の絶縁膜付き
半導体ウェハの製造方法。 4. The semiconductor wafer according to claim 1, wherein said insulating film is deposited.
The surface of the E c (NH 4) 2 S or (NH 4) with 2 S X
The method for producing a semiconductor wafer with an insulating film according to claim 3, further comprising a step of performing a surface treatment .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019283A JP2780501B2 (en) | 1991-01-18 | 1991-01-18 | Semiconductor wafer with insulating film and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019283A JP2780501B2 (en) | 1991-01-18 | 1991-01-18 | Semiconductor wafer with insulating film and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04236424A JPH04236424A (en) | 1992-08-25 |
| JP2780501B2 true JP2780501B2 (en) | 1998-07-30 |
Family
ID=11995121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3019283A Expired - Lifetime JP2780501B2 (en) | 1991-01-18 | 1991-01-18 | Semiconductor wafer with insulating film and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780501B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260325A (en) * | 2008-03-26 | 2009-11-05 | Univ Of Tokyo | Semiconductor substrate, method for manufacturing semiconductor substrate and semiconductor device |
| JP2016207789A (en) * | 2015-04-20 | 2016-12-08 | 東京エレクトロン株式会社 | Passivation processing method, semiconductor structure forming method, and semiconductor structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5739582A (en) * | 1980-08-20 | 1982-03-04 | Sumitomo Electric Ind Ltd | Manufacture of inversion type insulated gate field effect transistor |
| JPS58141576A (en) * | 1982-02-17 | 1983-08-22 | Nec Corp | Semiconductor device |
| JPH0239534A (en) * | 1988-07-29 | 1990-02-08 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH0456140A (en) * | 1990-06-22 | 1992-02-24 | Hitachi Ltd | Compound semiconductor device and manufacture thereof |
| JP2903134B2 (en) * | 1990-11-10 | 1999-06-07 | 株式会社 半導体エネルギー研究所 | Semiconductor device |
-
1991
- 1991-01-18 JP JP3019283A patent/JP2780501B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04236424A (en) | 1992-08-25 |
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