JP2776149B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2776149B2 JP2776149B2 JP4154886A JP15488692A JP2776149B2 JP 2776149 B2 JP2776149 B2 JP 2776149B2 JP 4154886 A JP4154886 A JP 4154886A JP 15488692 A JP15488692 A JP 15488692A JP 2776149 B2 JP2776149 B2 JP 2776149B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- integrated circuit
- layer
- semiconductor substrate
- insulator layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に係わ
り、超高速度と超高集積度を両立させた半導体集積回路
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having both high speed and high integration.
【０００２】[0002]
【従来の技術】半導体集積回路、特にＣＭＯＳ−ＬＳＩ
は、高速化と集積度の向上が続いており、今後もこれら
性能の一層の向上が要求されている。2. Description of the Related Art Semiconductor integrated circuits, particularly CMOS-LSI
As the speed and the degree of integration continue to increase, further improvements in these performances are required in the future.
【０００３】今までの性能向上は主にスケーリングで達
成されてきた。サブミクロンまでは一定の電源電圧のも
とにスケーリングが成されてきたために、動作速度の大
幅な向上を達成することができた。しかしサブミクロン
以降では電源電圧も低下せざるおえないために、単にス
ケーリングだけでは動作速度の向上傾向に陰りが見えて
きている。Up to now, performance improvement has been achieved mainly by scaling. Sub-micron scaling has been achieved under constant supply voltages, which has allowed a significant increase in operating speed. However, since the power supply voltage has to be reduced after the submicron, the trend of improvement in the operation speed has been declining by simply scaling.
【０００４】そのために、これらの壁を乗り越えようと
新しい技術の開発が進められている。絶縁体層上に半導
体素子を形成した半導体層を設けた、いわゆるＳＯＩ構
造もその一つである。[0004] For this purpose, new technologies are being developed to overcome these barriers. A so-called SOI structure in which a semiconductor layer in which a semiconductor element is formed over an insulator layer is one of them.
【０００５】図３は従来技術のＳＯＩ構造の半導体集積
回路の一例を示す断面図である。シリコン半導体基板１
０上に絶縁体層１１が設けられ、さらにその上にシリコ
ン半導体層１２が設けられている。このシリコン半導体
層の一部にソース，ドレイン領域となる高濃度拡散層１
３が形成され、ゲート絶縁膜２０上のゲート電極１４と
共にＭＯＳＦＥＴを構成している。FIG. 3 is a sectional view showing an example of a conventional semiconductor integrated circuit having an SOI structure. Silicon semiconductor substrate 1
0, an insulator layer 11 is provided thereon, and a silicon semiconductor layer 12 is further provided thereon. A high concentration diffusion layer 1 serving as a source / drain region is formed in a part of the silicon semiconductor layer.
3 are formed, and constitute a MOSFET together with the gate electrode 14 on the gate insulating film 20.
【０００６】ＭＯＳＦＥＴ全体は絶縁膜としてのシリコ
ン酸化膜１５によって覆われ、コンタクト孔２１の部分
の酸化膜が除去されてＷ（タングステン）等の電極導体
膜２０が埋め込まれ、ＡＬ（アルミニウム）配線膜１７
で相互配線がなされる。ＳＯＩ構造は、絶縁体層上のシ
リコン層を種々の方法で単結晶化させたり、シリコン基
板中に酸素原子をイオン注入して内部に絶縁体層として
の酸化膜層を形成したりして得られる。The entire MOSFET is covered with a silicon oxide film 15 as an insulating film, the oxide film in the contact hole 21 is removed, and an electrode conductor film 20 such as W (tungsten) is buried, and an AL (aluminum) wiring film is formed. 17
The interconnection is made. The SOI structure is obtained by monocrystallizing a silicon layer on an insulator layer by various methods, or by ion-implanting oxygen atoms into a silicon substrate to form an oxide film layer as an insulator layer therein. Can be
【０００７】ＳＯＩ構造のＭＯＳＦＥＴでは、拡散層の
容量が極めて小さくでき、またシリコン層の厚さを百ナ
ノメートル以下にした場合にオン電流が増大することが
報告され、注目を集めている。またＳＯＩ構造では、個
々のトランジスタを形成する活性領域が絶縁体で完全に
分離されているため、通常のバルクＣＭＯＳのようなウ
ェルは必要がない。そのため、ＮチャネルＭＯＳＦＥＴ
とＰチャネルＭＯＳＦＥＴを非常に近く配置することが
でき、集積度の点でも有利である。In a MOSFET having an SOI structure, it has been reported that the capacity of the diffusion layer can be made extremely small, and that the on-current increases when the thickness of the silicon layer is reduced to 100 nm or less. Further, in the SOI structure, since the active regions forming the individual transistors are completely separated by an insulator, there is no need for a well as in a normal bulk CMOS. Therefore, N-channel MOSFET
And a P-channel MOSFET can be arranged very close, which is advantageous in terms of the degree of integration.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上述し
たＳＯＩ構造の集積回路においては、以下に示すような
問題点がある。However, the integrated circuit having the SOI structure has the following problems.
【０００９】集積回路では、特にトランジスタ領域で熱
を発生する。この発熱量は相当なもので、時には数十ワ
ットにも達する。そのため集積回路装置では、様々な放
熱の対策が施されているが、集積回路の温度は数十度、
時には百度近く上昇する。温度上昇は集積回路に多くの
弊害をもたらす。キャリアの移動度が低下するためにト
ランジスタのオン電流が低下し、メタル配線の抵抗成分
が増大するために配線遅延が増大する。ＭＯＳＦＥＴの
しきい値電圧が低下しオフ電流が増加するために待機時
の消費電力が増大する。また多くの点で信頼性が低下す
る。In an integrated circuit, heat is generated particularly in the transistor region. This calorific value is considerable, sometimes as high as tens of watts. Therefore, in the integrated circuit device, various measures for heat radiation are taken, but the temperature of the integrated circuit is several tens of degrees,
Sometimes it rises by nearly Baidu. Increased temperatures have many adverse effects on integrated circuits. The on-current of the transistor is reduced due to a decrease in carrier mobility, and the wiring delay is increased due to an increase in the resistance component of the metal wiring. Since the threshold voltage of the MOSFET decreases and the off-state current increases, power consumption during standby increases. Also, reliability is reduced in many respects.
【００１０】ＳＯＩ構造でない従来の集積回路では、ト
ランジスタ領域で発生した熱は主に半導体基板を通って
チップ裏面が接しているパッケージに逃げる。半導体基
板、例えばシリコンは非常に熱を伝えやすいため、発生
した熱は速やかにパッケージに逃げることができる。In a conventional integrated circuit having no SOI structure, heat generated in a transistor region escapes mainly through a semiconductor substrate to a package in which the back surface of a chip is in contact. Since a semiconductor substrate, for example, silicon is very easy to transmit heat, the generated heat can be quickly released to the package.
【００１１】しかし従来のＳＯＩ構造の集積回路では、
トランジスタ領域と半導体基板との間には厚い（例えば
数ミクロン）絶縁膜あるいは絶縁体層が存在する。絶縁
物質、例えばシリコン酸化物は熱を伝え難いため、発生
した熱は速やかにパッケージに逃げることができずに温
度上昇が激しくなる。However, in an integrated circuit having a conventional SOI structure,
A thick (eg, several microns) insulating film or insulator layer exists between the transistor region and the semiconductor substrate. Since an insulating material, for example, silicon oxide, is difficult to conduct heat, the generated heat cannot escape to the package quickly, and the temperature rises sharply.
【００１２】[0012]
【課題を解決するための手段】本発明の特徴は、半導体
基板上に設けられた絶縁体層と、前記絶縁体層上に設け
られ半導体素子を形成する半導体層と、前記半導体層上
に設けられた絶縁膜と、前記絶縁膜に形成されたコンタ
クト孔と、前記コンタクト孔に充填されて前記半導体層
に形成された前記半導体素子の所定部に接続する電極導
体膜とを有し、前記コンタクト孔が前記絶縁体層を貫通
して前記半導体基板の内部に入り込み、前記電極導体膜
の側面が前記絶縁体層と前記半導体基板に接し底面が前
記半導体基板に接している半導体集積回路において、前
記電極導体膜は前記半導体基板とショットキー接合を形
成している半導体集積回路にある。 The features of the present invention include an insulator layer provided on a semiconductor substrate, a semiconductor layer provided on the insulator layer to form a semiconductor element, and a semiconductor layer provided on the semiconductor layer. an insulating layer which is, possess a contact hole formed in the insulating film, and an electrode conductive film to be connected to a predetermined portion of the semiconductor device is filled is formed on the semiconductor layer in the contact hole, the contact Hole penetrates the insulator layer
And enters the inside of the semiconductor substrate, and the electrode conductor film
The side surface is in contact with the insulator layer and the semiconductor substrate, and the bottom surface is
In the semiconductor integrated circuit in contact with the serial semiconductor substrate, prior to
The electrode conductor film forms a Schottky junction with the semiconductor substrate.
In the semiconductor integrated circuit that forms.
【００１３】この場合、前記半導体基板は、たとえば不
純物濃度が１×１０17ｃｍ-3以下のＮ型シリコン基板で
あることが好ましい。In this case, the semiconductor substrate is, for example, an N-type silicon substrate having an impurity concentration of 1 × 10 17 cm −3 or less.
Preferably, there is .
【００１４】[0014]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１は本発明に関連する技術を説明するた
めの断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view for explaining a technique related to the present invention.
【００１５】シリコン半導体基板１０上に絶縁体層１１
が設けられ、さらにその上にシリコン半導体層１２が設
けられている。このシリコン半導体層の一部にソース，
ドレイン領域となる高濃度拡散層１３が形成され、ゲー
ト絶縁膜２０上のゲート電極１４と共に半導体素子であ
るＭＯＳＦＥＴを構成している。ＭＯＳＦＥＴ全体はシ
リコン酸化膜１５によって覆われ、コンタクト孔２２の
部分のシリコン酸化膜１５、高濃度拡散層１３及び絶縁
体層１１の一部が除去されてＷ（タングステン）等の電
極導体膜１６が埋め込まれてその側面と底面が絶縁体層
１１に接し、ＡＬ（アルミニウム）膜１７が電極導体膜
１６の上面に接続して相互配線がなされる。An insulator layer 11 is formed on a silicon semiconductor substrate 10.
And a silicon semiconductor layer 12 is further provided thereon. A source, a part of this silicon semiconductor layer
A high concentration diffusion layer 13 serving as a drain region is formed, and together with the gate electrode 14 on the gate insulating film 20, constitutes a MOSFET as a semiconductor element. The entire MOSFET is covered with a silicon oxide film 15, and a part of the silicon oxide film 15, the high concentration diffusion layer 13 and the insulator layer 11 at the contact hole 22 is removed to form an electrode conductor film 16 such as W (tungsten). It is buried and its side and bottom surfaces are in contact with the insulator layer 11, and the AL (aluminum) film 17 is connected to the upper surface of the electrode conductor film 16 to perform interconnection.
【００１６】ゲート長がハーフミクロン程度の素子に本
実施例を適用する場合、シリコン半導体層１２の厚さは
百ｎｍ以下が適切である。絶縁体層１１の厚さは、酸素
原子をシリコン基板１０にイオン注入して形成する場合
は、例えば２．０ミクロン程度である。コンタクト孔部
分の絶縁体層１１の残膜は薄いほど良いが、膜厚やエッ
チングのばらつきを考慮して０．５ミクロン程度に設定
するのが適切である。When the present embodiment is applied to an element having a gate length of about half a micron, the thickness of the silicon semiconductor layer 12 is suitably 100 nm or less. The thickness of the insulator layer 11 is, for example, about 2.0 μm when oxygen atoms are ion-implanted into the silicon substrate 10. The remaining film of the insulator layer 11 in the contact hole portion is preferably as thin as possible, but it is appropriate to set the thickness to about 0.5 μm in consideration of the film thickness and the variation in etching.
【００１７】図１のＳＯＩ構造の半導体集積回路では、
トランジスタ領域で発生した熱をコンタクト孔部分を介
して容易にシリコン基板に逃がすことができる。従来構
造と比較するとコンタクト孔下の絶縁体層の厚さは１／
４になるため、熱抵抗もほぼ１／４にすることができ
る。In the semiconductor integrated circuit having the SOI structure shown in FIG .
The heat generated in the transistor region can be easily released to the silicon substrate through the contact hole. Compared to the conventional structure, the thickness of the insulator layer below the contact hole is 1 /
4, the thermal resistance can also be reduced to approximately 1/4.
【００１８】図２は本発明の実施例を説明するための断
面図である。コンタクト孔２３は絶縁体層１１を突き抜
けてシリコン基板１０まで達しており電極導体膜１８の
側面が絶縁体層１１とシリコン基板１０に接し底面はシ
リコン基板１０に接している。シリコン基板として、例
えば不純物濃度が１×１０17ｃｍ-3以下のＮ型シリコン
を用いると、電極導体膜１８との間に良好なショットキ
ー接合を形成させることができる。そのため、シリコン
基板１０を集積回路内で使用する最高電位に設定してお
けば、導体膜１８とシリコン基板１０とを電気的に絶縁
状態にすることができる。なお、シリコン基板１０にＰ
型シリコンを用いる場合には、集積回路内で使用する最
低電位に設定する。FIG. 2 is a sectional view for explaining an embodiment of the present invention. The contact hole 23 penetrates through the insulator layer 11 and reaches the silicon substrate 10. The side surface of the electrode conductor film 18 contacts the insulator layer 11 and the silicon substrate 10, and the bottom surface contacts the silicon substrate 10. When N-type silicon having an impurity concentration of, for example, 1 × 10 17 cm −3 or less is used as the silicon substrate, a good Schottky junction with the electrode conductor film 18 can be formed. Therefore, if the silicon substrate 10 is set to the highest potential used in the integrated circuit, the conductive film 18 and the silicon substrate 10 can be electrically insulated. In addition, P
In the case of using the type silicon, it is set to the lowest potential used in the integrated circuit.
【００１９】一方で、電極導体膜１８とシリコン基板１
０とは直接接しているために熱抵抗を非常に低くするこ
とができる。ショットキー接合部分でリーク電流が多少
発生するが、特に低消費電力用途でなければ全く問題な
い。On the other hand, the electrode conductor film 18 and the silicon substrate 1
Since it is in direct contact with 0, the thermal resistance can be made very low. Although some leakage current occurs at the Schottky junction, there is no problem unless the power consumption is particularly low.
【００２０】Ｗ（タングステン）はシリコンと比較的反
応しやすいため、電極導体膜１８としてＷ（タングステ
ン）単層を用いず、間にＴｉ（チタン）やＴｉＮ（窒化
チタン）等を挟むことが好ましい。Since W (tungsten) relatively easily reacts with silicon, it is preferable that a single layer of W (tungsten) is not used as the electrode conductor film 18 and Ti (titanium), TiN (titanium nitride), or the like is interposed therebetween. .
【００２１】上記実施例のＭＯＳＦＥＴはＮチャネル型
でもＰチャネル型でもかまわない。また、半導体素子と
してＮＰＮ型やＰＮＰ型のバイポーラトランジスタ等の
能動素子あるいは抵抗等の受動素子を形成した場合につ
いても全く同様である。The MOSFET of the above embodiment may be an N-channel type or a P-channel type. The same applies to the case where an active element such as an NPN type or PNP type bipolar transistor or a passive element such as a resistor is formed as a semiconductor element.
【００２２】[0022]
【発明の効果】以上説明したように本発明は、トランジ
スタ領域で発生した熱をコンタクトを介して半導体基板
に容易に逃がすことができるため、ＳＯＩ構造でない従
来の集積回路とほぼ等しい熱抵抗が達成できる。As described above, according to the present invention, the heat generated in the transistor region can be easily dissipated to the semiconductor substrate through the contact, so that a thermal resistance almost equal to that of the conventional integrated circuit having no SOI structure is achieved. it can.
【図１】本発明に関連する技術を説明するための断面図
である。FIG. 1 is a cross-sectional view for explaining a technique related to the present invention.
【図２】本発明の実施例を説明するための断面図であ
る。FIG. 2 is a cross-sectional view for explaining an embodiment of the present invention.
【図３】従来のＳＯＩ構造の集積回路を説明するための
断面図である。FIG. 3 is a cross-sectional view illustrating a conventional integrated circuit having an SOI structure.
１０ シリコン基板 １１ 絶縁体層 １２ シリコン層 １３ 高濃度拡散層 １４ ゲート電極 １５ シリコン酸化膜 １６，１８，２０ 電極導体膜 １７ ＡＬ配線膜 ２０ ゲート絶縁膜 ２１，２２，２３ コンタクト孔 DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 Insulator layer 12 Silicon layer 13 High concentration diffusion layer 14 Gate electrode 15 Silicon oxide film 16, 18, 20 Electrode conductor film 17 AL wiring film 20 Gate insulating film 21, 22, 23 Contact hole
Claims (2)
前記絶縁体層上に設けられ半導体素子を形成する半導体
層と、前記半導体層上に設けられた絶縁膜と、前記絶縁
膜に形成されたコンタクト孔と、前記コンタクト孔に充
填されて前記半導体層に形成された前記半導体素子の所
定部に接続する電極導体膜とを有し、前記コンタクト孔
が前記絶縁体層を貫通して前記半導体基板の内部に入り
込み、前記電極導体膜の側面が前記絶縁体層と前記半導
体基板に接し底面が前記半導体基板に接している半導体
集積回路において、前記電極導体膜は前記半導体基板と
ショットキー接合を形成していることを特徴とする半導
体集積回路。An insulator layer provided on a semiconductor substrate,
A semiconductor layer provided on the insulator layer to form a semiconductor element; an insulating film provided on the semiconductor layer; a contact hole formed in the insulating film; and a semiconductor layer filled in the contact hole. to connect to a predetermined portion of the semiconductor element formed on possess an electrode conductive film, the contact hole
Penetrates through the insulator layer and enters the inside of the semiconductor substrate.
The side surface of the electrode conductor film is in contact with the insulator layer and the semiconductor layer.
In a semiconductor integrated circuit in which a bottom surface is in contact with a semiconductor substrate and a bottom surface is in contact with the semiconductor substrate, the electrode conductor film is in contact with the semiconductor substrate.
A semiconductor integrated circuit characterized by forming a Schottky junction .
17ｃｍ-3以下のＮ型シリコン基板であることを特徴とす
る請求項１に記載の半導体集積回路。 2. The semiconductor substrate according to claim 1, wherein said semiconductor substrate has an impurity concentration of 1.times.10.
2. The semiconductor integrated circuit according to claim 1 , wherein the semiconductor integrated circuit is an N-type silicon substrate of 17 cm -3 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4154886A JP2776149B2 (en) | 1992-06-15 | 1992-06-15 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4154886A JP2776149B2 (en) | 1992-06-15 | 1992-06-15 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05347412A JPH05347412A (en) | 1993-12-27 |
| JP2776149B2 true JP2776149B2 (en) | 1998-07-16 |
Family
ID=15594111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4154886A Expired - Lifetime JP2776149B2 (en) | 1992-06-15 | 1992-06-15 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2776149B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100253699B1 (en) * | 1996-06-29 | 2000-05-01 | 김영환 | Soi device and its manufacturing method |
| JP2001068647A (en) * | 1999-08-30 | 2001-03-16 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JP2002231721A (en) * | 2001-02-06 | 2002-08-16 | Mitsubishi Electric Corp | Semiconductor device |
| JP2003100749A (en) * | 2001-09-20 | 2003-04-04 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP2003188386A (en) * | 2001-12-20 | 2003-07-04 | Sony Corp | Semiconductor device and its fabricating method |
| JP4773697B2 (en) * | 2004-06-30 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | SOI substrate, method of manufacturing the same, and semiconductor device |
| KR100675275B1 (en) | 2004-12-16 | 2007-01-26 | 삼성전자주식회사 | Semiconductor device and pad arrangement method thereof |
| JP5512930B2 (en) * | 2007-03-26 | 2014-06-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP5512931B2 (en) * | 2007-03-26 | 2014-06-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP2013191639A (en) * | 2012-03-12 | 2013-09-26 | Nippon Hoso Kyokai <Nhk> | Laminated semiconductor device and manufacturing method of the same |
| JP7030666B2 (en) * | 2018-09-20 | 2022-03-07 | 株式会社東芝 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2616134B2 (en) * | 1990-04-19 | 1997-06-04 | 日本電気株式会社 | SOI transistor stacked semiconductor device and method of manufacturing the same |
| JPH04146673A (en) * | 1990-10-09 | 1992-05-20 | Seiko Epson Corp | Thin film semiconductor device |
| JPH0536624A (en) * | 1991-07-26 | 1993-02-12 | Fujitsu Ltd | Manufacture of semiconductor device and semiconductor device |
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1992
- 1992-06-15 JP JP4154886A patent/JP2776149B2/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| JPH05347412A (en) | 1993-12-27 |
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