JP2776058B2 - Sample hold circuit - Google Patents
Sample hold circuitInfo
- Publication number
- JP2776058B2 JP2776058B2 JP3138110A JP13811091A JP2776058B2 JP 2776058 B2 JP2776058 B2 JP 2776058B2 JP 3138110 A JP3138110 A JP 3138110A JP 13811091 A JP13811091 A JP 13811091A JP 2776058 B2 JP2776058 B2 JP 2776058B2
- Authority
- JP
- Japan
- Prior art keywords
- switch circuit
- operational amplifier
- input terminal
- turned
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はサンプルホールド回路に
関し、特に演算増幅器，容量素子，及びスイッチ回路で
構成されたサンプルホールド回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit composed of an operational amplifier, a capacitor, and a switch circuit.
【０００２】[0002]
【従来の技術】サンプルホールド回路はＡ−Ｄ変換回路
等の電子回路に広く用いられ、特に計測器においてはそ
の精度と速度の向上がますます望まれている。2. Description of the Related Art Sampling and holding circuits are widely used in electronic circuits such as A / D conversion circuits, and particularly in measuring instruments, their accuracy and speed are increasingly desired.
【０００３】従来のサンプルホールド回路として、特開
平０１−０２３２３６号公報に示された例を図２に示
す。FIG. 2 shows an example of a conventional sample-hold circuit disclosed in Japanese Patent Application Laid-Open No. 01-0223636.
【０００４】このサンプルホールド回路は、第１の入力
端（−）及び第２の入力端（＋）を備えた演算増幅器１
と、一端に入力信号Ｖｉを入力し制御信号Ｓ１により所
定のタイミングでオン，オフしてオンのとき入力信号Ｖ
ｉを他端へ伝達する第１のスイッチ回路ＳＷ１と、この
第１のスイッチ回路ＳＷ１の他端と演算増幅器１の第１
の入力端（−）との間に接続された第１の容量素子Ｃ１
と、一端に基準電圧Ｖｒを入力し他端を演算増幅器１の
第２の入力端（＋）に接続し制御信号Ｓ２により所定の
タイミングでオン，オフしてオンのとき基準電圧Ｖｒを
演算増幅器１の第２の入力端（＋）へ伝達する第２のス
イッチ回路ＳＷ２と、演算増幅器１の第２の入力端
（＋）と基準電位点（接地電位点）との間に接続された
第２の容量素子Ｃ２と、演算増幅器１の出力端と第１の
スイッチ回路ＳＷ１の他端との間に接続され制御信号Ｓ
３により所定のタイミングでオン，オフする第３のスイ
ッチ回路ＳＷ３と、演算増幅器１の出力端と第１の入力
端との間に接続され制御信号Ｓ４により所定のタイミン
グでオン，オフする第４のスイッチ回路４とを有する構
成となっている。This sample and hold circuit comprises an operational amplifier 1 having a first input terminal (-) and a second input terminal (+).
The input signal Vi is input to one end and turned on and off at a predetermined timing by the control signal S1.
i to the other end of the first switch circuit SW1 and the other end of the first switch circuit SW1 and the first
Capacitive element C1 connected between the input terminal (−)
The reference voltage Vr is input to one end, the other end is connected to the second input terminal (+) of the operational amplifier 1, and is turned on and off at a predetermined timing by the control signal S2. A second switch circuit SW2 for transmitting the signal to the second input terminal (+) of the first operational amplifier 1; and a second switch circuit SW2 connected between the second input terminal (+) of the operational amplifier 1 and the reference potential point (ground potential point). And a control signal S connected between the output terminal of the operational amplifier 1 and the other end of the first switch circuit SW1.
3, a third switch circuit SW3 that is turned on and off at a predetermined timing, and a fourth switch circuit that is connected between the output terminal and the first input terminal of the operational amplifier 1 and that is turned on and off at a predetermined timing by a control signal S4. And the switch circuit 4 of FIG.
【０００５】次にこの回路の動作について説明する。Next, the operation of this circuit will be described.
【０００６】まず、サンプル期間では、スイッチ回路Ｓ
Ｗ１，ＳＷ２，ＳＷ４がオンになっており、入力信号Ｖ
ｉのレベルに比例した電荷が容量素子Ｃ１に充電され
る。このとき、基準電圧Ｖｒが演算増幅器１の入力端
（＋）に印加されているので、演算増幅器の仮想接地の
考え方により、演算増幅器１の出力端及び入力端（−）
の電位は基準電圧Ｖｒになっている。First, in the sample period, the switch circuit S
W1, SW2, and SW4 are on, and the input signal V
The charge proportional to the level of i is charged in the capacitor C1. At this time, since the reference voltage Vr is applied to the input terminal (+) of the operational amplifier 1, the output terminal and the input terminal (-) of the operational amplifier 1 are considered based on the concept of virtual grounding of the operational amplifier.
Is the reference voltage Vr.
【０００７】次に、スイッチ回路ＳＷ２，ＳＷ４がオフ
となり、容量素子Ｃ１，Ｃ２に蓄積された電荷を保持
し、続いてスイッチ回路ＳＷ１をオフ、スイッチ回路Ｓ
Ｗ３をオンにして、演算増幅器１の出力信号Ｖｏのレベ
ルを、サンプリングした入力信号Ｖｉのレベルに等しく
する。これがホールド期間である。Next, the switch circuits SW2 and SW4 are turned off to hold the electric charges accumulated in the capacitance elements C1 and C2. Subsequently, the switch circuit SW1 is turned off and the switch circuit S
By turning on W3, the level of the output signal Vo of the operational amplifier 1 is made equal to the level of the sampled input signal Vi. This is the hold period.
【０００８】[0008]
【発明が解決しようとする課題】上述した従来のサンプ
ルホールド回路では、演算増幅器１の出力端の電位がサ
ンプル期間では基準電圧Ｖｒに、またスイッチ回路ＳＷ
１と容量素子Ｃ１との接続点の電圧は入力電圧Ｖｉにな
っており、スイッチ回路ＳＷ２，ＳＷ４がオフになり続
いてスイッチ回路ＳＷ１がオフ、スイッチ回路ＳＷ３が
オンになってホールド期間に移るとき、スイッチ回路Ｓ
Ｗ３の両端に電位差が生じているのでスイッチ回路ＳＷ
３に電流が流れる。この電流は過渡的に容量素子Ｃ１上
の電荷量を変化させ、演算増幅器１の入力端（−）の電
荷量、さらには電位も変化させる。これによって出力信
号Ｖｏの電位がさらに変化する。従ってホールド期間に
なったときに出力信号Ｖｏの電位が静定するのに時間が
かかるという欠点があった。In the above-mentioned conventional sample and hold circuit, the potential at the output terminal of the operational amplifier 1 is set to the reference voltage Vr during the sampling period, and the switch circuit SW is turned on.
When the voltage at the connection point between the capacitor 1 and the capacitor C1 is the input voltage Vi, the switch circuits SW2 and SW4 are turned off, and then the switch circuit SW1 is turned off and the switch circuit SW3 is turned on to shift to the hold period. , Switch circuit S
Since there is a potential difference between both ends of W3, the switch circuit SW
Current flows through 3. This current transiently changes the amount of charge on the capacitive element C1, and also changes the amount of charge at the input terminal (-) of the operational amplifier 1 and further the potential. This further changes the potential of the output signal Vo. Therefore, there is a disadvantage that it takes time for the potential of the output signal Vo to settle when the hold period is reached.
【０００９】本発明の目的は、ホールド期間になったと
きの静定するまでの時間を短かくした高速なサンプルホ
ールド回路を提供することである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed sample-and-hold circuit in which the time required to settle when a hold period is reached is shortened.
【００１０】[0010]
【課題を解決するための手段】本発明のサンプルホール
ド回路は、第１及び第２の入力端を備えた演算増幅器
と、―端に入力信号を入力し所定の夕イミングでオン，
オフしてオンのとき前記入力信号を他端へ伝達する第１
のスイッチ回路と、この第１のスイッチ回路の他端と前
記演算増幅器の第１の入力端との間に接続された第１の
容量素子と、―端に基準電圧を入力し他端を前記演算増
幅器の第２の入力端に接続し所定のタイミングでオン，
オフしてオンのとき前記基準電圧を前記演算増幅器の第
２の入力端へ伝達する第２のスイッチ回路と、前記演算
増幅器の第２の入力端と基準電位点との間に接続された
第２の容量素子と、前記演算増幅器の出力端と前記第１
のスイッチ回路の他端との間に接続され所定のタイミン
グでオン，オフする第３のスイッチ回路と、前記演算増
幅器の出力端と第１の入力端との間に接続され所定のタ
イミングでオン，オフする第４のスイッチ回路とを有す
るサンプルホールド回路において、前記第３のスイッチ
回路と並列に第３の容量素子を接続して構成される。According to the present invention, there is provided a sample and hold circuit comprising an operational amplifier having first and second input terminals, and an input signal input to a negative terminal to turn on and off at a predetermined time.
When on off first transmitting the input signal to another end 1
The other end receives a reference voltage on the edge - and switch circuit, a first capacitive element connected between the first input terminal of the other end of the operational amplifier of the first switch circuit, Connected to the second input terminal of the operational amplifier and turned on at a predetermined timing;
A second switch circuit for transmitting the reference voltage to a second input terminal of the operational amplifier when turned off and on; a second switch circuit connected between the second input terminal of the operational amplifier and a reference potential point; 2 capacitive element, the output terminal of the operational amplifier and the first
A third switch circuit connected between the other end of the switch circuit and turned on and off at a predetermined timing; and a third switch circuit connected between the output terminal and the first input terminal of the operational amplifier and turned on at a predetermined timing. , And a fourth switch circuit for turning off, a third capacitance element connected in parallel with the third switch circuit.
【００１１】[0011]
【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【００１２】図１は本発明の一実施例を示す回路図であ
る。FIG. 1 is a circuit diagram showing one embodiment of the present invention.
【００１３】この実施例が図２に示された従来のサンプ
ルホールド回路と相違する点は、第３のスイッチ回路Ｓ
Ｗ３と並列に第３の容量素子Ｃ３を設けた点である。This embodiment is different from the conventional sample and hold circuit shown in FIG. 2 in that the third switch circuit S
The point is that a third capacitor C3 is provided in parallel with W3.
【００１４】次にこの実施例の動作について説明する。Next, the operation of this embodiment will be described.
【００１５】このサンプルホールド回路は、前述したよ
うにスイッチ回路ＳＷ１，ＳＷ２，ＳＷ４がオンのとき
サンプル期間であり、このとき容量素子Ｃ１上に入力信
号Ｖｉの電圧に比例した電荷を充電することで入力信号
Ｖｉのサンプリングを行なう。As described above, this sample and hold circuit is a sampling period when the switch circuits SW1, SW2, and SW4 are turned on. At this time, by charging the capacitor C1 with electric charge proportional to the voltage of the input signal Vi. The input signal Vi is sampled.
【００１６】演算増幅器１の入力端（＋）には基準電圧
Ｖｒが印加されているので、よく知られた演算増幅器の
仮想接地の考え方により、入力端（−）及び出力端の電
圧も基準電圧Ｖｒと等しくなっている。Since the reference voltage Vr is applied to the input terminal (+) of the operational amplifier 1, the voltage at the input terminal (-) and the voltage at the output terminal are also changed to the reference voltage according to the well-known concept of virtual grounding of the operational amplifier. Vr.
【００１７】スイッチ回路ＳＷ２，ＳＷ４がオフになる
ことで容量素子Ｃ１，Ｃ２の電荷は保持される。スイッ
チ回路ＳＷ１がオフになってスイッチ回路ＳＷ３がオン
になることでこのサンプルホールド回路はホールド期間
となり、出力端はサンプリングした入力信号Ｖｉの電圧
と等しい電圧の出力信号Ｖｏを出力する。When the switch circuits SW2 and SW4 are turned off, the charges of the capacitance elements C1 and C2 are held. When the switch circuit SW1 is turned off and the switch circuit SW3 is turned on, the sample hold circuit enters a hold period, and the output terminal outputs an output signal Vo having a voltage equal to the voltage of the sampled input signal Vi.
【００１８】サンプル期間からホールド期間に移行する
とき、スイッチ回路ＳＷ３の両端に電位差が生じている
のでスイッチ回路ＳＷ３に電流が流れる。しかし、従来
技術のサンプルホールド回路と異なり本サンプルホール
ド回路では、サンプル期間で容量素子Ｃ３も入力信号Ｖ
ｉ電圧で充電されており、サンプル期間からホールド期
間に移行するときに容量素子Ｃ３上の電荷を放電する。
従って容量素子Ｃ１上の電荷量の変化は従来のサンプル
ホールド回路に比べて小さくなり、演算増幅器１の入力
端（−）の電荷量の変化、さらには入力端（−）の電位
変化も小さくなる。これによって出力信号Ｖｏの電圧の
静定時間は短かくなり動作が速くなる。When a transition is made from the sample period to the hold period, a current flows through the switch circuit SW3 because a potential difference occurs at both ends of the switch circuit SW3. However, unlike the conventional sample-hold circuit, in the present sample-hold circuit, the capacitance element C3 also receives the input signal V during the sampling period.
It is charged with the i voltage, and discharges the charge on the capacitor C3 when shifting from the sample period to the hold period.
Therefore, the change in the amount of charge on the capacitive element C1 is smaller than that in the conventional sample and hold circuit, and the change in the amount of charge at the input terminal (-) of the operational amplifier 1 and the change in the potential at the input terminal (-) are also smaller. . As a result, the settling time of the voltage of the output signal Vo is shortened, and the operation is accelerated.
【００１９】[0019]
【発明の効果】以上説明したように本発明は、第３のス
イッチ回路と並列に容量素子を設けた構成とすることに
より、第１の容量素子上の電荷量の変化が小さくなるの
で、演算増幅器の第１の入力端の電荷量の変化が小さく
なり、従って出力信号の静定時間が短縮され、動作速度
を向上させることができる効果がある。As described above, according to the present invention, the change in the amount of charge on the first capacitor is reduced by providing the capacitor in parallel with the third switch circuit. The change in the amount of charge at the first input terminal of the amplifier is reduced, so that the stabilization time of the output signal is shortened, and the operation speed can be improved.
【図１】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.
【図２】従来のサンプルホールド回路の一例を示す回路
図である。FIG. 2 is a circuit diagram illustrating an example of a conventional sample and hold circuit.
１ 演算増幅器 Ｃ１〜Ｃ３ 容量素子 ＳＷ１〜ＳＷ４ スイッチ回路 1 operational amplifier C1-C3 capacitive element SW1-SW4 switch circuit
Claims (1)
器と、―端に入力信号を入力し所定の夕イミングでオ
ン，オフしてオンのとき前記入力信号を他端へ伝達する
第１のスイッチ回路と、この第１のスイッチ回路の他端
と前記演算増幅器の第１の入力端との間に接続された第
１の容量素子と、―端に基準電圧を入力し他端を前記演
算増幅器の第２の入力端に接続し所定のタイミングでオ
ン，オフしてオンのとき前記基準電圧を前記演算増幅器
の第２の入力端へ伝達する第２のスイッチ回路と、前記
演算増幅器の第２の入力端と基準電位点との間に接続さ
れた第２の容量素子と、前記演算増幅器の出力端と前記
第１のスイッチ回路の他端との間に接続され所定のタイ
ミングでオン，オフする第３のスイッチ回路と、前記演
算増幅器の出力端と第１の入力端との間に接続され所定
のタイミングでオン，オフする第４のスイッチ回路とを
有するサンプルホールド回路において、前記第３のスイ
ッチ回路と並列に第３の容量素子を接続したことを特徴
とするサンプルホ―ルド回路。And 1. A operational amplifier having first and second inputs, - transferring input on a predetermined evening timing input signal to the end, the input signal when the on-off to the other end a first switch circuit, a first capacitive element connected between the first input terminal of the other end of the operational amplifier of the first switching circuit, - the other end receives a reference voltage at an end Is connected to a second input terminal of the operational amplifier, and is turned on and off at a predetermined timing to transmit the reference voltage to a second input terminal of the operational amplifier when it is turned on. A second capacitive element connected between a second input terminal of the amplifier and a reference potential point, and a predetermined timing connected between an output terminal of the operational amplifier and the other end of the first switch circuit; A third switch circuit which is turned on and off by the switch, an output terminal of the operational amplifier and a A fourth switch circuit that is connected between the input terminal and the first input terminal and that is turned on and off at a predetermined timing; and a third capacitor element connected in parallel with the third switch circuit. Characteristic sample-hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138110A JP2776058B2 (en) | 1991-06-11 | 1991-06-11 | Sample hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138110A JP2776058B2 (en) | 1991-06-11 | 1991-06-11 | Sample hold circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04362598A JPH04362598A (en) | 1992-12-15 |
| JP2776058B2 true JP2776058B2 (en) | 1998-07-16 |
Family
ID=15214190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3138110A Expired - Lifetime JP2776058B2 (en) | 1991-06-11 | 1991-06-11 | Sample hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2776058B2 (en) |
-
1991
- 1991-06-11 JP JP3138110A patent/JP2776058B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04362598A (en) | 1992-12-15 |
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