JP2773171B2 - Bipolar signal monitor circuit - Google Patents
Bipolar signal monitor circuitInfo
- Publication number
- JP2773171B2 JP2773171B2 JP63333385A JP33338588A JP2773171B2 JP 2773171 B2 JP2773171 B2 JP 2773171B2 JP 63333385 A JP63333385 A JP 63333385A JP 33338588 A JP33338588 A JP 33338588A JP 2773171 B2 JP2773171 B2 JP 2773171B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- differential amplifier
- output terminal
- input terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明はバイポーラ信号を送受信する通信機におい
てバイポーラ信号をモニタするためのバイポーラ信号モ
ニタ回路の改良に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a bipolar signal monitoring circuit for monitoring a bipolar signal in a communication device for transmitting and receiving a bipolar signal.
従来、バイポーラ信号モニタ回路で原信号をモニタす
る場合、バイポーラ信号モニタ回路が原信号に影響を与
えないように抵抗分割などの方法でその原信号の振幅を
10分の１程度に分圧してモニタしていた。Conventionally, when an original signal is monitored by a bipolar signal monitor circuit, the amplitude of the original signal is divided by a method such as resistance division so that the bipolar signal monitor circuit does not affect the original signal.
The pressure was monitored by reducing the pressure to about 1/10.
しかし、原信号の伝送距離が長い場合には原信号が振
幅変動および波形劣化を生じることになり、従来のバイ
ポーラ信号モニタ回路ではこのように劣化した原信号を
そのままモニタしていた。したがつて、このように劣化
した原信号をモニタしている場合、このバイポーラ信号
モニタ回路の出力信号の符号則を測定器で測定しても正
確な結果を得ることはできないという問題が生じてい
た。However, when the transmission distance of the original signal is long, the original signal causes amplitude fluctuation and waveform deterioration, and the conventional bipolar signal monitor circuit monitors the deteriorated original signal as it is. Therefore, when monitoring such a deteriorated original signal, there is a problem that an accurate result cannot be obtained even if the sign rule of the output signal of the bipolar signal monitor circuit is measured by a measuring instrument. Was.
この発明のバイポーラ信号モニタ回路は、反転出力端
子と非反転出力端子と入力端子とを有しかつこの入力端
子に正論理のユニポーラ信号が入力される第１の論理回
路と、非反転入力端子が第１の論理回路の非反転出力端
子に接続されるとともに反転入力端子が第１の論理回路
の反転出力端子に接続された第１の差動増幅回路と、反
転出力端子と非反転出力端子と入力端子とを有しかつこ
の入力端子に負論理のユニポーラ信号が入力される第２
の論理回路と、非反転入力端子が第２の論理回路の非反
転出力端子に接続されるとともに反転入力端子が第２の
論理回路の反転出力端子に接続された第２の差動増幅回
路と、一端が高電位電源に接続されるとともに他端が出
力端子に接続された負荷抵抗とを有し、第１の差動増幅
回路は反転入力端子にベースが接続された第１のトラン
ジスタを含み、第２の差動増幅回路は反転入力端子にベ
ースが接続された第２のトランジスタを含み、第１およ
び第２のトランジスタの各エミッタは低電位電源に共通
接続されるとともに第１および第２のトランジスタの各
コレクタは負荷抵抗の他端に共通接続されている。A bipolar signal monitor circuit according to the present invention includes a first logic circuit having an inverting output terminal, a non-inverting output terminal, and an input terminal, and a positive logic unipolar signal being input to the input terminal; A first differential amplifier circuit connected to a non-inverting output terminal of the first logic circuit and having an inverting input terminal connected to the inverting output terminal of the first logic circuit; an inverting output terminal and a non-inverting output terminal; And a second input terminal to which a negative-polarity unipolar signal is input.
A second differential amplifier circuit having a non-inverting input terminal connected to the non-inverting output terminal of the second logic circuit and an inverting input terminal connected to the inverting output terminal of the second logic circuit. A load resistor having one end connected to the high potential power supply and the other end connected to the output terminal, the first differential amplifier circuit includes a first transistor having a base connected to the inverting input terminal. , The second differential amplifier circuit includes a second transistor having a base connected to the inverting input terminal, and the emitters of the first and second transistors are commonly connected to a low-potential power supply and the first and second transistors are connected. Are commonly connected to the other end of the load resistor.
バイポーラ／ユニポーラ変換回路によつてバイポーラ
信号の正パルスおよび負パルスは正論理および負論理の
２つのユニポーラ信号に変換されて各々第１および第２
の論理回路の入力端子に入力される。The bipolar and unipolar conversion circuits convert the positive and negative pulses of the bipolar signal into two unipolar signals of positive logic and negative logic, respectively, and convert them into first and second unipolar signals, respectively.
Is input to the input terminal of the logic circuit.
正論理のユニポーラ信号が「Ｈ」、負論理のユニポー
ラ信号が「Ｈ」のとき、第１および第２の差動増幅回路
はともにオフとなるので、負荷抵抗に電流は流れない。When the positive logic unipolar signal is “H” and the negative logic unipolar signal is “H”, the first and second differential amplifier circuits are both turned off, so that no current flows through the load resistance.
正論理のユニポーラ信号が、「Ｌ」、負論理のユニポ
ーラ信号が「Ｈ」のとき、第１の差動増幅回路はオン、
第２の差動増幅回路はオフとなるので、負荷抵抗には第
１の差動増幅回路に相当する定電流が流れる。When the positive logic unipolar signal is “L” and the negative logic unipolar signal is “H”, the first differential amplifier circuit is on,
Since the second differential amplifier circuit is turned off, a constant current corresponding to the first differential amplifier circuit flows through the load resistance.
正論理のユニポーラ信号が「Ｌ」、負論理のユニポー
ラ信号が「Ｌ」のとき、第１および第２の差動増幅器は
ともにオンとなるので、負荷抵抗には第１および第２の
差動増幅回路に相当する定電流が流れる。When the positive-polarity unipolar signal is “L” and the negative-polarity unipolar signal is “L”, the first and second differential amplifiers are both turned on. A constant current corresponding to the amplifier circuit flows.
次にこの発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図はこの発明の一実施例を示す回路図、第２図は
同実施例における波形図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram in the embodiment.
１は入力された信号の非反転信号および反転信号をそ
れぞれ出力する非反転出力端子および反転出力端子を有
する第１の論理回路であり、OR/NORゲートG1からなる。
２はこれと同様にOR/NORゲートG2からなる第２の論理回
路である。Reference numeral 1 denotes a first logic circuit having a non-inverted output terminal and an inverted output terminal for outputting a non-inverted signal and an inverted signal of the input signal, respectively, and includes an OR / NOR gate G1.
Reference numeral 2 denotes a second logic circuit including an OR / NOR gate G2.
３はトランジスタTR1,TR2（TR2は第１のトランジスタ
である），および定電流Ｉ〔mA〕を流す定電流源I1から
なる第１の差動増幅器である。第１の差動増幅回路３の
非反転入力端子T1および反転入力端子T2はそれぞれ第１
の論理回路１の非反転出力端子および反転出力端子に接
続されている。定電流源I1の一端はトランジスタTR1,TR
2のエミッタに共通接続され、他端は負電源（低電位電
源）VEE［Ｖ］に接続されている。トランジスタTR1およ
びTR2の各ベースはそれぞれ第１の差動増幅器３の非反
転入力端子T1および反転入力端子T2に接続されている。Reference numeral 3 denotes a first differential amplifier including transistors TR1 and TR2 (TR2 is a first transistor) and a constant current source I1 for supplying a constant current I [mA]. The non-inverting input terminal T1 and the inverting input terminal T2 of the first differential amplifier circuit 3
Are connected to the non-inverting output terminal and the inverting output terminal of the logic circuit 1. One end of the constant current source I1 is connected to transistors TR1, TR
The other end is connected to a negative power supply (low potential power supply) V EE [V]. Each base of the transistors TR1 and TR2 is connected to the non-inverting input terminal T1 and the inverting input terminal T2 of the first differential amplifier 3, respectively.
４は第１の差動増幅回路３と同様に、トランジスタTR
3,TR4（TR4は第２のトランジスタである），および定電
流Ｉ〔mA〕を流す定電流源12からなる第２の差動増幅器
である。第２の差動増幅回路４の非反転入力端子T3およ
び反転入力端子T4はそれぞれ第２の論理回路２の非反転
出力端子および反転出力端子に接続されている。定電流
源12の一端はトランジスタTR3,TR4のエミッタに共通接
続され、他端は負電源VEE〔Ｖ〕に接続されている。ト
ランジスタTR3およびTR4の各ベースはそれぞれ第２の差
動増幅器４の非反転入力端子T3および反転入力端子T4に
接続されている。4 is a transistor TR similar to the first differential amplifier circuit 3.
3, a second differential amplifier comprising TR4 (TR4 is a second transistor) and a constant current source 12 for flowing a constant current I [mA]. The non-inverting input terminal T3 and the inverting input terminal T4 of the second differential amplifier circuit 4 are connected to the non-inverting output terminal and the inverting output terminal of the second logic circuit 2, respectively. One end of the constant current source 12 is commonly connected to the emitters of the transistors TR3 and TR4, and the other end is connected to a negative power supply V EE [V]. Each base of the transistors TR3 and TR4 is connected to the non-inverting input terminal T3 and the inverting input terminal T4 of the second differential amplifier 4, respectively.
５は一端が正電源（高電位電源）VCC［Ｖ］に接続さ
れ他端がトランジスタTR2,TR4の各コレクタ、および出
力端子Ｃに接続された抵抗Ｒ［ｋΩ］の負荷抵抗であ
る。Reference numeral 5 denotes a load resistance of a resistor R [kΩ] having one end connected to a positive power supply (high potential power supply) V CC [V] and the other end connected to the collectors of the transistors TR2 and TR4 and the output terminal C.
次に動作について説明する。いま、第２図（ａ）に示
すように正側V+に振れる正パルスおよび負側V_に振れる
負パルスからなるバイポーラ信号Ｂが図示しないバイポ
ーラ／ユニポーラ変換回路によつてユニポーラ信号に変
換される過程で、正パルスは正論理のユニポーラ信号U1
（第２図（ｂ））に変換され、負パルスは負論理のユニ
ポーラ信号U2（第２図（ｃ））に変換されたとする。そ
して、この２つのユニポーラ信号U1およびU2を第１図に
示すバイポーラ信号モニタ回路の入力端子ＡおよびＢを
介して論理回路１および２に入力する。Next, the operation will be described. Now, as shown in FIG. 2 (a), a bipolar signal B composed of a positive pulse swinging on the positive side V + and a negative pulse swinging on the negative side V_ is converted into a unipolar signal by a bipolar / unipolar conversion circuit (not shown). In the process, the positive pulse is a positive-polarity unipolar signal U1
(FIG. 2 (b)), and the negative pulse is converted into a negative logic unipolar signal U2 (FIG. 2 (c)). Then, these two unipolar signals U1 and U2 are input to logic circuits 1 and 2 via input terminals A and B of the bipolar signal monitor circuit shown in FIG.
ユニポーラ信号U1が「Ｈ」のとき、第１の論理回路１
によつて第１の差動増幅回路３の非反転入力端子T1には
「Ｈ」が、反転入力端子T2には「Ｌ」が出力されるの
で、TR1はオンしTR2はオフする。すなわち、第１の差動
増幅回路３はオフとなるため、TR2に電流は流れない。
これに対してユニポーラ信号U1が「Ｌ」のときは、第１
の論理回路１によつて第１の差動増幅回路３の非反転入
力端子T1には「Ｌ」が、反転入力端子T2には「Ｈ」が出
力されるので、TR1はオフしTR2はオンする。すなわち、
第１の差動増幅器３はオンとなるため、TR2には定電流
源I1によつて定電流Ｉ〔mA〕が流れる。When the unipolar signal U1 is "H", the first logic circuit 1
As a result, "H" is output to the non-inverting input terminal T1 and "L" is output to the inverting input terminal T2 of the first differential amplifier circuit 3, so that TR1 turns on and TR2 turns off. That is, since the first differential amplifier circuit 3 is turned off, no current flows through TR2.
On the other hand, when the unipolar signal U1 is "L", the first
The logic circuit 1 outputs "L" to the non-inverting input terminal T1 and "H" to the inverting input terminal T2 of the first differential amplifier circuit 3, so that TR1 is turned off and TR2 is turned on. I do. That is,
Since the first differential amplifier 3 is turned on, a constant current I [mA] flows through TR2 from the constant current source I1.
上記と同様に、ユニポーラ信号U2が「Ｈ」のとき、第
２の論理回路２によつて第２の差動増幅回路４はオフと
なるため、TR4に電流は流れない。これに対してユニポ
ーラ信号U2が「Ｌ」のとき、第２の論理回路２によつて
第２の差動回路４はオンとなるため、TR4には定電流源I
2によつて定電流Ｉ〔mA〕が流れる。Similarly to the above, when the unipolar signal U2 is "H", the second differential amplifier circuit 4 is turned off by the second logic circuit 2, so that no current flows through TR4. On the other hand, when the unipolar signal U2 is "L", the second differential circuit 4 is turned on by the second logic circuit 2, so that the constant current source I
2, a constant current I [mA] flows.
なお、バイポーラ信号Ｂの振動変動および波形劣化に
よつてユニポーラ信号U1およびU2が同様の信号劣化を生
じている場合、その信号劣化が第１および第２の論理回
路1,2の許容範囲内である限り第１および第２の差動増
幅回路3,4はオン，オフの動作を正常に行う。When the unipolar signals U1 and U2 have the same signal deterioration due to the oscillation fluctuation and waveform deterioration of the bipolar signal B, the signal deterioration is within the allowable range of the first and second logic circuits 1 and 2. As long as possible, the first and second differential amplifier circuits 3 and 4 perform on / off operations normally.
次に、第２図（ｂ）および（ｃ）に示すようなユニポ
ーラ信号U1およびU2が入力端子ＡおよびＢに入力した場
合の動作を３つに分けて考える。Next, the operation when unipolar signals U1 and U2 as shown in FIGS. 2 (b) and 2 (c) are input to input terminals A and B will be divided into three.
まず、第一にユニポーラ信号U1が「Ｈ」、U2が「Ｈ」
のとき、すなわちバイポーラ信号Ｂの正パルスに相当す
る信号が入力したときは、前述したように第１および第
２の差動増幅回路3,4はともにオフとなるので、トラン
ジスタTR2およびTR4に電流は流れないため、出力信号Ｍ
はVCC〔Ｖ〕となる（第２図（ｄ））。First, the unipolar signal U1 is "H" and U2 is "H".
In other words, when the signal corresponding to the positive pulse of the bipolar signal B is input, the first and second differential amplifier circuits 3 and 4 are both turned off as described above, and thus the current is supplied to the transistors TR2 and TR4. Does not flow, the output signal M
Becomes V CC [V] (FIG. 2 (d)).
第二にユニポーラ信号U1が「Ｌ」、U2が「Ｈ」のと
き、すなわちバイポーラ信号Ｂの無信号状態（GNDレベ
ル）に相当する信号が入力したときは、第１の差動増幅
回路３はオン、これに対して第２の差動増幅回路４はオ
フとなるので、トランジスタTR2には定電流Ｉ〔mA〕が
流れトランジスタTR4には電流が流れないため、負荷抵
抗５では電圧降下RI〔Ｖ〕が生じる。すなわち、出力信
号ＭはVCC−RI〔Ｖ〕となる（第２図（ｄ））。Second, when the unipolar signal U1 is "L" and U2 is "H", that is, when a signal corresponding to the no-signal state (GND level) of the bipolar signal B is input, the first differential amplifier circuit 3 On, on the other hand, the second differential amplifier circuit 4 is turned off, so that a constant current I [mA] flows through the transistor TR2 and no current flows through the transistor TR4. V]. That is, the output signal M becomes V CC -RI [V] (FIG. 2 (d)).
第三にユニポーラ信号U1が「Ｌ」、U2が「Ｌ」のと
き，すなちバイポーラ信号Ｂの負パルスに相当する信号
が入力したときは、第１および第２の差動増幅回路3,4
はともにオンとなるので、トランジスタTR2およびTS4に
は定電流Ｉ〔mA〕が流れるため、負荷抵抗５は電圧降下
2RI〔Ｖ〕が生じる。すなわち、出力信号ＭはVCC−2RI
〔Ｖ〕となる（第２図（ｄ））。Third, when the unipolar signal U1 is "L" and U2 is "L", that is, when a signal corresponding to the negative pulse of the bipolar signal B is input, the first and second differential amplifiers 3, 3 Four
Are both turned on, a constant current I [mA] flows through the transistors TR2 and TS4.
2RI [V] occurs. That is, the output signal M is V CC −2RI
[V] (FIG. 2 (d)).
以上説明したように出力端子Ｃに生じる出力信号Ｍ
は、バイポーラ信号Ｂと同じ位相関係を保つとともに所
定の電圧振幅を有するバイポーラ波形となる。As described above, the output signal M generated at the output terminal C
Is a bipolar waveform having the same phase relationship as the bipolar signal B and a predetermined voltage amplitude.
以上説明したようにこの発明では、原信号のバイポー
ラ信号が振幅変動および波形劣化を生じた場合、入力端
子に入力されるユニポーラ信号の劣化が第１および第２
の論理回路の許容範囲内であれば、第１および第２の差
動増幅回路が正常に動作するので、原信号のバイポーラ
信号と同じ位相関係を保つとともに所定の電圧振幅を有
するバイポーラ波形の出力信号を得ることが可能とな
る。As described above, according to the present invention, when the bipolar signal of the original signal undergoes amplitude fluctuation and waveform deterioration, the deterioration of the unipolar signal input to the input terminal is reduced by the first and second signals.
Is within the permissible range of the logic circuit, the first and second differential amplifier circuits operate normally, so that the output of the bipolar waveform having the predetermined voltage amplitude while maintaining the same phase relationship as the bipolar signal of the original signal is maintained. A signal can be obtained.
第１図はこの発明の一実施例を示す回路図、第２図は同
実施例における各信号の波形図である。 １……第１の論理回路、２……第２の論理回路、３……
第１の差動増幅回路、４……第２の差動増幅回路、５…
…負荷抵抗、VCC……正電源、VEE……負電源。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of each signal in the embodiment. 1 ... first logic circuit, 2 ... second logic circuit, 3 ...
A first differential amplifier circuit, 4... A second differential amplifier circuit, 5.
… Load resistance, V CC … Positive power supply, V EE …… Negative power supply.
Claims (1)
とを有しかつこの入力端子に正論理のユニポーラ信号が
入力される第１の論理回路と、 非反転入力端子が前記第１の論理回路の非反転出力端子
に接続されるとともに反転入力端子が前記第１の論理回
路の反転出力端子に接続された第１の差動増幅回路と、 反転出力端子と非反転出力端子と入力端子とを有しかつ
この入力端子に負論理のユニポーラ信号が入力される第
２の論理回路と、 非反転入力端子が前記第２の論理回路の非反転出力端子
に接続されるとともに反転入力端子が前記第２の論理回
路の反転出力端子に接続された第２の差動増幅回路と、 一端が高電位電源に接続されるとともに他端が出力端子
に接続された負荷抵抗とを有し、 前記第１の差動増幅回路は、前記第１の差動増幅回路の
反転入力端子にベースが接続された第１のトランジスタ
を含み、 前記第２の差動増幅回路は、前記第２の差動増幅回路の
反転入力端子にベースが接続された第２のトランジスタ
を含み、 前記第１および第２のトランジスタの各エミッタは低電
位電源に共通接続されるとともに前記第１および第２の
トランジスタの各コレクタは前記負荷抵抗の他端に共通
接続されることを特徴とするバイポーラ信号モニタ回
路。A first logic circuit having an inverted output terminal, a non-inverted output terminal, and an input terminal, to which a positive-polarity unipolar signal is input; and a non-inverted input terminal connected to the first logic circuit. A first differential amplifier circuit connected to a non-inverted output terminal of the logic circuit and having an inverted input terminal connected to the inverted output terminal of the first logic circuit; an inverted output terminal, a non-inverted output terminal, and an input terminal And a second logic circuit having a negative logic unipolar signal input to the input terminal thereof; a non-inverting input terminal connected to the non-inverting output terminal of the second logic circuit; A second differential amplifier circuit connected to an inverted output terminal of the second logic circuit, a load resistor having one end connected to a high potential power supply and the other end connected to an output terminal, The first differential amplifier circuit includes the first differential amplifier. A first transistor having a base connected to an inverting input terminal of the amplifier circuit, wherein the second differential amplifier circuit has a second transistor having a base connected to the inverting input terminal of the second differential amplifier circuit; A transistor, wherein the emitters of the first and second transistors are commonly connected to a low potential power supply, and the collectors of the first and second transistors are commonly connected to the other end of the load resistor. Characteristic bipolar signal monitor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63333385A JP2773171B2 (en) | 1988-12-28 | 1988-12-28 | Bipolar signal monitor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63333385A JP2773171B2 (en) | 1988-12-28 | 1988-12-28 | Bipolar signal monitor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02179055A JPH02179055A (en) | 1990-07-12 |
| JP2773171B2 true JP2773171B2 (en) | 1998-07-09 |
Family
ID=18265526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63333385A Expired - Lifetime JP2773171B2 (en) | 1988-12-28 | 1988-12-28 | Bipolar signal monitor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2773171B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS581364A (en) * | 1981-06-26 | 1983-01-06 | Fujitsu Ltd | Pulse output circuit |
-
1988
- 1988-12-28 JP JP63333385A patent/JP2773171B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02179055A (en) | 1990-07-12 |
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