JP2760047B2 - Emitter-coupled logic circuit - Google Patents
Emitter-coupled logic circuitInfo
- Publication number
- JP2760047B2 JP2760047B2 JP11772089A JP11772089A JP2760047B2 JP 2760047 B2 JP2760047 B2 JP 2760047B2 JP 11772089 A JP11772089 A JP 11772089A JP 11772089 A JP11772089 A JP 11772089A JP 2760047 B2 JP2760047 B2 JP 2760047B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- terminal
- transistor
- mos transistor
- channel mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Logic Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はエミッタ結合論理回路に関する。The present invention relates to an emitter-coupled logic circuit.
従来のエミッタ結合論理回路は、第２図に示すごと
く、第一の信号入力端子１を第一のNPN型トランジスタQ
1のベース電極に接続し、第二の信号入力端子２の第二
のNPN型トランジスタQ2のベース電極に接続し、第一の
抵抗素子R1の一方の端子を正電源（Ｇ）にまた他方の端
子をトランジスタQ1のコレクタ電極及び第一の信号出力
端子５に接続し、第二の抵抗素子R2の一方の端子を正電
源（Ｇ）にまた他方の端子をトランジスタQ2の一方の端
子を正電源（Ｇ）にまた他方の端子をトランジスタQ2の
コレクタ電源および第二の信号出力端子８に接続し、定
電流源10の電流入力端子をトランジスタQ1及びQ2のエミ
ッタ電極に接続し、定電流源10の電流出力端子を負電源
（−Ｅ）に接続した構成を有する。In a conventional emitter-coupled logic circuit, as shown in FIG. 2, a first signal input terminal 1 is connected to a first NPN transistor Q
Connected to the first base electrode is connected to a second second base electrode of the NPN transistor Q 2 of the signal input terminal 2, or the first one of the terminals of the resistance element R 1 to the positive supply (G) connect the other terminal to the collector electrode and the first signal output terminal 5 of the transistor Q 1, or one of the other terminal of the transistor Q 2 in the second one terminal of the resistor R 2 positive power supply (G) the terminals or other terminal to the positive power supply (G) connected to the collector power source and a second signal output terminal 8 of the transistor Q 2, the constant current source 10 emitter electrode current input terminals of the transistors Q 1 and Q 2 of And the current output terminal of the constant current source 10 is connected to a negative power supply (-E).
上述した従来のエミッタ結合論理回路では、信号出力
端子５あるいは８の出力が論理値“1"から“0"に変化す
る時には、トランジスタQ1（あるいはQ2）によって電流
を駆動するためその変化が速いが、“0"から“1"に変化
する時には、抵抗素子R1（あるいはR2）によって駆動す
るため、容量性負荷が接続されている場合、その変化に
時間がかかるという問題点がある。In conventional emitter coupled logic circuit described above, when the output of the signal output terminal 5 or 8 is changed from "0" to logic "1", the change to drive the current through the transistor Q 1 (or Q 2) is fast, but when changing from "1" to "0", for driving the resistive element R 1 (or R 2), if the capacitive load is connected, there is a problem that time the change takes .
本発明のエミッタ結合論理回路は、第一の信号入力端
子を第一のNPN型トランジスタのベース電極と第一のＰ
チャンネル型MOSトランジスタのゲート電極とに接続
し、第二の信号入力端子を第二のNPN型トランジスタの
ベース電極と第二のＰチャンネル型MOSトランジスタの
ゲート電極とに接続し、第一の抵抗素子の一方の端子を
正電源と前記第一のＰチャンネル型MOSトランジスタの
ソース電極とに接続し、該第一の抵抗素子の他方の端子
を前記第一のＰチャンネル型MOSトランジスタのドレイ
ン電極と前記第一のNPN型トランジスタのコレクタ電極
と第一の信号出力端子とに接続し、第二の抵抗素子の一
方の端子を正電源と前記第二のＰチャンネル型MOSトラ
ンジスタのソース電極とに接続し、該第二の抵抗素子の
他方の端子を前記第二のＰチャンネル型MOSトランジス
タのドレイン電極と第二のNPN型トランジスタのコレク
タ電極と第二の信号出力端子とに接続し、定電流源の電
流入力端子を前記第一及び第二のNPN型トランジスタの
エミッタ電極に接続し、該定電流源の電流出力端子を負
電源に接続した構成を有する。In the emitter-coupled logic circuit of the present invention, the first signal input terminal is connected to the base electrode of the first NPN transistor and the first PPN transistor.
A first resistor element connected to a gate electrode of the channel type MOS transistor, a second signal input terminal connected to a base electrode of the second NPN type transistor and a gate electrode of the second P channel type MOS transistor; Is connected to a positive power supply and the source electrode of the first P-channel MOS transistor, and the other terminal of the first resistance element is connected to the drain electrode of the first P-channel MOS transistor. A collector terminal of the first NPN transistor is connected to the first signal output terminal, and one terminal of the second resistor is connected to a positive power supply and a source electrode of the second P-channel MOS transistor. Connecting the other terminal of the second resistance element to the drain electrode of the second P-channel MOS transistor, the collector electrode of the second NPN transistor, and a second signal output terminal. Having a current input terminal of the constant current source connected to the emitter electrode of said first and second NPN type transistors, and connecting the current output terminal of the constant current source to the negative power supply configuration.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の回路図である。同図にお
いて、第２図と同じ構成をもつ回路の抵抗素子R1及びR2
の両端にはそれぞれＰチャンネル型のMOSトランジスタQ
3及びQ4のドレイン電極及びソース電極を接続してあ
り、MOSトランジスタQ3及びQ4のゲート電極はそれぞれ
信号入力端子１及び２に接続してある。FIG. 1 is a circuit diagram of one embodiment of the present invention. In the figure, the resistance elements R 1 and R 2 of the circuit having the same configuration as FIG.
P-channel type MOS transistor Q
3 and be connected to one drain electrode and source electrode of Q 4, the gate electrodes of the MOS transistors Q 3 and Q 4 is coupled to the signal input terminal 1 and 2.
本実施例の回路では、信号出力端子５（あるいは８）
の出力が論理値が“0"から“1"に変化する時には、MOS
トランジスタQ3あるいはQ4がオン状態となるので、容量
性負荷が接続されている場合でも、立ち上がり時間を速
めることが出来る。In the circuit of this embodiment, the signal output terminal 5 (or 8)
When the logical value of the output changes from “0” to “1”, the MOS
Since the transistor Q 3 or Q 4 is turned on, even when the capacitive load is connected, it is possible to accelerate the rise time.
以上説明したように本発明によれば、出力信号が論理
値“0"から“1"に変化する時間を従来回路よりも速める
ことが出来る。As described above, according to the present invention, the time when the output signal changes from the logical value “0” to “1” can be made faster than in the conventional circuit.
第１図は本発明の実施例の回路図、第２図は従来のエミ
ッタ結合論理回路を示す回路図である。 1,2……信号入力端子、5,8……信号出力端子、Q1〜Q4…
…トランジスタ、R1,R2……抵抗素子。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional emitter-coupled logic circuit. 1,2 …… Signal input terminal, 5,8 …… Signal output terminal, Q 1 to Q 4 …
... transistors, R 1 , R 2 ... resistance elements.
Claims (1)
ジスタのベース電極と第一のＰチャンネル型MOSトラン
ジスタのゲート電極とに接続し、第二の信号入力端子を
第二のNPN型トランジスタのベース電極と第二のＰチャ
ンネル型MOSトランジスタのゲート電極とに接続し、第
一の抵抗素子の一方の端子を正電源と前記第一のＰチャ
ンネル型MOSトランジスタのソース電極とに接続し、該
第一の抵抗素子の他方の端子を前記第一のＰチャンネル
型MOSトランジスタのドレイン電極と前記第一のNPN型ト
ランジスタのコレクタ電極と第一の信号出力端子とに接
続し、第二の抵抗素子の一方の端子を正電源と前記第二
のＰチャンネル型MOSトランジスタのソース電極とに接
続し、該第二の抵抗素子の他方の端子を前記第二のＰチ
ャンネル型MOSトランジスタのドレイン電極と第二のNPN
型トランジスタのコレクタ電極と第二の信号出力端子と
に接続し、定電流源の電流入力端子を前記第一及び第二
のNPN型トランジスタのエミッタ電極に接続し、該定電
流源の電流出力端子を負電源に接続した構成を有するこ
とを特徴とするエミッタ結合型論理回路。A first signal input terminal is connected to a base electrode of a first NPN transistor and a gate electrode of a first P-channel MOS transistor, and a second signal input terminal is connected to a second NPN transistor. A transistor is connected to a base electrode and a gate electrode of a second P-channel MOS transistor, and one terminal of the first resistor is connected to a positive power supply and a source electrode of the first P-channel MOS transistor. Connecting the other terminal of the first resistance element to the drain electrode of the first P-channel MOS transistor, the collector electrode of the first NPN transistor, and a first signal output terminal; One terminal of the resistance element is connected to a positive power supply and the source electrode of the second P-channel MOS transistor, and the other terminal of the second resistance element is connected to the drain of the second P-channel MOS transistor. Down electrode and a second NPN
The current input terminal of the constant current source is connected to the emitter electrode of the first and second NPN transistors, and the current output terminal of the constant current source is connected to the collector electrode of the type transistor and the second signal output terminal. An emitter-coupled logic circuit having a configuration in which is connected to a negative power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11772089A JP2760047B2 (en) | 1989-05-10 | 1989-05-10 | Emitter-coupled logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11772089A JP2760047B2 (en) | 1989-05-10 | 1989-05-10 | Emitter-coupled logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02295314A JPH02295314A (en) | 1990-12-06 |
| JP2760047B2 true JP2760047B2 (en) | 1998-05-28 |
Family
ID=14718626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11772089A Expired - Lifetime JP2760047B2 (en) | 1989-05-10 | 1989-05-10 | Emitter-coupled logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2760047B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008160304A (en) * | 2006-12-21 | 2008-07-10 | Nec Electronics Corp | Cml circuit |
| WO2013054474A1 (en) * | 2011-10-14 | 2013-04-18 | 旭化成エレクトロニクス株式会社 | Output buffer circuit |
-
1989
- 1989-05-10 JP JP11772089A patent/JP2760047B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02295314A (en) | 1990-12-06 |
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