JP2750119B2 - Ultrasonic thickness measuring device - Google Patents
Ultrasonic thickness measuring deviceInfo
- Publication number
- JP2750119B2 JP2750119B2 JP2168188A JP2168188A JP2750119B2 JP 2750119 B2 JP2750119 B2 JP 2750119B2 JP 2168188 A JP2168188 A JP 2168188A JP 2168188 A JP2168188 A JP 2168188A JP 2750119 B2 JP2750119 B2 JP 2750119B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- test material
- ultrasonic
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Length Measuring Devices Characterised By Use Of Acoustic Means (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は例えば探触子より超音波パルスを被検材へ
送信し、被検材からの反射パルス到達の時間より厚さを
測定する超音波厚さ測定装置。特に被検材内の多重反射
パルスを用いた測定に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a supersonic transmission that transmits an ultrasonic pulse from a probe to a test material and measures the thickness from the time of arrival of a reflected pulse from the test material. Sound wave thickness measuring device. In particular, the present invention relates to measurement using multiple reflection pulses in a test material.
［従来の技術］ 第３図は従来の超音波厚さ測定装置の一例を示すブロ
ック図、 図において、１は超音波パルス送信のタイミングを決
める同期パルスを発生する同期回路、２は同期パルスよ
り探触子を付勢する電気パルスを発生する送信回路、３
は超音波パルスの送受信を行う探触子、４は多重反射パ
ルスを受信増幅する受信回路、12は単位時間のクロック
パルスを発生する第２クロック回路、13はクロックパル
スを選択する第3AND回路、14は第3AND回路13の出力パル
スを計数する計数回路、15は計数結果を表示するデイジ
タル表示器、16は表面に油などのカプラントを塗布し探
触子３を接触させて厚さ測定する被検材、17は受信開始
の遅延ならびに利得制御信号を出力する制御回路、18は
多重反射パルスを表示するCRT表示器である。[Prior Art] FIG. 3 is a block diagram showing an example of a conventional ultrasonic thickness measuring apparatus. In the figure, reference numeral 1 denotes a synchronous circuit for generating a synchronous pulse for determining the timing of ultrasonic pulse transmission, and 2 denotes a synchronous pulse. A transmission circuit for generating an electric pulse for energizing the probe, 3
Is a probe that transmits and receives ultrasonic pulses, 4 is a receiving circuit that receives and amplifies multiple reflection pulses, 12 is a second clock circuit that generates a clock pulse for a unit time, 13 is a third AND circuit that selects a clock pulse, 14 is a counting circuit that counts the output pulses of the third AND circuit 13, 15 is a digital display that displays the counting result, 16 is a substrate that is coated with a couplant such as oil on the surface and the thickness of the probe 3 is measured by contacting the probe 3. An inspection material, 17 is a control circuit for outputting a delay of reception start and a gain control signal, and 18 is a CRT display for displaying multiple reflection pulses.
従来の超音波厚さ測定装置は上記のように構成され、 同期回路１出力の同期パルスにより探触子３から被検
材16へ送信された超音波パルスは、被検材16の表面と底
面との間において多重反射を行い、反射パルスは受信回
路４で受信されて第2FF11により多重反射パルス相互の
間Ｈレベルとなる測定ゲートが形成される、また反射パ
ルスはCRT表示器18へ表示される。The conventional ultrasonic thickness measuring apparatus is configured as described above. The ultrasonic pulse transmitted from the probe 3 to the test material 16 by the synchronization pulse output from the synchronization circuit 1 is applied to the surface and the bottom of the test material 16. The reflected pulse is received by the receiving circuit 4 and a second FF 11 forms a measurement gate which becomes H level between the multiple reflected pulses. The reflected pulse is displayed on the CRT display 18. You.
このとき制御回路17により受信利得の制御や遅延ゲー
トの調整が行われ不要信号の多重反射パルスへの混入を
抑制している。At this time, the control of the reception gain and the adjustment of the delay gate are performed by the control circuit 17, thereby suppressing the mixing of unnecessary signals into the multiple reflection pulses.
更にCRT表示器18の掃引線を調整し反射パルスの表示
位置や測定レンジの点検が行われている。Further, the sweep line of the CRT display 18 is adjusted to check the display position of the reflected pulse and the measurement range.
第４図に従来の超音波厚さ測定装置の動作波形を示
す、は送信パルスＴと被検材16底面からの最初の反射
の第１反射パルスB1と２回目の反射の第２反射パルス
B2、は第2FF11から出力される第１反射パルスB1と第
２反射パルスB2との時間間隔に比例した矩形信号の測定
ゲート、は測定ゲートと単位時間を示すクロックパル
スとの論理積出力パルスを示し、 この出力パルスが計数されてデイジタル表示器15に被
検材16の厚さ測定結果が表示される。Figure 4 shows the operation waveforms of a conventional ultrasonic thickness measuring device, the transmission pulse T and the second reflected pulse of the first first reflected pulse B 1 reflections and second reflections from the material being tested 16 bottom
B 2 is a measurement gate of a rectangular signal proportional to the time interval between the first reflection pulse B 1 and the second reflection pulse B 2 output from the second FF 11, and is the logical product of the measurement gate and a clock pulse indicating a unit time The output pulses are counted, and the output pulses are counted, and the result of measuring the thickness of the test material 16 is displayed on the digital display 15.
［発明が解決すべき課題］ 上記のような従来の超音波厚さ測定装置では、被検材
16内の多重反射パルスを選択するため、CRT表示器18を
付属してこれを監視しつつゲートを調整して雑音や不要
信号などの干渉妨害信号を抑制し、 更に反射パルスの表示位置や測定レンジの点検が行わ
れている。[Problems to be solved by the invention] In the conventional ultrasonic thickness measuring apparatus as described above,
In order to select multiple reflection pulses within 16, a CRT display 18 is attached and the gate is adjusted while monitoring this to suppress interference and other interference signals such as noise and unnecessary signals. A range check is being performed.
厚さ測定は第１反射パルスB1と第２反射パルスB2の時
間間隔よりなる測定ゲートを用いて行われるが、第２反
射バルスB2の検出はCRT表示において等間隔に表示され
る受信信号を目視で識別して選択されていた。The thickness measurement is performed using the measurement gate consisting time interval between the first reflected pulse B 1 and the second reflected pulse B 2, reception detection of the second reflecting BALS B 2 are displayed at equal intervals in the CRT display The signal was visually identified and selected.
また第１反射パルスB1の減衰振動や第１反射パルスB1
と第２反射パルスB2との間に発生する他の伝搬路を経た
遅れ信号などによって正常な測定が妨げられるという問
題点があった。The damping vibrations and first reflected pulse B 1 first reflected pulse B 1
When normal measured by such other channel delay signal subjected generated between the second reflected pulse B 2 it is disadvantageously hindered.
この発明はかかる問題点を解決するためになされたも
ので、CRT表示器18を用いることなく不要信号の除去が
自動的に行え、干渉妨害や雑音の少ない多重反射パルス
を用いた高精度の厚さ測定が行える小型、軽量の超音波
厚さ測定装置を得ることを目的とする。The present invention has been made to solve such a problem. Unnecessary signals can be automatically removed without using a CRT display 18, and a high-precision thickness using multiple reflection pulses with little interference and noise is used. It is an object of the present invention to obtain a small and lightweight ultrasonic thickness measuring device capable of measuring the thickness.
［課題を解決するための手段］ この発明に係る超音波厚さ測定装置は、超音波パルス
の送信時から第１反射パルスB1の到達までの時間と、第
１反射パルスB1から第２反射パルスB2までの時間がほぼ
等しいということに関連し、これらの時間を計測するた
めのアップダウンカウンタと、アップダウンカウンタの
計数値の所定量への到達を検出する検出回路と、検出時
から計数値が零になる間のゲートを出力するラッチ回路
と、ラッチ回路から出力されたゲートにより第２反射パ
ルスを通過させるAND回路を備えて、前記第１反射パル
スと前記第２反射パルスとの時間間隔より厚さ測定を行
うものである。[Means for Solving the Problems] An ultrasonic thickness measuring apparatus according to the present invention provides a time from the transmission of an ultrasonic pulse to the arrival of a first reflected pulse B 1 , and the time from the first reflected pulse B 1 to the second reflected pulse B 1 . time to reflected pulse B 2 is related to the fact that approximately equal, and the up-down counter for measuring these times, a detection circuit for detecting the arrival of a predetermined amount of count values of the up-down counter, upon detection A latch circuit that outputs a gate during which the count value becomes zero, and an AND circuit that passes the second reflection pulse by the gate output from the latch circuit, wherein the first reflection pulse and the second reflection pulse The thickness measurement is performed from the time interval of.
［作用］ この発明においては、超音波パルスの送信と同時にア
ップダウンカウンタはアップカウントの計数を開始し、
被検材底面からの第１反射パルスが検知された時ダウン
カウントに反転する。[Operation] In the present invention, the up / down counter starts counting up simultaneously with the transmission of the ultrasonic pulse,
When the first reflection pulse from the bottom surface of the test material is detected, the count is inverted to the down count.
ラッチ回路はアップダウンカウンタの計数値が零近傍
の所定量への到達を検知してラッチし、計数値が零に達
したとき解除される、この間にゲートを発生して被検材
底面からの第２反射パルスが選択できるので、受信信号
に含まれる雑音や不要信号の影響を避けることができ
る。The latch circuit latches when the count value of the up / down counter reaches a predetermined amount near zero, and is released when the count value reaches zero.During this time, a gate is generated to generate a gate from the bottom surface of the test material. Since the second reflection pulse can be selected, it is possible to avoid the influence of noise and unnecessary signals included in the received signal.
超音波パルスを送信してから第１反射パルスB1が受信
されるまでの時間 には探触子前面に設けられこれを保護する前面板や探触
子と被検材との間のカプラントに用いられる油膜などの
伝搬時間が含まれる。Time from the transmission of the ultrasonic pulse to the first reflected pulse B 1 is being received Includes the propagation time of a front plate provided on the front surface of the probe to protect the probe and an oil film used for a couplant between the probe and the test material.
一方、第１反射パルスB1と第２反射パルスB2との間の
時間 には上記時間が含まれないので、被検材内を超音波が往
復する時間のみよりなり の関係となる。On the other hand, the first reflected pulse B 1 and time between the second reflected pulse B 2 Since the above does not include the above time, it consists only of the time that the ultrasonic wave reciprocates in the test material. It becomes the relationship.
従って第２反射パルスB2は常にアップダウンカウンタ
の計数値が零に到達する以前に発生するので上記ゲート
により選択できる。Thus since the second reflected pulse B 2 always count value of the up-down counter occurs before reaching zero can be selected by the gate.
［実施例］ 本発明の一実施例を添付図を参照して詳細に説明す
る。Embodiment An embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第１図はこの発明の一実施例を示すブロック図であ
り、 図において、１〜４、11〜15は上記従来装置と同一で
ある。５はアップダウンカウンタ、６はアップダウンカ
ウンタ５の計数を制御する第1FF、７はアップダウンカ
ウンタ５へ一定周期のクロックパルスを与える第１クロ
ック回路、８はアップダウンカウンタ５の計数値を検出
する検出回路、９は検出回路８の出力をラッチしゲート
を発生するラッチ回路、10−１は第１反射パルスB1を選
択する第1AND回路、10−２は第２反射パルスB2を選択す
る第2AND回路を示している。FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numerals 1 to 4 and 11 to 15 are the same as those of the above-mentioned conventional apparatus. 5 is an up / down counter, 6 is a first FF for controlling the count of the up / down counter 5, 7 is a first clock circuit for applying a clock pulse of a fixed period to the up / down counter 5, and 8 is a count value of the up / down counter 5 detection circuit for a latch circuit 9 for generating a latch output of the detection circuit 8 gates, the 1AND circuit for selecting a first reflected pulse B 1 represents 10-1, selects the second reflected pulse B 2 10-2 2 shows a second AND circuit.
第２図は本装置の動作波形の一例を示し、は超音波
パルスのタイミングを決める同期パルス、は受信回路
４出力の送信パルスＴ、第１反射パルスB1、第２反射パ
ルスB2、不要信号Ｎ、は第1FF5出力信号、は第１ク
ロック回路７出力のクロックパルス、はアップダウン
カウンタ５の動作例、はラッチ回路９出力信号、は
第2FF11出力の測定ゲートを示している。FIG. 2 shows an example of an operation waveform of the present apparatus, wherein: is a synchronization pulse for determining the timing of an ultrasonic pulse; is a transmission pulse T output from the receiving circuit 4; a first reflection pulse B 1 , a second reflection pulse B 2 ; A signal N is a first FF5 output signal, is a clock pulse output from the first clock circuit 7, is an operation example of the up / down counter 5, is a latch circuit 9 output signal, and is a measurement gate of the second FF11 output.
上記のように構成された超音波厚さ測定装置におい
て、被検材16からの多重反射パルスを利用した厚さ測定
は、探触子３の構造に基づく内部の超音波伝搬の遅れ、
被検材16表面の塗膜ならびにカプラントに用いられる油
膜などの影響が避けられ、被検材16の表面と底面との間
の超音波パルスの伝搬時間に音速度校正を施すことによ
り行える。In the ultrasonic thickness measuring device configured as described above, the thickness measurement using the multiple reflection pulses from the test material 16 is performed based on the delay of the internal ultrasonic wave propagation based on the structure of the probe 3,
The influence of the coating film on the surface of the test material 16 and the oil film used for the couplant can be avoided, and the sound velocity can be calibrated to the propagation time of the ultrasonic pulse between the surface and the bottom surface of the test material 16.
同期回路１出力の同期パルスによって送信回路２が
励振され、探触子３から被検材16へ送信パルスＴが放射
されると同時に、第1FF6がセットされて、アップダウン
カウンタ５は第１クロック回路７のクロックパルスによ
りアップカウントを開始する。The transmitting circuit 2 is excited by the synchronizing pulse output from the synchronizing circuit 1, the transmitting pulse T is emitted from the probe 3 to the test material 16, and at the same time, the first FF6 is set, and the up-down counter 5 starts the first clock. The up-count is started by the clock pulse of the circuit 7.
被検材16の底面から最初に反射された第１反射パルス
B1は探触子３で受信され、受信回路４にて増幅されて第
1FF6をリセットすると同時に第1AND回路10−１を介して
第2FF11をセットする。First reflected pulse first reflected from the bottom surface of the test material 16
B 1 is received by the probe 3, amplified by the receiving circuit 4,
At the same time as resetting 1FF6, the second FF11 is set via the first AND circuit 10-1.
アップダウンカウンタ５は第1FF6出力によりダウンカ
ウントに転じると同時に、第1AND回路10−１のゲートは
閉じられ受信信号によって第2FF11は再びセットされる
ことはない。The up / down counter 5 starts counting down by the output of the first FF6, and at the same time, the gate of the first AND circuit 10-1 is closed, and the second FF11 is not set again by the received signal.
アップダウンカウンタ５のダウンカウントの計数値が
次第に零に接近し所定量に達すると検出回路８によって
検出され、ラッチ回路９にてラッチされ第2AND回路10−
２が開かれる。被検材16の底面からの第２反射パルスB2
が受信回路４から出力されると、第2AND回路10−２を介
して第2FF11をリセットする。When the count value of the down count of the up / down counter 5 gradually approaches zero and reaches a predetermined amount, the count value is detected by the detection circuit 8, latched by the latch circuit 9, and latched by the second AND circuit 10-.
2 is opened. Second reflected pulse B 2 from the bottom surface of the test material 16
Is output from the receiving circuit 4, the second FF 11 is reset via the second AND circuit 10-2.
このとき第１反射パルスB1と第２反射パルスB2との間
に発生する不要信号Ｎは、第2AND回路10−２が閉じてい
るのでこの回路にて阻止され第2FF11への干渉が避けら
れる。Unwanted signal N generated between the time the first reflected pulse B 1 and the second reflected pulse B 2 is interference avoiding to the 2AND circuit since 10-2 is closed is prevented by this circuit first 2FF11 Can be
アップダウンカウンタ５の計数値が零に達するとラッ
チ回路９は解除され第2AND回路10−２が閉じられて、そ
の後受信される信号はこの回路にて阻止される。When the count value of the up / down counter 5 reaches zero, the latch circuit 9 is released, the second AND circuit 10-2 is closed, and signals received thereafter are blocked by this circuit.
第2FF11出力には第１反射パルスB1と第２反射パルスB
2とにより形成される測定ゲートが得られ、第3AND回路1
3に加えられて第２クロック回路12からの単位時間より
なるクロックパルスを選択し、計数回路14にて計測され
被検材16の厚さがデイジタル表示器15へ表示される。The 2FF11 the output first reflected pulse B 1 and the second reflected pulse B
2 and a measurement gate formed by the third AND circuit 1
A clock pulse consisting of a unit time from the second clock circuit 12 is selected in addition to 3 and the thickness of the test material 16 measured by the counting circuit 14 is displayed on the digital display 15.
上記のとおり、第2AND回路10−２はラッチ回路９出力
により第２反射パルスB2の発生するタイミング近傍にて
ゲートが開かれるので、雑音や不要信号などの干渉妨害
信号が抑制されて確度の高い厚さ測定ができる。As described above, the 2AND circuit 10-2 since the gate at generation timing near the latch circuit 9 outputs the second reflected pulse B 2 is opened, the noise or unwanted signals, such as interference signal is suppressed in the accuracy of the High thickness measurement is possible.
本発明におけるアップダウンカウンタ５は積分回路に
置き換え、アナログ信号を用いた信号処理を行っても同
等の作用を行うことができる。The same operation can be performed even if the up / down counter 5 in the present invention is replaced with an integration circuit and performs signal processing using an analog signal.
［発明の効果］ この発明は以上説明したとおり、被検材からの第１反
射パルスにより反転するアップダウンカウンタと、ダウ
ンカウントにおいて所定量の計数値を検出する検出回路
と、検出出力をラッチするラッチ回路を設ける簡単な構
造により、 被検材の厚さに自動的に対応する第２反射パルスの受
信タイミングと一致するゲートが形成され、上記ゲート
により受信回路の利得が制御できるので、第２反射パル
スは選択受信される。[Effects of the Invention] As described above, the present invention latches up and down counters that are inverted by a first reflection pulse from a test material, a detection circuit that detects a predetermined amount of count values in a down count, and a detection output. With a simple structure in which the latch circuit is provided, a gate is formed which coincides with the reception timing of the second reflection pulse automatically corresponding to the thickness of the test material. The gain of the reception circuit can be controlled by the gate. The reflected pulse is selectively received.
従って、雑音や不要信号などの干渉妨害信号が抑制で
きて、第１反射パルスと第２反射パルスは所定レベルに
て受信され被検材の厚さ測定が再現性ならびに確度高く
行える。Therefore, interference and disturbance signals such as noise and unnecessary signals can be suppressed, and the first reflected pulse and the second reflected pulse are received at a predetermined level, and the thickness of the test material can be measured with high reproducibility and accuracy.
また多重反射パルスを用いた厚さ測定は探触子内にお
ける超音波パルスの伝搬遅れ、被検材表面の塗膜および
カプラントに用いられる油膜の影響が避けられて被検材
の厚さが正しく測定できるという効果がある。In addition, the thickness measurement using multiple reflection pulses prevents the propagation delay of the ultrasonic pulse in the probe, the effect of the coating film on the surface of the test material and the oil film used for the couplant, and corrects the thickness of the test material. It has the effect of being measurable.
第１図はこの発明の一実施例を示すブロック図、第２図
は本装置動作波形の一例、第３図は従来の超音波厚さ測
定装置の一例を示すブロック図、第４図は従来の超音波
厚さ測定装置の動作波形である。 図において、１は同期回路、２は送信回路、３は探触
子、４は受信回路、５はアップダウンカウンタ、６は第
1FF、７は第１クロック回路、８は検出回路、９はラッ
チ回路、10−１は第1AND回路、10−２は第2AND回路、11
は第2FF、12は第２クロック回路、13は第3AND回路、14
は計数回路、15はデイジタル表示器、16は被検材であ
る。 なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an example of an operation waveform of the present apparatus, FIG. 3 is a block diagram showing an example of a conventional ultrasonic thickness measuring apparatus, and FIG. 5 is an operation waveform of the ultrasonic thickness measuring device of FIG. In the figure, 1 is a synchronous circuit, 2 is a transmitting circuit, 3 is a probe, 4 is a receiving circuit, 5 is an up / down counter, and 6 is
1FF, 7 is a first clock circuit, 8 is a detection circuit, 9 is a latch circuit, 10-1 is a first AND circuit, 10-2 is a second AND circuit, 11
Is the second FF, 12 is the second clock circuit, 13 is the third AND circuit, 14
Is a counting circuit, 15 is a digital display, and 16 is a test material. In the drawings, the same reference numerals indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) G01B 17/02──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) G01B 17/02
Claims (1)
し、被検材内多重反射パルスの時間間隔より厚さ測定を
行う超音波厚さ測定装置において、 超音波パルス送信時から計数を開始し被検材底面よりの
第１反射パルスにてアップからダウンへ計数が反転する
アップダウンカウンタと、ダウンカウンタ時における所
定両の計数値を検出する検出回路と、該検出回路の検出
時から上記計数値が零になるまで出力をラッチしゲート
を出力するラッチ回路と、該ラッチ回路から出力された
ゲートにより受信信号を通過させるAND回路と、を備え
て、前記第１反射パルスとAND回路を通過した反射パル
スとの時間間隔より厚さ測定を行うことを特徴とする超
音波厚さ測定装置。1. An ultrasonic thickness measuring apparatus for transmitting an ultrasonic pulse from a probe to a test material and measuring a thickness from a time interval of a multiple reflection pulse in the test material. An up / down counter that starts counting and counts up from down with a first reflected pulse from the bottom surface of the test material, a detection circuit that detects both predetermined count values at the time of the down counter, and detection of the detection circuit A latch circuit that latches an output from the time until the count value becomes zero and outputs a gate, and an AND circuit that passes a received signal through the gate output from the latch circuit, and the first reflection pulse and An ultrasonic thickness measuring device, wherein a thickness is measured from a time interval between a reflected pulse passing through an AND circuit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168188A JP2750119B2 (en) | 1988-02-01 | 1988-02-01 | Ultrasonic thickness measuring device |
| US07/304,445 US5009103A (en) | 1988-02-01 | 1989-01-31 | Ultrasonic thickness measuring method and apparatus |
| DE3903396A DE3903396A1 (en) | 1988-02-01 | 1989-02-01 | Method and device for ultrasonic thickness measurement, and a test device for the latter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168188A JP2750119B2 (en) | 1988-02-01 | 1988-02-01 | Ultrasonic thickness measuring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01196504A JPH01196504A (en) | 1989-08-08 |
| JP2750119B2 true JP2750119B2 (en) | 1998-05-13 |
Family
ID=12061805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2168188A Expired - Lifetime JP2750119B2 (en) | 1988-02-01 | 1988-02-01 | Ultrasonic thickness measuring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2750119B2 (en) |
-
1988
- 1988-02-01 JP JP2168188A patent/JP2750119B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01196504A (en) | 1989-08-08 |
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