JP2738772B2 - Surface mount type electronic components - Google Patents
Surface mount type electronic componentsInfo
- Publication number
- JP2738772B2 JP2738772B2 JP2090994A JP9099490A JP2738772B2 JP 2738772 B2 JP2738772 B2 JP 2738772B2 JP 2090994 A JP2090994 A JP 2090994A JP 9099490 A JP9099490 A JP 9099490A JP 2738772 B2 JP2738772 B2 JP 2738772B2
- Authority
- JP
- Japan
- Prior art keywords
- lead terminals
- mold portion
- exposed
- mold
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体チップ等の部分を熱硬化性合成樹脂
製のモールド部で封止して成る電子部品のうち、面実装
に適するように構成したいわゆる面実装型の電子部品に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an electronic component formed by sealing a portion such as a semiconductor chip with a thermosetting synthetic resin mold portion so as to be suitable for surface mounting. The present invention relates to a so-called surface mounted electronic component.
従来、この種の面実装型の電子部品においては、その
複数本のリード端子を、半導体チップ等で封止する合成
樹脂製のモールド部における少なくとも一側面から、当
該一側面の長手方向に沿って適宜間隔で突出し、該各リ
ード端子を、前記モールド部の底面と略同一平面状に沿
うように屈曲して、この各リード端子を、プリント基板
におけるプリント配線に半田付けするように構成してい
ることは、殊更、文献を提示するまでもなく周知の通り
である。Conventionally, in this type of surface-mount type electronic component, the plurality of lead terminals are formed along at least one side surface of a synthetic resin molded portion that is sealed with a semiconductor chip or the like, along the longitudinal direction of the one side surface. Projected at appropriate intervals, the respective lead terminals are bent along substantially the same plane as the bottom surface of the mold portion, and the respective lead terminals are soldered to printed wiring on a printed circuit board. This is particularly well known without presenting any literature.
しかし、この電子部品において、そのモールド部を小
型化するためには、当該モールド部の側面から突出する
各リード端子の相互間における間隔を狭くすれば良い
が、その各リード端子は、モールド部の側面から突出し
ているから、各リード端子のプリント基板に対する半田
付けが確実にできているか否かの確認は容易にできる反
面、この各リード端子の相互間における間隔を狭くする
と、プリント基板に対する半田付けに際して、隣接する
リード端子の間において半田のブリッジ現象が発生する
ばかりか、前記各リード端子が、電子部品の取扱い中に
おいて外力を受けて少し変形するだけでも、隣接のリー
ド端子に接触すると言う問題が発生する。However, in this electronic component, in order to reduce the size of the molded part, the interval between the lead terminals protruding from the side surface of the molded part may be narrowed. Since it protrudes from the side, it is easy to check whether the soldering of each lead terminal to the printed board is easy.However, if the space between these lead terminals is narrowed, the soldering to the printed board is easy. In this case, not only a solder bridge phenomenon occurs between adjacent lead terminals, but also each lead terminal comes into contact with an adjacent lead terminal even if it is slightly deformed by an external force during handling of an electronic component. Occurs.
従って、前記各リード端子の相互間における間隔を狭
くすることには、一定の限界が存在するから、このこと
が、面実装型電子部品の小型化を妨げているのであっ
た。Therefore, there is a certain limit in reducing the interval between the lead terminals, and this has hindered the miniaturization of the surface mount electronic component.
本発明は、各リード端子のプリント基板に対する半田
付けが確実・強固にでき、且つ、この半田付けの確認が
容易にできる状態のもとで、各リード端子の相互間の間
隔を、前記のような半田のブリッジ現象や各リード端子
の接触を招来することなく、狭くできるようにした面実
装型の電子部品を提供することを目的とするものであ
る。According to the present invention, the soldering of each lead terminal to a printed circuit board can be reliably and firmly performed, and the distance between the lead terminals can be reduced as described above in a state where the soldering can be easily confirmed. It is an object of the present invention to provide a surface-mounted electronic component that can be made narrow without causing a bridging phenomenon of solder or contact between lead terminals.
この目的を達成するため本発明は、 「複数本のリード端子を、合成樹脂製のモールド部にお
ける少なくとも一側面に、当該一側面の長手方向に沿っ
て適宜間隔で配設して成る面実装型の電子部品におい
て、 前記各リード端子のうち一つおきに位置する各リード
端子を、前記モールド部の側面より突出して、この突出
端を、前記モールド部の底面と略同一平面状に沿うよう
に屈曲する一方、他の各リード端子を、前記モールド部
内に、当該他の各リード端子の下面が前記モールド部の
底面に同一平面状に露出し、当該他の各リード端子の先
端面がモールド部の側面に同一平面状に露出するように
露出するように埋設し、更に、前記モールド部の側面の
うち前記他の各リード端子に該当する部分に、当該他の
各リード端子の上面の一部を露出するようにした凹み部
を設ける。」 と言う構成にした。In order to achieve this object, the present invention provides a surface-mounted type in which a plurality of lead terminals are disposed on at least one side surface of a synthetic resin mold portion at appropriate intervals along the longitudinal direction of the one side surface. In the electronic component of (1), every other lead terminal among the respective lead terminals is protruded from the side surface of the mold portion, and the protruding end is substantially flush with the bottom surface of the mold portion. On the other hand, the other lead terminals are bent, and the lower surface of each of the other lead terminals is exposed to the same plane as the bottom surface of the mold portion in the mold portion. Embedded in the side surface of the mold so as to be exposed so as to be exposed in the same plane. Expose As in the recess provided with a. I was in the configuration to say. "
このように、モールド部の少なくとも一つの側面にお
ける各リード端子のうち一つおきに位置する各リード端
子を、前記モールド部の側面より突出して、この突出端
を、前記モールド部の底面と略同一平面状に沿うように
屈曲する一方、他の各リード端子を、前記モールド部内
に、当該他の各リード端子の下面が前記モールド部の底
面に同一平面状に露出し、当該他の各リード端子の先端
面がモールド部の側面に同一平面状に露出するように露
出するように埋設すると言う構成にしたことにより、前
記モールド部における少なくとも一つの側面に位置する
各リード端子は、このうち一つおきの各リード端子のみ
がモールド部の側面により突出した部位において一列に
並び、一方、他の各リード端子は、モールド部の側面か
ら突出していないと言う形態になるから、モールド部の
一つの側面における各リード端子の相互間の間隔を狭く
した場合において、各リード端子の間に半田のブリッジ
現象が発生すること、及び、各リード端子の僅かな変形
によってリード端子の接触が発生することを確実に回避
できるのである。As described above, each of the lead terminals located at every other one of the lead terminals on at least one side surface of the mold portion protrudes from the side surface of the mold portion, and this protruding end is substantially the same as the bottom surface of the mold portion. While being bent along the plane, each of the other lead terminals is exposed in the mold portion so that the lower surface of each of the other lead terminals is exposed on the bottom surface of the mold portion in the same plane. Is embedded so that the tip end surface of the mold portion is exposed so as to be exposed to the same plane on the side surface of the mold portion, so that each lead terminal located on at least one side surface of the mold portion has one of them. Only every other lead terminal is arranged in a line at the part protruding from the side surface of the mold part, while each other lead terminal does not protrude from the side surface of the mold part. Therefore, when the distance between the lead terminals on one side surface of the mold portion is reduced, a bridge phenomenon of solder occurs between the lead terminals, and a slight This prevents the contact of the lead terminals from occurring due to the deformation.
また、前記のように、モールド部における側面から突
出していない他の各リード端子は、その上面の一部がモ
ールド部の側面に設けた凹み部にて露出していることに
より、この他の各リード端子を、プリント基板等に対し
て確実・強固に半田付けすることができると共に、この
半田付け良否の確認が容易にできるのである。Further, as described above, each of the other lead terminals not protruding from the side surface of the mold portion has a part of the upper surface exposed by the concave portion provided on the side surface of the mold portion. The lead terminals can be securely and firmly soldered to a printed circuit board or the like, and the quality of the soldering can be easily checked.
従って、本発明によると、各リード端子のプリント基
板に対する半田付けが確実・強固にでき、且つ、この半
田付けの確認が容易にできる状態のもとで、各リード端
子の相互間の間隔を、各リード端子の相互間における半
田のブリッジ現象や各リード端子の接触を招来すること
なく、大幅に狭することができる効果を有する。Therefore, according to the present invention, the soldering of each lead terminal to the printed circuit board can be surely and firmly performed, and under the condition that the soldering can be easily confirmed, the interval between the respective lead terminals is reduced. There is an effect that the width can be significantly reduced without causing the solder bridge phenomenon between the lead terminals and the contact of the lead terminals.
以下、本発明の実施例を図面について説明すると、図
において符号１は、面実装型の集積回路（IC）を示し、
該集積回路１は、アイランド２に搭載した半導体チップ
３を封止する熱硬化性合成樹脂製のモールド部４と、前
記半導体チップ３に対する複数本のリード端子5,6,7,8,
9,10,11,12,13,14,15,16,17,18とから成り、前記各リー
ド端子5,6,7,8,9,10,11,12,13,14,15,16,17,18の半分の
各リード端子5,6,7,8,9,10,11は、前記モールド部４に
おける左右両側面4a,4bのうち右側面4aに、残りの半分
の各リード端子12,13,14,15,16,17,18は、前記モールド
部４における左側面4bに、当該左右両側面4a,4bの長手
方向に沿って適宜間隔Ｐで配設されている。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, reference numeral 1 indicates a surface-mounted integrated circuit (IC),
The integrated circuit 1 includes a mold portion 4 made of a thermosetting synthetic resin for sealing a semiconductor chip 3 mounted on an island 2, and a plurality of lead terminals 5, 6, 7, 8,
9,10,11,12,13,14,15,16,17,18, and the lead terminals 5,6,7,8,9,10,11,12,13,14,15,16 , 17,18, the lead terminals 5,6,7,8,9,10,11 are provided on the right side surface 4a of the left and right side surfaces 4a, 4b in the molding part 4, and the other half of each lead terminal The 12, 13, 14, 15, 16, 17, 18 are disposed on the left side surface 4b of the mold section 4 at appropriate intervals P along the longitudinal direction of the left and right side surfaces 4a, 4b.
そして、前記モールド部４の右側面4aにおける各リー
ド端子5,6,7,8,9,10,11のうち一つおきの各リード端子
5,7,9,11を、右側面4aから突出して、この突出端を前記
モールド部４における底面4cと略同一平面状に屈曲する
一方、前記一つおきの各リード端子5,7,9,11の間に位置
する他の各リード端子6,8,10を、前記モールド部４内
に、当該他の各リード端子6,8,10の下面がモールド４部
４における底面4cに同一平面状に露出し、当該他の各リ
ード端子6,8,10の先端面がモールド部４の右側面4aに同
一平面状に露出するように露出するように埋設する。And every other lead terminal among the respective lead terminals 5, 6, 7, 8, 9, 10, 11 on the right side surface 4a of the molded part 4
5, 7, 9 and 11 are projected from the right side surface 4a, and this projected end is bent in substantially the same plane as the bottom surface 4c of the mold part 4, while the alternate lead terminals 5, 7, and 9 are bent. , 11 and the other lead terminals 6, 8, and 10 are placed in the mold portion 4, and the lower surfaces of the other lead terminals 6, 8, and 10 are flush with the bottom surface 4c of the mold 4 portion 4. The other lead terminals 6, 8 and 10 are buried so as to be exposed on the right side surface 4a of the mold portion 4 so as to be exposed in the same plane.
更に、前記モールド部４の左側面4bにおける各リード
端子12,13,14,15,16,17,18のうち一つおきの各リード端
子12,14,16,18を、左側面4bから突出して、この突出端
を前記モールド部４における底面4cと略同一平面状に屈
曲する一方、前記一つおきの各リード端子12,14,16,18
の間に位置する他の各リード端子13,15,17を、前記モー
ルド部４内に、当該他の各リード端子13,15,17の下面が
モールド部４における底面4cに同一平面状に露出し、当
該他の各リード端子13,15,17の先端面がモールド部４の
左側面4bに同一平面状に露出するように露出するように
埋設する。Furthermore, every other lead terminal 12, 14, 16, 18 of each of the lead terminals 12, 13, 14, 15, 16, 17, 18 on the left side surface 4b of the molded portion 4 projects from the left side surface 4b. While this protruding end is bent in substantially the same plane as the bottom surface 4c of the mold part 4, the other lead terminals 12, 14, 16, 18
The other lead terminals 13, 15, 17 located between them are exposed in the mold portion 4 in such a manner that the lower surfaces of the other lead terminals 13, 15, 17 are flush with the bottom surface 4 c of the mold portion 4. Then, the other lead terminals 13, 15, 17 are embedded so as to be exposed on the left side surface 4b of the molded portion 4 so as to be exposed on the same plane.
また、前記モールド部４における左右両側面4a,4bの
うち、前記他の各リード端子6,8,10、13,15,17に該当す
る部分に、当該各リード端子6,8,10,13,15,17の上面を
一部だけ露出するようにした凹み部19,20を設ける。Further, of the left and right side surfaces 4a and 4b of the molded portion 4, the portions corresponding to the other lead terminals 6, 8, 10, 13, 15, and 17 are respectively provided with the respective lead terminals 6, 8, 10, 13 , 15, 17 are provided with recesses 19, 20 so that only the upper surfaces thereof are partially exposed.
このように構成すると、モールド部４における右側面
4aにおける各リード端子5,6,7,8,9,10,11は、このうち
一つおきの各リード端子5,7,9,11がモールド部４の右側
面4aにより突出した部位において一列に並ぶ一方、当該
一つおきの各リード端子5,7,9,11の間に位置する他の各
リード端子6,8,10は、モールド部４の右側面4aから突出
していないと言う形態になる。With this configuration, the right side surface of the mold section 4
Each lead terminal 5,6,7,8,9,10,11 in 4a is arranged in a line at a position where every other lead terminal 5,7,9,11 protrudes from the right side surface 4a of the molded part 4. While the other lead terminals 6, 8, 10 located between the alternate lead terminals 5, 7, 9, 11 do not protrude from the right side surface 4a of the molded part 4. become.
また、モールド部４における左側面4bにおける各リー
ド端子12,13,14,15,16,17,18も、このうち一つおきの各
リード端子12,14,16,18がモールド部４の左側面4bによ
り突出した部位において一列に並ぶ一方、当該一つおき
の各リード端子12,14,16,18の間に位置する他の各リー
ド端子13,15,17は、モールド部４の左側面4bから突出し
ていないと言う形態になる。Also, each of the lead terminals 12, 13, 14, 15, 16, 17, and 18 on the left side surface 4b of the molded part 4 is the other lead terminal 12, 14, 16, 18 of the left side of the molded part 4. While being lined up in a row at the portion protruding by the surface 4b, the other lead terminals 13, 15, 17 located between the alternate lead terminals 12, 14, 16, 18 are located on the left side surface of the molded part 4. 4b does not protrude.
すなわち、各リード端子5,6,7,8,9,10,11,12,13,14,1
5,16,17,18は、その一つおきにモールド部４における左
右両側面4a,4bから突出した形態になっているから、各
リード端子の相互間の間隔Ｐを狭くした場合において、
各リード端子の間に半田のブリッジ現象が発生するこ
と、及び、各リード端子の僅かな変形によってリード端
子の接触が発生することを確実に回避できるのである。That is, each lead terminal 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 1
5, 16, 17, 18 are formed so as to protrude from the left and right side surfaces 4a, 4b of the mold part 4 every other one, so that when the interval P between the lead terminals is reduced,
It is possible to reliably avoid the occurrence of a solder bridge phenomenon between the lead terminals and the occurrence of contact between the lead terminals due to slight deformation of each lead terminal.
更にまた、各リード端子のうちモールド部４における
左右両側面4a,4bから突出していない各リード端子6,8,1
0,13,15,17は、その上面の一部がモールド部４における
左右両側面4a,4bに設けた凹み部19,20にて露出している
から、この各リード端子6,8,10,13,15,17を、プリント
基板等に対して確実に、且つ、強固に半田付けすること
ができると共に、この半田付けの良否の確認が容易にで
きるのである。Furthermore, of the respective lead terminals, the respective lead terminals 6, 8, 1 which do not protrude from the left and right side surfaces 4a, 4b of the mold portion 4
0,13,15,17 have their upper surfaces partially exposed at the concave portions 19,20 provided on the left and right side surfaces 4a, 4b of the mold portion 4, so that the respective lead terminals 6,8,10 , 13, 15, and 17 can be securely and firmly soldered to a printed circuit board or the like, and the quality of the soldering can be easily confirmed.
なお、前記実施例は、多数本のリード端子を、モール
ド部における左右両側面に配設した場合を示したが、本
発明は、これに限らず、多数本のリード端子を、モール
ド部の一側面のみに配設するとか、或いは、モールド部
における四つの側面の全部に配設したクワッドタイプの
場合にも適用することができ、また、前記集積回路以外
の他の電子部品に対しても適用できることは言うまでも
ない。In the above-described embodiment, the case where a large number of lead terminals are disposed on both the left and right sides of the mold portion has been described. However, the present invention is not limited to this. It can be applied to only the side surface, or to the case of a quad type in which all four side surfaces of the mold portion are provided, and also applicable to other electronic components other than the integrated circuit. It goes without saying that you can do it.
図面は本発明の実施例を示し、第１図は平面図、第２図
は第１図のII−II視断面図、第３図は第１図のIII−III
視断面図、第４図は斜視図である。 １……集積回路、２……アイランド、３……半導体チッ
プ、４……モールド部、4a……モールド部の右側面、4b
……モールドの左側、 4c……モールドの底面、5,6,7,8,9,10,11,12,13,14,15,
16,17,18……リード端子、19,20……凹み部。1 is a plan view, FIG. 2 is a sectional view taken along the line II-II of FIG. 1, and FIG. 3 is a line III-III of FIG.
FIG. 4 is a perspective view. DESCRIPTION OF SYMBOLS 1 ... Integrated circuit, 2 ... Island, 3 ... Semiconductor chip, 4 ... Mold part, 4a ... Right side of mold part, 4b
…… Left side of mold, 4c …… Bottom of mold, 5,6,7,8,9,10,11,12,13,14,15,
16, 17, 18: Lead terminals, 19, 20: recess.
Claims (1)
ルド部における少なくとも一側面に、当該一側面の長手
方向に沿って適宜間隔で配設して成る面実装型の電子部
品において、 前記各リード端子のうち一つおきに位置する各リード端
子を、前記モールド部の側面より突出して、この突出端
を、前記モールド部の底面と略同一平面状に沿うように
屈曲する一方、他の各リード端子を、前記モールド部内
に、当該他の各リード端子の下面が前記モールド部の底
面に同一平面状に露出し、当該他の各リード端子の先端
面がモールド部の側面に同一平面状に露出するように露
出するように埋設し、更に、前記モールド部の側面のう
ち前記他の各リード端子に該当する部分に、当該他の各
リード端子の上面の一部を露出するようにした凹み部を
設けたことを特徴とする面実装型電子部品。1. A surface-mounted electronic component comprising a plurality of lead terminals disposed on at least one side surface of a synthetic resin molded portion at appropriate intervals along a longitudinal direction of the one side surface. Each lead terminal located every other one of the lead terminals protrudes from the side surface of the mold portion, and the protruding end is bent so as to be substantially flush with the bottom surface of the mold portion, while the other end is bent. In each of the lead terminals, the lower surface of each of the other lead terminals is exposed in the same plane on the bottom surface of the mold portion, and the tip surface of each of the other lead terminals is in the same plane on the side surface of the mold portion. Buried so as to be exposed so as to be exposed, and further, a portion of the upper surface of each of the other lead terminals is exposed at a portion corresponding to the other one of the lead terminals on the side surface of the molded portion. Provide a recess A surface-mounted electronic component characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2090994A JP2738772B2 (en) | 1990-04-05 | 1990-04-05 | Surface mount type electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2090994A JP2738772B2 (en) | 1990-04-05 | 1990-04-05 | Surface mount type electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03289162A JPH03289162A (en) | 1991-12-19 |
| JP2738772B2 true JP2738772B2 (en) | 1998-04-08 |
Family
ID=14014064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2090994A Expired - Fee Related JP2738772B2 (en) | 1990-04-05 | 1990-04-05 | Surface mount type electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2738772B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4314910A1 (en) * | 1993-05-05 | 1994-06-30 | Siemens Ag | Package for integrated circuit with pattern of coupling contacts |
| WO2003065452A1 (en) * | 2002-02-01 | 2003-08-07 | Infineon Technologies Ag | A lead frame |
| US7968998B1 (en) * | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
| US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
| TWI557183B (en) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | Siloxane resin composition, and photoelectric device employing the same |
| US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
| US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
| US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6061742U (en) * | 1983-09-30 | 1985-04-30 | 日本電気株式会社 | integrated circuit device |
| JPS60141148U (en) * | 1984-02-29 | 1985-09-18 | 日本電気株式会社 | semiconductor equipment |
| JPS6236548U (en) * | 1985-08-20 | 1987-03-04 |
-
1990
- 1990-04-05 JP JP2090994A patent/JP2738772B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03289162A (en) | 1991-12-19 |
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| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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| LAPS | Cancellation because of no payment of annual fees |