JP2720612B2 - Method of manufacturing thin film transistor array substrate - Google Patents
Method of manufacturing thin film transistor array substrateInfo
- Publication number
- JP2720612B2 JP2720612B2 JP5360591A JP5360591A JP2720612B2 JP 2720612 B2 JP2720612 B2 JP 2720612B2 JP 5360591 A JP5360591 A JP 5360591A JP 5360591 A JP5360591 A JP 5360591A JP 2720612 B2 JP2720612 B2 JP 2720612B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- substrate
- film
- film transistor
- transistor array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はアクティブマトリクス液
晶ディスプレイに用いられる薄膜トランジスタアレイ
〔以下、ＴＦＴ（Thin Film Transistor）と称する〕基
板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as TFT (Thin Film Transistor)) substrate used in an active matrix liquid crystal display.
【０００２】[0002]
【従来の技術】一般に液晶ディスプレイ等に用いられる
ＴＦＴ基板は透明絶縁体のガラス基板に各種素材の薄膜
を形成した後これを所要パターンに形成する工程を複数
回繰返すことにより行われる。そして、完成されたＴＦ
Ｔ基板は、ガラス基板の表面にゲートとしての導電性薄
膜と、ゲート絶縁膜としての絶縁性薄膜と、アモルファ
スシリコン薄膜と、ソース及びドレインとしての導電性
薄膜と、表示電極としての導電性薄膜が夫々積層状態に
形成されている。2. Description of the Related Art In general, a TFT substrate used for a liquid crystal display or the like is formed by forming a thin film of various materials on a transparent insulating glass substrate and then forming the thin film into a required pattern a plurality of times. And the completed TF
The T substrate has a conductive thin film as a gate, an insulating thin film as a gate insulating film, an amorphous silicon thin film, a conductive thin film as a source and a drain, and a conductive thin film as a display electrode on a surface of a glass substrate. Each is formed in a laminated state.
【０００３】[0003]
【発明が解決しようとする課題】ところで、この種のＴ
ＦＴ基板では、その製造に際してのＴＦＴ基板の搬送等
においてＴＦＴ基板の裏面に静電気が帯電することがあ
る。そして、この帯電した静電気により、ＴＦＴ素子側
にはガラス基板をキャパシタとして電荷が誘起される。
この静電気はガラス基板の全面において一様でなく分布
をもったものとなり、したがって素子側に誘起される電
荷も分布を持つことになり、ＴＦＴ素子面で電位差が発
生し、この電位差によってＴＦＴ素子に静電破壊が生じ
ることがあるという問題がある。本発明の目的はこのよ
うなＴＦＴ素子の静電破壊を防止したＴＦＴ基板の製造
方法を提供することにある。By the way, this kind of T
In the case of the FT substrate, static electricity may be charged on the back surface of the TFT substrate when the TFT substrate is transported during the manufacture thereof. Then, due to the charged static electricity, charges are induced on the TFT element side using the glass substrate as a capacitor.
This static electricity has a non-uniform distribution over the entire surface of the glass substrate, so that the electric charge induced on the element side also has a distribution, and a potential difference is generated on the TFT element surface. There is a problem that electrostatic breakdown may occur. An object of the present invention is to manufacture a TFT substrate in which such a TFT element is prevented from being electrostatically damaged.
It is to provide a method .
【０００４】[0004]
【課題を解決するための手段】本発明のＴＦＴ基板の製
造方法は、絶縁性基板の裏面に透明導電膜を形成する工
程と、前記透明導電膜及び前記絶縁性基板に対して２５
０℃でアニール処理を行う工程と、前記絶縁性基板の表
面に複数個のＴＦＴ素子を形成する工程を含んでいる。
この場合、液晶ディスプレイ等に用いるＴＦＴ基板で
は、前記絶縁性基板に透明ガラス基板を用い、裏面に形
成する前記透明導電膜に透明なＩＴＯ膜を形成する。According to a method of manufacturing a TFT substrate of the present invention, a step of forming a transparent conductive film on the back surface of an insulating substrate and a step of forming a transparent conductive film on the back surface of the insulating conductive substrate are performed by using a method of forming a transparent conductive film on the back surface of the insulating substrate.
A step of performing an annealing process at 0 ° C. and a step of forming a plurality of TFT elements on the surface of the insulating substrate.
In this case, the TFT substrate used in a liquid crystal display or the like, a transparent glass substrate to the insulating substrate to form a transparent ITO film on the transparent conductive film formed on the back surface.
【０００５】[0005]
【作用】本発明によれば、基板の裏面の導電膜によって
帯電する静電気の分布を均一にし、ＴＦＴ素子における
電位差の発生を防止して静電破壊を防止したＴＦＴ基板
の製造が実現される。また、前記導電膜をアニールする
ことでエッチングレートが低下され、ＴＦＴ素子を形成
する際にもエッチング除去されることが防止される。 According to the present invention, TFT substrate and a uniform distribution of the static electricity charged by the rear surface of the conductive film of the substrate, to prevent electrostatic breakdown and prevent the generation of the potential difference in the TFT element
Is realized. And annealing the conductive film.
This lowers the etching rate and forms a TFT element
Also, it is prevented from being removed by etching.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明にかかるＴＦＴ基板の断面図である。
ガラス基板１の表面には導電性薄膜によりゲート３が形
成され、その上にゲート絶縁膜４が形成される。又、こ
のゲート絶縁膜４上にはゲート３を覆うようにアモルフ
ァスシリコン膜５が形成され、その上には導電性薄膜に
よりドレイン６とソース７が形成されている。更に、前
記ゲート絶縁膜４上には液晶表示装置の表示電極を構成
する表示電極８が導電性薄膜により形成され、前記ソー
ス７に電気的に接続されている。Next, the present invention will be described with reference to the drawings. Figure 1 is a cross-sectional view of a TFT substrate according to the present invention.
A gate 3 is formed of a conductive thin film on the surface of the glass substrate 1, and a gate insulating film 4 is formed thereon. An amorphous silicon film 5 is formed on the gate insulating film 4 so as to cover the gate 3, and a drain 6 and a source 7 are formed thereon by a conductive thin film. Further, a display electrode 8 constituting a display electrode of the liquid crystal display is formed of a conductive thin film on the gate insulating film 4 and is electrically connected to the source 7.
【０００７】一方、前記ガラス基板１の裏面には透明で
かつ導電性の薄膜、この例では厚さ400ÅのＩｎ2 Ｏ5
・ＳｎＯ2 膜（以下、ＩＴＯ膜と称する）２を形成して
いる。このＩＴＯ膜２は前記表示電極８と同じ材料のも
のを用いることができ、この場合にはＩＴＯ膜２はガラ
ス基板１の表面側に形成するＴＦＴ素子の形成工程に先
立って形成され、形成後に約 250℃のアニール処理を行
っている。このアニールを行うことにより、その後の工
程において表示電極８としての厚さ 400ÅのＩＴＯ膜を
形成しかつこれをエッチングしたときにも、裏面側のＩ
ＴＯ膜２をアニール処理していることで、このＩＴＯ膜
２のエッチングレートが約１／10程度となり、表示電極
８を形成する際のエッチングによってもＩＴＯ膜２がエ
ッチング除去されることはない。On the other hand, the rear surface to the transparent and electrically conductive thin film of the glass substrate 1, an In 2 O 5 having a thickness of 400Å in this example
A SnO 2 film (hereinafter, referred to as an ITO film) 2 is formed. The ITO film 2 can be made of the same material as the display electrode 8. In this case, the ITO film 2 is formed prior to the step of forming a TFT element formed on the front side of the glass substrate 1, and after the formation, Annealed at about 250 ° C. By performing this annealing, an ITO film having a thickness of 400.degree. As the display electrode 8 is formed in a subsequent step, and when the ITO film is etched, the I.sub.
Since the TO film 2 is annealed, the etching rate of the ITO film 2 is reduced to about 1/10, and the ITO film 2 is not removed by etching even when the display electrode 8 is formed.
【０００８】したがって、このＴＦＴ基板では、裏面に
静電気が帯電した場合でも、ＩＴＯ膜２の導電性によっ
て帯電が一様化されることになり、表面のＴＦＴ素子に
誘起される電荷によって電位差が生じることはなく、Ｔ
ＦＴ素子の静電破壊を防止することが可能となる。Therefore, in this TFT substrate, even when static electricity is charged on the back surface, the charge is made uniform by the conductivity of the ITO film 2, and a potential difference is generated by the charge induced in the TFT element on the front surface. No, T
It is possible to prevent electrostatic breakdown of the FT element.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、ＴＦＴ素
子を形成した絶縁性基板の裏面に透明導電膜を形成し、
かつ２５０℃でアニール処理した上で絶縁性基板の表面
にＴＦＴ素子を形成しているので、帯電した静電気が一
様に分布するため、ＴＦＴ素子に電位差が生じることが
なく、ＴＦＴ素子の静電破壊を防止することができる効
果がある。また、前記導電膜をアニールすることでエッ
チングレートが低下され、ＴＦＴ素子を形成する際にも
エッチング除去されることが防止される。As described above, according to the present invention, a transparent conductive film is formed on the back surface of an insulating substrate on which a TFT element is formed ,
In addition, since the TFT element is formed on the surface of the insulating substrate after annealing at 250 ° C. , the charged static electricity is uniformly distributed. There is an effect that destruction can be prevented. Further, the annealing rate of the conductive film is reduced by annealing the conductive film, and the TFT is prevented from being removed even when the TFT element is formed.
【図１】本発明にかかる薄膜トランジスタアレイ基板の
一実施例の断面図である。FIG. 1 is a cross-sectional view of one embodiment of a thin film transistor array substrate according to the present invention.
１ ガラス基板 ２ ＩＴＯ膜（透明導電性基板） ３ ゲート ５ アモルファスシリコン膜 ６ ドレイン ７ ソース ８ 表示電極 Reference Signs List 1 glass substrate 2 ITO film (transparent conductive substrate) 3 gate 5 amorphous silicon film 6 drain 7 source 8 display electrode
Claims (2)
ジスタを配列形成してなる薄膜トランジスタアレイ基板
において、前記絶縁性基板の裏面に透明導電膜を形成す
る工程と、前記透明導電膜及び前記絶縁性基板に対して
２５０℃でアニール処理を行う工程と、前記絶縁性基板
の表面に前記複数個の薄膜トランジスタを形成する工程
を含むことを特徴とする薄膜トランジスタアレイ基板の
製造方法。A step of forming a transparent conductive film on the back surface of the insulating substrate in a thin film transistor array substrate having a plurality of thin film transistors arrayed on the surface of the insulating substrate ; A method for manufacturing a thin film transistor array substrate, comprising: a step of performing an annealing treatment on a substrate at 250 ° C .; and a step of forming the plurality of thin film transistors on a surface of the insulating substrate.
り、裏面に形成する前記透明導電膜は透明なＩＴＯ膜で
ある請求項１記載の薄膜トランジスタアレイ基板の製造
方法。2. The method according to claim 1, wherein the insulating substrate is a transparent glass substrate, and the transparent conductive film formed on the back surface is a transparent ITO film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5360591A JP2720612B2 (en) | 1991-02-27 | 1991-02-27 | Method of manufacturing thin film transistor array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5360591A JP2720612B2 (en) | 1991-02-27 | 1991-02-27 | Method of manufacturing thin film transistor array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04273166A JPH04273166A (en) | 1992-09-29 |
| JP2720612B2 true JP2720612B2 (en) | 1998-03-04 |
Family
ID=12947522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5360591A Expired - Lifetime JP2720612B2 (en) | 1991-02-27 | 1991-02-27 | Method of manufacturing thin film transistor array substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2720612B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4003842B2 (en) * | 1996-12-02 | 2007-11-07 | 大日本印刷株式会社 | Color filter and manufacturing method thereof |
| JP2005303262A (en) | 2004-03-18 | 2005-10-27 | Sharp Corp | Active matrix substrate, manufacturing method therefor, and display device |
| WO2016025320A1 (en) * | 2014-08-12 | 2016-02-18 | Corning Incorporated | Organic surface treatments for display glasses to reduce esd |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61161765A (en) * | 1985-01-11 | 1986-07-22 | Nec Corp | Manufacture of thin film transistor array |
| JPH03274027A (en) * | 1990-03-24 | 1991-12-05 | Seiko Epson Corp | Liquid crystal display device |
-
1991
- 1991-02-27 JP JP5360591A patent/JP2720612B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04273166A (en) | 1992-09-29 |
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