JP2709494B2 - Semiconductor element connection structure - Google Patents
Semiconductor element connection structureInfo
- Publication number
- JP2709494B2 JP2709494B2 JP1027298A JP2729889A JP2709494B2 JP 2709494 B2 JP2709494 B2 JP 2709494B2 JP 1027298 A JP1027298 A JP 1027298A JP 2729889 A JP2729889 A JP 2729889A JP 2709494 B2 JP2709494 B2 JP 2709494B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bump
- superelastic
- connection
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14143—Circular array, i.e. array with radial symmetry with a staggered arrangement, e.g. depopulated array
- H01L2224/14145—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、ICチップに代表される半導体素子と実装基
板の接続構造に関するものである。The present invention relates to a connection structure between a semiconductor element represented by an IC chip and a mounting board.
［従来の技術］ 従来の半導体素子のバンプによる接続方法の概略構造
を第５図に示す。図中の１は半導体素子、２は配線基
板、３は半導体素子または配線基板に構成されたはんだ
バンプ、４は半導体素子１と配線基板２の電極であり、
Ａ−Ａ′は半導体素子の中心を示している。[Prior Art] FIG. 5 shows a schematic structure of a conventional connection method of a semiconductor device using bumps. In the figure, 1 is a semiconductor element, 2 is a wiring board, 3 is a semiconductor element or a solder bump formed on the wiring board, 4 is an electrode of the semiconductor element 1 and the wiring board 2,
AA 'indicates the center of the semiconductor element.
接続は、はんだバンプ３を加熱溶融することにより行
われ、一括接続であるため、ワイヤ接続方法に比べて作
業性に優れ、またワイヤ接続及びTAB（TAPE AUTOMATED
BONDING）方法の如く、電極配置が半導体素子の周辺に
限定されるものと比較して、大幅に接続端子数を増やす
ことができるという特徴を持っている。The connection is performed by heating and melting the solder bumps 3 and is a collective connection. Therefore, the workability is superior to the wire connection method, and the wire connection and TAB (TAPE AUTOMATED) are performed.
It is characterized in that the number of connection terminals can be greatly increased as compared with the case where the electrode arrangement is limited to the periphery of the semiconductor element as in the case of the (BONDING) method.
しかしながら、この方法では、温度変化により、第６
図に示すような半導体素子１と配線基板２との熱膨張差
による寸法ずれＢが起こりはんだバンプ３にせん断歪が
生じ、接続信頼性が低下する。せん断歪は、はんだバン
プ３と半導体素子１の中心との距離の増加とともに増大
するため、はんだバンプ３の許容し得るせん断歪量から
はんだバンプ３を配置できる領域が制限され多端子化な
らびに大面積の半導体素子への適用が困難であった。ま
た、熱歪による応力が作用する方向は、実装基板の形状
が第２図に示すような場合、図中の矢印の方向となる。However, with this method, the sixth
As shown in the figure, a dimensional deviation B due to a difference in thermal expansion between the semiconductor element 1 and the wiring board 2 occurs, causing a shear strain in the solder bumps 3 and lowering connection reliability. Since the shear strain increases with an increase in the distance between the solder bump 3 and the center of the semiconductor element 1, the area where the solder bump 3 can be arranged is limited due to the allowable shear strain of the solder bump 3, so that the number of terminals is increased and the area is increased. Is difficult to apply to semiconductor devices. Further, the direction in which the stress due to thermal strain acts is the direction of the arrow in the figure when the shape of the mounting board is as shown in FIG.
このはんだバンプのせん断歪を低減させる手段とし
て、半導体素子と熱膨張係数の近い実装基板を用いる方
法が考えられるが、実装基板材料が限定されてしまうた
め、熱膨張係数の異なる材質の半導体ICを混載すること
ができない等の欠点がある。一方はんだバンプの高さを
高くしてせん断歪を低減させる手段が提案されている。
この手段としては、ポリイミドフィルムで支持したはん
だバンプを重ねることにより、多段バンプを形成する方
法（特開昭62−293730号公報）があるが、この方法で
は、はんだバンプを積み重ねるため、必要部材の増加、
製造工数増加にともなう価格上昇という問題がある。As a means of reducing the shear strain of the solder bumps, a method using a mounting substrate having a thermal expansion coefficient close to that of the semiconductor element can be considered.However, since the mounting substrate material is limited, a semiconductor IC having a different thermal expansion coefficient is used. There are drawbacks such as the inability to mix. On the other hand, means for increasing the height of the solder bump to reduce shear strain has been proposed.
As this means, there is a method of forming a multi-stage bump by laminating solder bumps supported by a polyimide film (Japanese Patent Application Laid-Open No. 62-293730). increase,
There is a problem of a price increase accompanying an increase in the number of manufacturing steps.
また、第７図は、はんだバンプを圧力で接触させて電
気的接続を得る半導体素子接続構造である。第７図にお
いて、半導体素子１と実装基板２のそれぞれの電極４上
にははんだバンプ３が形成されている。このはんだバン
プ３には樹脂５の硬化時の収縮力により圧力が加わり、
はんだバンプ３同士が機械的に接触し電気的接続が得ら
れる。FIG. 7 shows a semiconductor element connection structure in which solder bumps are brought into contact with each other by pressure to obtain electrical connection. In FIG. 7, solder bumps 3 are formed on the respective electrodes 4 of the semiconductor element 1 and the mounting substrate 2. Pressure is applied to the solder bumps 3 by the shrinkage force of the resin 5 during curing,
The solder bumps 3 are brought into mechanical contact with each other, and electrical connection is obtained.
しかしながら、この接続構造でははんだバンプ３の高
さがばらつくと電気的接続が得られない箇所が生ずる。
また、樹脂５の膨張係数ははんだバンプに比べて大きい
ため、温度変化が生じると圧力が弱まり、はんだバンプ
３の接触が不安定になるので、接続信頼性に欠けるとい
う問題があった。However, in this connection structure, if the height of the solder bumps 3 varies, there are places where electrical connection cannot be obtained.
In addition, since the expansion coefficient of the resin 5 is larger than that of the solder bumps, when the temperature changes, the pressure is weakened, and the contact of the solder bumps 3 becomes unstable.
［発明が解決しようとする課題］ 本発明では、上記の如き半導体素子と実装基板の間に
生じる大きなせん断歪み，バンプ高さのばらつき及び、
樹脂の熱膨張による圧力変動に対して電気的接続の信頼
性が高く、しかも微細な接続が可能で安価な半導体素子
接続構造を提供することを目的とする。[Problems to be Solved by the Invention] In the present invention, a large shear strain generated between the semiconductor element and the mounting board as described above, a variation in bump height, and
It is an object of the present invention to provide an inexpensive semiconductor element connection structure in which electrical connection is highly reliable with respect to pressure fluctuation due to thermal expansion of a resin, fine connection is possible, and inexpensive.
［課題を解決するための手段および作用］ 本発明は、半導体素子の金属電極と、実装基板の間
に、超弾性合金からなる突起電極（バンプ）を前記半導
体素子の金属電極と実装基板の間に生ずる熱応力と、超
弾性効果の能力の高い方向を合わせて、単独または、組
み合わせて形成し、加圧または、接合により接続させた
ことを特徴とする半導体素子接続構造を要旨とするもの
で、熱歪によって応力の生じる方向と超弾性合金バンプ
の超弾性効果の能力の高い方向を合わせることにより著
しい熱歪に対しても追従できるようにしている。Means and Action for Solving the Problems According to the present invention, a protruding electrode (bump) made of a superelastic alloy is provided between a metal electrode of a semiconductor element and a mounting board between the metal electrode of the semiconductor element and the mounting board. The gist of the present invention is a semiconductor element connection structure characterized by being formed alone or in combination with the direction of high thermal stress and the direction of high superelastic effect, and connected by pressing or joining. By matching the direction in which stress is generated by thermal strain with the direction in which the superelastic alloy bump has a high superelastic effect, it is possible to follow even significant thermal strain.
熱歪による応力が作用する方向は、実装基板が第２図
に示した形状の場合、図中の矢印の方向で著しいので、
この方向に超弾性効果の能力の高い方位を合わせる。ま
た、第７図に示すように半導体素子と実装基板をバンプ
により接続した後、樹脂の硬化時の収縮力によって素子
と基板を接続する方法においては、樹脂の熱膨張係数が
大きいため温度変化が起きて樹脂の収縮圧力が弱まって
も半導体素子に対して垂直方向に超弾性効果の能力の高
い方位の単結晶を組み合わせておけば、超弾性効果によ
る伸びで、垂直方向の熱歪に追従できる。The direction in which the stress due to thermal strain acts is remarkable in the direction of the arrow in the figure when the mounting board has the shape shown in FIG.
An azimuth with a high superelastic effect capability is set in this direction. Also, as shown in FIG. 7, in the method of connecting the semiconductor element and the mounting board by bumps and then connecting the element and the board by the shrinkage force at the time of curing of the resin, the resin has a large thermal expansion coefficient, so that the temperature changes. Even if the contraction pressure of the resin weakens and rises, the combination of a single crystal with a high direction of superelastic effect in the vertical direction with respect to the semiconductor element can follow the thermal strain in the vertical direction by elongation due to the superelastic effect. .
半導体素子側の金属電極、実装基板への超弾性合金の
接合及び、同種または異種の超弾性合金同士の接合は、
はんだまたは加熱超音波法を用いることにより行う。超
弾性効果の能力の高い方位として、Cu−Al−Niでは［01
1］方向,Ti−Niでは［111］方向,Ni−Alでは［001］方
向,Ag−Cdでは［011］方向,Cu−Zn−Caでは［011］方向
等を選ぶ。単結晶の作製は、例えば、種結晶からのエピ
タキシャル成長で、また集合組織の利用では例えば伸線
材を使う。The metal electrode on the semiconductor element side, the joining of the superelastic alloy to the mounting board, and the joining of the same or different superelastic alloys,
This is performed by using a solder or a heating ultrasonic method. As a direction having a high superelastic effect, Cu—Al—Ni has [01]
1] direction, [111] direction for Ti-Ni, [001] direction for Ni-Al, [011] direction for Ag-Cd, [011] direction for Cu-Zn-Ca, etc. A single crystal is produced, for example, by epitaxial growth from a seed crystal, and a texture is used, for example, by using a drawn wire.
このように、半導体素子と実装基板の熱膨張係数が著
しく異なる場合でも、半導体素子用接続バンプとして、
熱歪による応力が生じる方向と超弾性効果の能力の高い
方向とを一致させた超弾性合金を単独、または組み合わ
せて使うことにより、熱変形歪に対しても超弾性変形を
含めた弾性変形のみで補うことができ、外部歪に柔軟に
追従してバンプ材が破断しない信頼性の高い接続が実現
できる。Thus, even when the thermal expansion coefficients of the semiconductor element and the mounting board are significantly different, as a connection bump for the semiconductor element,
By using a superelastic alloy alone or in combination with the direction in which stress due to thermal strain is generated and the direction of high superelastic effect capability, only elastic deformation including superelastic deformation can be used for thermal deformation strain And a highly reliable connection in which the bump material is not broken by flexibly following external distortion can be realized.
［実施例］ 次に、本発明の実施例を図面に基づいて説明する。Example Next, an example of the present invention will be described with reference to the drawings.
実施例１ 第１図は、接続バンプが構成された半導体素子の断面
を示す。図中の１は半導体素子,2は実装基板,4は金属電
極,6は単結晶超弾性バンプを示す。Example 1 FIG. 1 shows a cross section of a semiconductor device having connection bumps. In the figure, reference numeral 1 denotes a semiconductor element, 2 denotes a mounting board, 4 denotes a metal electrode, and 6 denotes a single-crystal superelastic bump.
本発明の接続バンプ構成法を説明する。 The connection bump forming method of the present invention will be described.
１は半導体素子上に、金属電極（Al）４を形成し、そ
の上に柱状のCu−Al−Ni合金からなる単結晶超弾性バン
プ６を熱膨張による応力の予想される方向に合わせて、
前記Cu−Al−Ni合金の方位が［011］となるように設定
してから、はんだにより接合する。膨張による熱応力の
方向は、実装基板の構造にもよるが、第２図に示すよう
な構造の場合、熱応力の方向は図中の矢印の方向である
ため、バンプの結晶方位［011］をこれに合わせて第３
図のように配置する。第２図中の破線は、半導体素子の
置かれる位置を示している。同時に、配線基板にも同様
の方法で接合する。なお、Cu−Al−Ni合金の組成は、室
温以上の温度で超弾性を示すCu−14wt％Al−4wt％Niを
選んでいる。このような構造にすることにより、本超弾
性バンプは、水平方向のせん断歪で10％の弾性変形を有
し、０〜150℃の温度サイクルを1000回繰り返しても電
気的接触は維持された。1 is to form a metal electrode (Al) 4 on a semiconductor element, and to place a single crystal super-elastic bump 6 made of a columnar Cu-Al-Ni alloy on the metal electrode (Al) 4 in accordance with the expected direction of stress due to thermal expansion.
After setting the orientation of the Cu-Al-Ni alloy to be [011], it is joined by solder. The direction of the thermal stress due to expansion depends on the structure of the mounting board, but in the case of the structure shown in FIG. 2, since the direction of the thermal stress is the direction of the arrow in the figure, the crystal orientation of the bump [011] The third
Arrange them as shown. The broken line in FIG. 2 indicates the position where the semiconductor element is placed. At the same time, it is joined to the wiring board in the same manner. The composition of the Cu-Al-Ni alloy is selected from Cu-14wt% Al-4wt% Ni, which exhibits superelasticity at a temperature higher than room temperature. By adopting such a structure, the present superelastic bump has an elastic deformation of 10% due to a shear strain in the horizontal direction, and the electrical contact is maintained even when the temperature cycle of 0 to 150 ° C. is repeated 1000 times. .
実施例２ 第４図（ａ），（ｂ）に、単結晶超弾性バンプを組み
合わせて使用する場合の実施例を示す。１は半導体素
子,2は実装基板,4は金属電極,6と７は超弾性バンプであ
る。１のシリコン基板上に、金属電極（Al）４を形成
し、その上に柱状の［011］単結晶Cu−Al−Ni合金から
なる超弾性バンプ６を第３図に示したように水平方向の
膨張による熱応力の予想される方向に接合、形成する。
Cu−Al−Ni合金の組成は、室温以上の温度で超弾性を示
すCu−14wt％Al−4wt％Niを選んでいる。また、２の配
線基板上にも同じ成分の単結晶超弾性バンプ６を同様に
接合、形成する。両超弾性合金の間に柱状の［111］単
結晶Ti−Ni合金７を第４図（ａ）に示すように［111］
方向が半導体素子に垂直となるように置き、第４図
（ｂ）に示すように各バンプ同士が接触するようにして
樹脂５により接合する。Ti−Ni合金の組成は、室温以上
の温度で超弾性を示すTi−50.5at％Niを選んでいる。こ
のような構造にすることにより、このバンプは、半導体
素子に対して水平方向のせん断歪で10％、垂直方向のせ
ん断歪で12％の弾性変形を有し、いずれの方向の熱歪に
対しても、電気的接続の信頼性が高い半導体素子接続構
造が実現できた。本構造を用いて０〜150℃の温度サイ
クルを1000回繰り返しても、電気的接触は維持された。Embodiment 2 FIGS. 4 (a) and 4 (b) show an embodiment in which a single crystal superelastic bump is used in combination. 1 is a semiconductor element, 2 is a mounting board, 4 is a metal electrode, and 6 and 7 are superelastic bumps. A metal electrode (Al) 4 is formed on a silicon substrate 1 and a columnar [011] single crystal Cu-Al-Ni alloy superelastic bump 6 is formed on the metal electrode (Al) 4 in the horizontal direction as shown in FIG. Bonding and forming in the direction in which thermal stress is expected due to the expansion of the material.
As the composition of the Cu-Al-Ni alloy, Cu-14wt% Al-4wt% Ni, which exhibits superelasticity at a temperature higher than room temperature, is selected. Also, the single crystal superelastic bumps 6 of the same components are similarly bonded and formed on the second wiring board. A columnar [111] single crystal Ti—Ni alloy 7 is interposed between the two superelastic alloys as shown in FIG.
It is placed so that the direction is perpendicular to the semiconductor element, and is joined by the resin 5 so that the bumps are in contact with each other as shown in FIG. 4 (b). As the composition of the Ti-Ni alloy, Ti-50.5at% Ni, which exhibits superelasticity at a temperature higher than room temperature, is selected. By adopting such a structure, this bump has an elastic deformation of 10% in the horizontal shear strain and 12% in the vertical shear strain with respect to the semiconductor element, and is resistant to thermal strain in any direction. However, a semiconductor element connection structure with high reliability of electrical connection was realized. Even when the temperature cycle of 0 to 150 ° C. was repeated 1000 times using this structure, the electrical contact was maintained.
［発明の効果］ 以上の如く本発明は、半導体素子接続用バンプとし
て、単結晶の超弾性合金、または集合組織など特定の結
晶方位を持つ超弾性合金を単独または、組み合わせて使
用し、熱歪による応力の生ずる方向と超弾性バンプの回
復能力の高い方向を合わせることにより著しい熱歪に対
しても追従できることを特徴としている。本バンプを用
いて、半導体素子と基板電極を接続することにより、温
度変化で生じる熱歪による破断とバンプ高さのばらつき
に対して信頼性の高い半導体素子の接合が可能となっ
た。[Effects of the Invention] As described above, the present invention uses a single crystal superelastic alloy or a superelastic alloy having a specific crystal orientation such as a texture alone or in combination as a bump for connecting a semiconductor element, By setting the direction in which the stress is generated by the direction of the superelastic bump and the direction in which the recovery capability of the superelastic bump is high, it is possible to follow a remarkable thermal strain. By connecting the semiconductor element and the substrate electrode using the present bump, it is possible to join the semiconductor element with high reliability against breakage due to thermal strain caused by temperature change and variation in bump height.
第１図と第４図は、単結晶超弾性バンプを単独および組
み合わせて用いた場合の半導体素子接続構造の断面図で
あり、図中の矢印は超弾性効果の能力の高い単結晶の結
晶方位を示す。第２図は、金属電極と半導体素子の置か
れる位置を示す平面図、第３図は、半導体素子の電極位
置に付けたバンプの配置と単結晶の方位を示す平面図で
ある。第５図〜第７図は、従来のはんだバンプにより接
続された半導体素子と配線基板の断面図であり、第５図
は、正常の状態を示す説明図、第６図は、温度変化によ
り配線基板が膨張し、バンプにせん断歪みが導入された
様子を示す説明図、第７図は、はんだバンプを圧力で接
触させて、樹脂で固めた場合の半導体素子構造の断面図
である。 １……半導体素子、２……実装基板又は配線基板、 ３……はんだバンプ、４……金属電極、５……樹脂、 6,7……単結晶超弾性バンプ。1 and 4 are cross-sectional views of a semiconductor element connection structure when single crystal superelastic bumps are used alone or in combination. The arrows in the figures indicate the crystal orientation of a single crystal having a high superelastic effect. Is shown. FIG. 2 is a plan view showing a position where a metal electrode and a semiconductor element are placed, and FIG. 3 is a plan view showing an arrangement of bumps and an orientation of a single crystal provided at an electrode position of the semiconductor element. 5 to 7 are cross-sectional views of a conventional semiconductor element and a wiring board connected by solder bumps. FIG. 5 is an explanatory view showing a normal state, and FIG. FIG. 7 is an explanatory view showing a state where the substrate has expanded and shear strain has been introduced to the bumps. FIG. 7 is a cross-sectional view of a semiconductor element structure in a case where solder bumps are brought into contact with each other by pressure and solidified with resin. DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Mounting board or wiring board, 3 ... Solder bump, 4 ... Metal electrode, 5 ... Resin, 6,7 ... Single crystal super elastic bump.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大関 芳雄 神奈川県川崎市中原区井田1618番地 新 日本製鐵株式會社第１技術研究所内 (72)発明者 渡辺 敬介 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 金森 孝史 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 井口 泰男 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (56)参考文献 特開 平２−137240（ＪＰ，Ａ) 特開 昭57−163919（ＪＰ，Ａ) 特開 平１−192125（ＪＰ，Ａ) 特開 平２−180036（ＪＰ，Ａ) 特開 平２−185050（ＪＰ，Ａ) 特開 平２−206124（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshio Ozeki 1618 Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture New Nippon Steel Corporation 1st Technical Research Institute (72) Inventor Keisuke Watanabe 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (72) Inventor Takashi Kanamori 1-7-1, Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Yasuo Iguchi 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (56) References JP-A-2-137240 (JP, A) JP-A-57-163919 (JP, A) JP-A-1-192125 (JP, A) JP 2-180036 (JP, A) JP-A-2-185050 (JP, A) JP-A-2-206124 (JP, A)
Claims (1)
に、超弾性合金からなる突起電極（バンプ）を、前記半
導体素子の金属電極と実装基板の間に生ずる熱応力を緩
和するように、超弾性効果の能力の高い方向を合わせ
て、単独または、組み合わせて形成し、加圧または、接
合により接続させたことを特徴とする半導体素子接続構
造。A protruding electrode (bump) made of a superelastic alloy is provided between a metal electrode of a semiconductor element and a mounting substrate so as to reduce thermal stress generated between the metal electrode of the semiconductor element and the mounting substrate. A semiconductor element connection structure characterized in that they are formed singly or in combination with directions having high superelastic effects, and are connected by pressing or joining.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027298A JP2709494B2 (en) | 1989-02-06 | 1989-02-06 | Semiconductor element connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027298A JP2709494B2 (en) | 1989-02-06 | 1989-02-06 | Semiconductor element connection structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02206139A JPH02206139A (en) | 1990-08-15 |
| JP2709494B2 true JP2709494B2 (en) | 1998-02-04 |
Family
ID=12217185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1027298A Expired - Fee Related JP2709494B2 (en) | 1989-02-06 | 1989-02-06 | Semiconductor element connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2709494B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013013204A3 (en) * | 2011-07-21 | 2013-03-14 | Qualcomm Incorporated | Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2570626B2 (en) * | 1994-08-31 | 1997-01-08 | 日本電気株式会社 | Board connection structure and connection method |
| FR2736569B1 (en) * | 1995-07-13 | 1997-08-08 | Thomson Csf | CONNECTION DEVICE AND CONNECTION METHOD |
| JP4236778B2 (en) * | 1999-11-01 | 2009-03-11 | 株式会社ルネサステクノロジ | Semiconductor device |
-
1989
- 1989-02-06 JP JP1027298A patent/JP2709494B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013013204A3 (en) * | 2011-07-21 | 2013-03-14 | Qualcomm Incorporated | Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress |
| US9184144B2 (en) | 2011-07-21 | 2015-11-10 | Qualcomm Incorporated | Interconnect pillars with directed compliance geometry |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02206139A (en) | 1990-08-15 |
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